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1
Su, Lisa T. (Lisa Tzu-Feng). "Extreme-submicrometer silicon-on-insulator (SOI) MOSFETs." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/11618.
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De, Luca Andrea. "SOI smart multi-sensor platform for harsh environment applications." Thesis, University of Cambridge, 2016. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.709510.
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Wainwright, Simon Peter. "A study of silicon on insulator (SOI) : materials, devices and circuits." Thesis, University of Liverpool, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.338453.
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Sherony, Melanie J. (Melanie Jane). "Design, process, and reliability considerations in silicon-on-insulator (SOI) MOSFETs." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/10049.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 111-119
by Melanie J. Sherony.
Ph.D.
5
Zissis, Nikolaos. "Design and study of an electron beam system for silicon recrystallization." Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241194.
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Ngwa, Chrisantus Soh. "Electrical characterisation of SIMOX SiOâ†2 for silicon-on-insulator technology." Thesis, University of Liverpool, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.263706.
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Md, Zain Ahmad Rifqi. "One-dimensional photonic crystal / photonic wire cavities based on silicon-on-insulator (SOI)." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/996/.
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It has been of major interest in recent research to produce faster optical processing for many telecommunications applications, as well as other applications of high performance optoelectronics. The combination of one-dimensional photonic crystal structures (PhC) and narrow photonic wire (PhW) waveguides in high refractive-index contrast materials such as silicon-on-insulator (SOI) is one of the main contenders for provision of various compact devices on a single chip. This development is due to the ability of silicon technology to support monolithic integration of optical interconnects and form fully functional photonic devices incorporated into CMOS chips. The high index contrast of the combination of a silicon core with a surrounding cladding of silica and/or air provides strong optical confinement, leading to the realization of more compact structures and small device volumes. In order to obtain a wide range of device functionality, the reduction of propagation losses in narrow wires is equally important, although there are still performance limitations determined by fabrication processes. Compact single-row PhC structures embedded in PhW waveguide micro-cavities could become essential components for wavelength selective devices, especially for possible application in WDM systems. The high quality factor, Q, and confinement of light in a small volume, V, are important for optical signal processing and filtering purposes, implying large Purcell factor values. In this thesis, one-dimensional photonic crystal/photonic wire micro-cavities have been designed and modeled using both 2D and 3D versions of the finite-difference time-domain (FDTD) approach. These devices were fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) for patterning of the silicon layer. The device structures were characterized with TE polarized light, using a tunable laser covering the range from 1480 nm to 1585 nm. Single-row periodic hole-type PhC mirrors consisting of identical and equally spaced holes were embedded in 500 nm wire waveguides. Two PhC hole mirrors were separated with a cavity spacer varying from 400 nm to 500 nm in length to form a micro-cavity. In contrast, several different cavity arrangements were also successfully investigated, - i.e. extended cavity and coupled micro-cavity structures. The experimental results on photonic crystal/photonic wire micro-cavity structures have demonstrated that further enhancement of the quality-factor (Q-factor) - up to approximately 149,000 at wavelengths in the fibre telecommunications range is possible. The Q factor values and the useful transmission levels achieved are due, in particular, to the combination of both tapering within and outside the micro-cavity, with carefully designed hole diameters and non-periodic hole placement within the tapered sections. On the other hand, a large resonance quality factor of approximately 18,500, together with high normalized transmission of 85% through the use of tapering on both sides of the hole-type PhC mirrors that formed the micro-cavity, has been obtained. For the extended cavity case, the multiple resonances excited within the stop band, together with substantial tuning capability of the resonances obtained by varying the cavity length has been demonstrated, together with a Q-factor value of approximately 74,000 at the selected resonance frequency with a normalised transmission of 40%. In addition, the coupled micro-cavity structures considered in this thesis have formed the basic building block for designing multiple cavity structures where the combination of several cavities splits the selected single cavity resonance frequency into a number of resonances that depends directly on the number of cavities used in the design. The coupling strength between the resonators and the Free Spectral Range (FSR) between the split resonance frequencies of the coupled cavity combination were controlled via the use of different numbers of periodic hole structures – and through the use of different aperiodic hole taper arrangements between the two cavities in the middle section of the mirrors.
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Heinle, Ulrich. "Vertical High-Voltage Transistors on Thick Silicon-on-Insulator." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3179.
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More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silicon-on-Insulator (SOI) substrates. MOSFETs possess a number of features which makes them indispensable for Power Integrated Circuits (PICs): high switching speed, high efficiency, and simple drive circuits. SOI substrates combined with trench technology is superior to traditional Junction Isolation (JI) techniques in terms of cross-talk and leakage currents. Vertical DMOS transistors on SOI have been manufactured and characterized, and an analytical model for their on-resistance is presented. A description of self-heating and operation at elevated temperatures is included. Furthermore, the switching dynamics of these components is investigated by means of device simulations with the result that the dissipated power during unclamped inductive switching tests is reduced substantially compared to bulk vertical DMOSFETs. A large number of defects is created in the device layer if the trenches are exposed to high temperatures during processing. A new fabrication process with back-end trench formation is introduced in order to minimize defect generation. In addition, a model for the capacitive coupling between trench-isolated structures is developed.
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Zheng, Qi. "Performance Characterization of Silicon-On-Insulator (SOI) Corner Turning and Multimode Interference Devices." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/23234.
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Silicon-on-insulator (SOI) technology has become increasingly attractive because of the strong light confinement, which significantly reduces the footprint of the photonic components, and the possibility of monolithically integrating advanced photonic waveguide circuits with complex electronic circuits, which may reduce the cost of photonic integrated circuits by mass production. This thesis is dedicated to numerical simulation and experimental performance measurement of passive SOI waveguide devices. The thesis consists of two main parts. In the first part, SOI curved waveguide and corner turning mirror are studied. Propagation losses of the SOI waveguide devices are accurately measured using a Fabry-Perot interference method. Our measurements verify that the SOI corner turning mirror structures can not only significantly reduce the footprint size, but also reduce the access loss by replacing the curved sections in any SOI planar lightwave circuit systems. In the second part, an optical 90o hybrid based on 4 × 4 multimode interference (MMI) coupler is studied. Its quadrature phase behavior is verified by both numerical simulations and experimental measurements.
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Haneef, Ibraheem. "SOI CMOS MEMS flow sensors." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611843.
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Nayfeh, Hasan M. (Hasan Munir) 1974. "Correlation of silicon microroughness with electrical parameters of SOI-AS (silicon-on-insulator with active substrate)." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47504.
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Mohd, Zain Anis Suhaila. "Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs." Thesis, University of Glasgow, 2013. http://theses.gla.ac.uk/4281/.
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The main objective of this thesis is to perform a comprehensive simulation study of the statistical variability in well scaled fully depleted ultra thin body silicon on insulator (FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB SOI transistor scaling and the impacts of statistical variability and reliability the scaled template transistor. The starting point of this study is a systematic simulation analysis based on a welldesigned 32nm thin body SOI template transistor provided by the FP7 project PULLNANO. The 32nm template transistor is consistent with the International Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished 3D ‘atomistic’ simulator GARAND has been employed in the designing of the scaled transistors and to carry out the statistical variability simulations. Following the foundation work in characterizing and optimizing the template 32 nm gate length transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using typically 0.7 scaling factor in respect of the horizontal and vertical transistor dimensions. The device design process is targeted for low power applications with a careful consideration of the impacts of the design parameters choice including buried oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation results, carefully assessing the impact on manufacturability and to consider the corresponding trade-off between short channel effects and on-current performance. Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been adopted as optimum values respectively. iv The statistical variability of the transistor characteristics due to intrinsic parameter fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain induced barrier lowering (DIBL) are analysed. Each principal sources of variability is treated individually and in combination with other variability sources in the simulation of large ensembles of microscopically different devices. The introduction of highk/ metal gate stack has improved the electrostatic integrity and enhanced the overall device performance. However, in the case of fully depleted channel transistors, MGG has become a dominant variability factor for all critical electrical parameters at gate first technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon, increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter fluctuations and therefore, none of these sources should be overlooked in the simulations. Finally, the impact of different variability sources in combination with positive bias temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not only introduces a significant degradation of transistor performance, but also accelerates the statistical variability. For example, the effect of a late degradation stage (at trap density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to 36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors.
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Tashtush, Aktham Atallah Mofleh. "Characterization of integrated Bragg gratings in silicon-on-insulator." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amslaurea.unibo.it/7670/.
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Silicon-on-insulator (SOI) is rapidly emerging as a very promising material platform for integrated photonics.
As it combines the potential for optoelectronic integration with the low-cost and large volume manufacturing capabilities and they are already accumulate a huge amount of applications in areas like sensing, quantum optics, optical telecommunications and metrology.
One of the main limitations of current technology is that waveguide propagation losses are still much higher than in standard glass-based platform because of many reasons such as bends, surface roughness and the very strong optical confinement provided by SOI.
Such high loss prevents the fabrication of efficient optical resonators and complex devices severely limiting the current potential of the SOI platform.
The project in the first part deals with the simple waveguides loss problem and trying to link that with the polarization problem and the loss based on Fabry-Perot Technique.
The second part of the thesis deals with the Bragg Grating characterization from again the point of view of the polarization effect which leads to a better stop-band use filters.
To a better comprehension a brief review on the basics of the SOI and the integrated Bragg grating ends up with the fabrication techniques and some of its applications will be presented in both parts, until the end of both the third and the fourth chapters to some results which hopefully make its precedent explanations easier to deal with.
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Shen, Chao. "Study of CMOS active pixel image sensor on SOI/SOS substrate /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20SHEN.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 67-69). Also available in electronic version. Access restricted to campus users.
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Wu, I.-Tsang. "Integrated Electrostatically- and Piezoelectrically-Transduced Contour-Mode MEMS Resonator on Silicon-on-Insulator (SOI) Wafer." Scholar Commons, 2014. https://scholarcommons.usf.edu/etd/5336.
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Due to the recent rapid growth in personal mobile communication devices (smartphones, PDA's, tablets, etc.), the wireless market is always looking for new ways to further miniaturize the RF front-ends while reducing the cost and power consumption. For many years, wireless transceivers and subsystems have been relying on high quality factor (Q) passives (e.g., quartz crystal, ceramics) to implement oscillators, filters, and other key RF front-end circuitry elements. However, these off-chip discrete components occupy large chip area and require power-demanding interfacing circuits. As a result, a great deal of research effort has been devoted to the development of micromechanical resonators that are much more amenable to direct integration with integrated circuit (IC).
Over the past few years, vibrating RF MEMS (Micro-Electrical-Mechanical-System) resonator technology has emerged as a viable solution, most notably, the film bulk acoustic resonator (FBAR) and surface acoustic wave (SAW) resonator, which have already been successfully implemented into commercial products. Undoubtedly, micromechanical resonators such as FBAR's can perform as well as if not better than its bulky conventional counterparts and facilitate the miniaturization and power reduction of conventional RF systems. However, in some cases when multi-frequency functionality on a single-chip is needed, FBAR simply won't deliver.
To address this dilemma, contour-mode MEMS resonators have been developed and regarded as the most viable on-chip high-Q alternative. Unlike FBAR, contour-mode resonators use lateral dimensions to define its resonating frequencies, thus allowing for single-chip multi-frequency functionality. However, there is still room for improvement with respect to lowering the motional resistance of these devices to allow matching to 50 Ω electronics, while retaining low power consumption, small size, and simpler manufacturing process.
This dissertation presents the design, fabrication, characterization and experimental analysis of two types of micro-mechanical resonators. Piezoelectrically- and electrostatically-transduced micromechanical resonators will both be shown. Both types of resonator will be fabricated in the same micro-fabrication run, which makes the comparison between the two much more impartial. The impacts of substrate's resistivity over the device performances will also be studied.
Among the most significant results, this dissertation also presents several ideas that are enabled by the use of silicon-on-insulator (SOI) wafer. A novel single-mask fabrication process that can produce capacitive resonator with nano-meter gap is demonstrated. The concept of dual-transduced micro-mechanical resonator is introduced by combining both piezoelectric and capacitive based resonators. Finally, frequency tuning of MEMS resonator are explored and detailed in this work as well.
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England, Troy Daniel. "Silicon-germanium BiCMOS and silicon-on-insulator CMOS analog circuits for extreme environment applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51806.
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Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
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A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.
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Lim, Soon Thor. "Flat spectral response arrayed waveguide grating (AWG) in silicon-on-insulator (SOI) via ion implantation." Thesis, University of Surrey, 2005. http://epubs.surrey.ac.uk/844540/.
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This thesis proposed and demonstrated a flat-spectral response Arrayed Waveguide Grating (AWG) in Silicon-on-Insulator (SOI). The response exhibits a flat spectral of approximately 0.5nm with a crosstalk level of round -3dB. The high crosstalk is due to the phase errors as a result of fabrication tolerance and errors. Two main errors were identified. Firstly, the systematic errors of waveguide rib width and etched depth and secondly, the random variation of photomask resolution which was subjected to fabrication equipment in Southampton University. These errors have been investigated and the observations of the analysis were consistent with the experimental result. The AWG is designed to operate at a centre wavelength of 1.55mum at a grating order of 52 with path length differences of 23.62mum. The rib waveguides of the array are designed to operate as singlemode waveguides and to exhibit minimum polarisation dependence. As this thesis is to proof of principle, additional optimisation of the AWG is not carried out. The main ideology of the design method is to introduce free carriers to parts of the waveguides across the grating arms to induce absorption. This will modify the shape the field distribution across the array waveguides from a Gaussian to a SINC function. By applying Fourier optics to the free space region of the AWG, this field profile is the inverse Fourier transforms of the required output field of the AWG, which is the flat spectral response. This method gives the robustness of tailoring the optical field distribution across the AWs by the appropriate choice of net doping concentration, and hence gives room for design flexibility without increasing the physical dimension of the AWG significantly. The potential of achieving a smaller SOI AWG device with the use of higher net dosage and the realisation of achieving a uniform doping concentration through multiple implantations has been discussed. Keywords: Arrayed Waveguide Gratings (AWG), Flat-spectral response, Ion Implantation, Rib waveguides, Silicon-on-insulator (SOI), Silicon photonics.
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Deng, Henghua. "Design and Characterization of Silicon-on-Insulator Passive Polarization Converter with Finite-Element Analysis." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/833.
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As optical fiber systems evolve to higher data rates, the importance of polarization control and manipulation steadily increases. Polarization manipulating devices, such as polarization splitters and converters, can be realized by introducing material anisotropy or geometric asymmetry. Compared to active devices, passive polarization converters are more simply fabricated and controlled; therefore they have attracted increasing attention during the past two decades. However, materials employed in previous polarization rotating waveguides are mainly limited to low index-contrast III-V semiconductors such as InP and GaAs. Such III-V devices possess large radiation loss, large curvature loss, and low coupling efficiency to single-mode fibers; in addition, due to the weak optical confinement, the device spacing has to be large, which prevents high-density and large-scale integration in optoelectronic integrated circuits (OEIC) and planar lightwave circuits (PLC). In this dissertation, the silicon-on-insulator (SOI) technology is introduced to the design and fabrication of passive polarization rotators (PR). Efficient and accurate full-vectorial finite-element eigenmode solvers as well as propagation schemes for characterizing novel SOI PRs are developed because commercial software packages based on finite-difference techniques are inefficient in dealing with arbitrary waveguide geometries.
A set of general design procedures are accordingly developed to design a series of slanted-angle polarization converters, regardless of the material system (SOI or III-V), outer-slab layer configuration (symmetric or asymmetric), and longitudinal loading (single- or multi-section). In particular, our normalized design charts and simple empirical formula for SOI polarization converters are applicable to a wide range of silicon-guiding-film thickness, e. g. , from 1 to 30 μm, enabling fast and accurate polarization rotator design on most commercial SOI wafers. With these procedures, in principle 100% polarization conversion efficiency can be achieved by optimizing waveguide geometric parameters.
A novel configuration with asymmetric external waveguiding layers is proposed, which is advantageous for fabrication procedure, manufacturing tolerance, single-mode region, and conversion efficiency. By etching along the crystallographic plane, the angled-facet can be perfectly fabricated. Completely removing external waveguiding layer beside the sloped sidewall not only simplifies production procedures but also enhances fabrication tolerances.
To accurately and efficiently characterize asymmetric slanted-angle SOI polarization converters, adaptive mesh generation procedures are incorporated into our finite-element method (FEM) analysis. In addition, anisotropic perfectly-matched-layer (PML) boundary condition (BC) is employed in the beam propagation method (BPM) in order to effectively suppress reflections from the edges of the computation window. For the BPM algorithm, the power conservation is strictly monitored, the non-unitarity is thoroughly analyzed, and the inherent numerical dissipation is reduced by adopting the quasi-Crank-Nicholson scheme and adaptive complex reference index.
Advantages of SOI polarization rotators over III-V counterparts are studied through comprehensive research on power exchange, single-mode condition, fabrication tolerance, wavelength stability, bending characteristics, loss and coupling properties. The performance of SOI PRs is stable for wavelengths in the ITU-T C-band and L-band, making such devices quite suitable for DWDM applications. Due to the flexible cross-section of SOI polarization converters, the coupling loss to laser diodes and single mode fibers (SMF) can be designed to be very small and can be further reduced by a tapered waveguide with cross-sections always satisfying the single-mode criteria. Slanted-angle SOI polarization rotators display asymmetric bending characteristics and permit extremely small curvatures with negligible radiation loss when the angled-facet is located at the outer bend radius. Moreover, SOI polarization rotators can be manufactured with low-price processing techniques that are fully compatible with CMOS integrated circuits (IC) technology, and thus can be integrated on both photonic and electronic chips.
Experimental verifications have shown good agreement with theoretical analysis and have confirmed the promising characteristics of our novel asymmetric SOI polarization converters. Similar asymmetric-outer-slab geometry has recently been employed by peer researchers to fabricate high performance III-V polarization rotators. We therefore believe that results in this dissertation will contribute much to related research fields.
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Forhan, Neisy Amparo Escobar. "Fabricação de novas heteroestruturas a partir de estruturas SOI obtidas pela técnica \'smart-cut\'." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-02042008-112321/.
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Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico.In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.
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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.
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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
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Ndoye, Coumba. "Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/46321.
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The semiconductor industry scaling has mainly been driven by Mooreâ s law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated.
Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary.
This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms.Master of Science
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Baudot, Sophie. "MOSFETs contraints sur SOI : analyse des déformations par diffraction des rayons X et étude des propriétés électriques." Phd thesis, Grenoble, 2010. http://www.theses.fr/2010GRENY064.
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L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canalThe use of mechanical stress in the channel of MOSFETs on SOI is mandatory for sub-22 nm technological nodes. Its efficiency depends on the device geometry and design. The impact of different steps of the transistor fabrication process (active area patterning, metal gate formation, Source/Drain (S/D) implantation) on the strain in strained Silicon-On-Insulator (sSOI) materials has been measured by Grazing Incidence X-Ray Diffraction (GIXRD). The electrical performance enhancement of MOSFETs on sSOI has also been estimated with respect to SOI (100% mobility enhancement for long and wide nMOS (L=W=10 μm), 35% saturation drive current (IDsat) enhancement for short and narrow nMOS (L=25 nm, W=77 nm)). Innovative strained structures have then been studied. We demonstrate a 37% (18%) IDsat enhancement for pMOS on SOI (sSOI) with SiGe S/D compared to sSOI with Si S/D, for a 60 nm gate length and a 15 nm film thickness. GIXRD measurements, together with mechanical simulations, enabled the study and optimization of new structures using the stress transfer from an embedded and stressed layer (SiGe or nitride) toward the channel
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Litty, Antoine. "Conception, fabrication, caractérisation et modélisation de transistors MOSFET haute tension en technologie avancée SOI (Silicon-On-Insulator)." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT002/document.
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A l’heure où la miniaturisation des technologies CMOS sur substrat massif atteint des limites, la technologie FDSOI (silicium sur isolant totalement déserté) s’impose comme une alternative pour l’industrie en raison de ses meilleures performances. Dans cette technologie, l’utilisation d’un substrat SOI ultramince améliore le comportement des transistors MOSFETs et garantit leur intégrité électrostatique pour des dimensions en deçà de 28nm. Afin de lui intégrer de nouvelles fonctionnalités, il devient nécessaire de développer des applications dites « haute tension » comme les convertisseurs DC/DC, les régulateurs de tension ou encore les amplificateurs de puissance. Cependant les composants standards de la technologie CMOS ne sont pas capables de fonctionner sous les hautes tensions requises. Pour répondre à cette limitation, ces travaux portent sur le développement et l’étude de transistors MOS haute tension en technologie FDSOI. Plusieurs solutions sont étudiées à l’aide de simulations numériques et de caractérisations électriques : l’hybridation du substrat (gravure localisée de l’oxyde enterré) et la transposition sur le film mince. Une architecture innovante sur SOI, le Dual Gound Plane EDMOS, est alors proposée, caractérisée et modélisée. Cette architecture repose sur la polarisation d’une seconde grille arrière pour offrir un compromis RON.S/BV prometteur pour les applications viséesNowadays the scaling of bulk silicon CMOS technologies is reaching physical limits. In this context, the FDSOI technology (fully depleted silicon-on-insulator) becomes an alternative for the industry because of its superior performances. The use of an ultra-thin SOI substrate provides an improvement of the MOSFETs behaviour and guarantees their electrostatic integrity for devices of 28nm and below. The development of high-voltage applications such DC/DC converters, voltage regulators and power amplifiers become necessary to integrate new functionalities in the technology. However, the standard devices are not designed to handle such high voltages. To overcome this limitation, this work is focused on the design of a high voltage MOSFET in FDSOI. Through simulations and electrical characterizations, we are exploring several solutions such as the hybridization of the SOI substrate (local opening of the buried oxide) or the implementation in the silicon film. An innovative architecture on SOI, the Dual Ground Plane EDMOS, is proposed, characterized and modelled. It relies on the biasing of a dedicated ground plane introduced below the device to offer promising RON.S/BV trade-off for the targeted applications
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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
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High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.
To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.
The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.
The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.
A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.
Report code: LiU-Tek-Lic-2005:68.
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Baudot, Sophie. "MOSFETs contraints sur SOI : analyse des déformations par diffraction des rayons X et étude des propriétés électriques." Phd thesis, Grenoble, 2010. http://tel.archives-ouvertes.fr/tel-00557963.
Full textAbstract:
L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canal.
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Jiang, Hao. "Numerical Modeling and Analysis of Micro-structuring on Silicon on Insulator (SOI) Film under Localized Single Pulse Laser Irradiation." University of Toledo / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1302280541.
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Dai, Daoxin. "Designs and simulations of silicon-based microphotonic devices." Doctoral thesis, Stockholm: Division of Electromagnetic Theory, Royal Institute of Technology, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-226.
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Moolamalla, Himaja Reddy. "An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377751&SrchMode=1&sid=5&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277473834&clientId=28564.
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Bellini, Marco. "Operation of silicon-germanium heterojunction bipolar transistors on." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28206.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Cressler, John D.; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen; Committee Member: Shen, Shyh-Chiang; Committee Member: Zhou, Hao Min.
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Song, Jiguo. "Compact Trench-Based Silicon-on-Insulator Rib Waveguide 90-Degree and 105-Degree Bend and Splitter Design." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2547.pdf.
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Foell, III Charles Alden. "Luminescent properties of Pb-based (PbX) colloidal quantum dots (CQDs) in vacuum, on silicon and integrated with a silicon-on-insulator (SOI) photonic integrated circuit (PIC)." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/57665.
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In the rapidly evolving field of experimental quantum information processing, one important sub-field pursues a potentially scalable implementation that transports quantum information encoded in photons throughout “photonic circuits” fabricated in a silicon wafer. A key component is an efficient on-demand source of these single photons, and this dissertation aimed to assess the feasibility of one proposed realization of such a source by integrating few PbSe colloidal quantum dots (CQDs, demonstrated single photon emitters in nanoparticle form) into the mode volume of an optical microcavity designed to efficiently direct quantum dot emission into a silicon photonic circuit. Although no direct evidence of {\it single} photon emission was observed, results prompted a number of follow-up experiments and considerable theoretical modeling to understand this quantum dot, photonic circuit system.
The methods of investigation included (1) temporally-, spectrally-, and spatially-resolved photoluminescence (PL) measurements of PbSe CQDs integrated into SOI PICs and relatable environments (solution, thick film, thin film), (2) temperature-dependent, air-exposure studies of PbSe CQD thick film PL, (3) development and application of kinetic and quantum mechanical cavity-coupled modeling that admit complete accounting of the photonic density of states, depolarization effects, and non-radiative decay, and (4) a photon coincidence test of single photon emission.
The main findings of this work are: (1) while capture of cavity-enhanced PbSe CQD emission into a silicon photonic circuit was demonstrated, the overall photon generate rate is inadequate for any useful implementation, (2) the measured coupling rate can be modeled and explained in terms of system parameters extracted from auxiliary experimental results obtained with the PbSe CQDs in isolation, or on isolated microcavities, and (3) consistent results could only be obtained after nontrivial depolarization factors and non-radiative decay processes are properly accounted for. From this it is clear that the performance of PbSe CQDs in this configuration of a single photon source in silicon is currently limited by a long-lived trap state with a several microsecond lifetime, and large depolarization effects that inhibit emission. Although plausible future efforts may mitigate these effects substantially, performance may still be hindered by the intrinsic emission strength of PbSe CQDs.Science, Faculty of
Physics and Astronomy, Department of
Graduate
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Singh, Siddhartha. "Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature /." Online version of thesis, 2009. http://hdl.handle.net/1850/11427.
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Gallet, Antonin. "Hybrid III-V on silicon lasers for optical communications." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT019/document.
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L’intégration photonique permet de réduire la taille et la consommation d’énergie des systèmes de communication par fibre optique par rapport aux systèmes assemblés à partir de composants unitaires. Cette technologie a récemment suscité un grand intérêt avec les progrès de l’intégration sur InP et le développement de la photonique sur silicium. Cette dernière challenge la plate-forme d’intégration sur InP car des composants à hautes performances et faibles coûts peuvent être fabriqués dans des fonderies originellement développées pour la microélectronique. Les lasers sont l'une des pièces maitresses des émetteurs-récepteurs pour les communications optiques. Leur intégration sur la plateforme silicium permet de développer des émetteurs-récepteurs comprenant les fonctions critiques d’émission de lumière, de modulation et de détection sur une même puce. L’intégration de matériaux III-V par collage moléculaire sur plaque silicium permet de produire de grands volumes : plusieurs dizaines voire centaines de composants sont réalisés par wafer. Dans cette thèse, j’ai étudié théoriquement et expérimentalement les propriétés des lasers accordables basés sur des résonateurs en anneau en silicium, des lasers à rétroaction distribuée modulés directement et des lasers à haut facteur de qualité qui présentent un faible bruit de phase et d’intensitéPhotonic integration reduces the size and energy consumption of fiber optic communication systems compared to systems assembled from discrete components. This technology has recently attracted a great interest with the progress of integration on InP and the development of silicon photonics. The latter challenges the integration platform on InP as high-performance and low-cost components can be manufactured in foundries originally developed for microelectronics. Lasers are one of the main parts of transceivers for optical communications. With their integration on the silicon platform, transceivers that include the critical functions of light emission, modulation and detection on the same chip can be made. In the heterogeneous integration platform, components are manufactured in high volumes: several tens or even hundreds of components are produced per wafer. In this thesis, I studied theoretically and experimentally the properties of tunable lasers based on silicon ring resonators, directly modulated distributed feedback lasers and low noise high-quality factor lasers
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Passanante, Thibault. "Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI." Thesis, Aix-Marseille, 2014. http://www.theses.fr/2014AIXM4020.
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Ce travail de thèse est consacré à l’étude expérimentale des mécanismes de démouillage de films solides d’épaisseur nanométrique conduisant à la transformation d’un film mince en une assemblée d’îlots tridimensionnels. L’utilisation de la microscopie à électrons lents (LEEM) nous a permis d’étudier la morphologie et la cinétique in situ et en temps réel du démouillage de films de Si/SiO2 (SOI) et de Ge/SiO2 (GOI) obtenus par collage moléculaire (procédé Smart Cut™). Ces mesures expérimentales ont été complétées par des analyses par diffusion centrale des rayons X en incidence rasante (GISAXS) et des observations ex situ par microscopie à force atomique (AFM). Les mécanismes de démouillage de SOI et GOI sont thermodynamiquement pilotés par la capillarité et cinétiquement contrôlés par la diffusion de surface. L’étude complémentaire du démouillage à partir de fronts cristallographiquement orientés obtenus par lithographie nous a permis d’analyser le rôle central du facettage, de l’anisotropie cristalline et des processus de formation du bourrelet de démouillage. En particulier, le rôle de la nucléation 2D sur la cinétique d’épaississement (couche par couche) du bourrelet a pu être mis en évidence. Les résultats expérimentaux ont pu être confrontés à des modèles analytiques et des simulations de type Monte Carlo cinétique. Nous en avons déduit les valeurs des paramètres physiques pertinents et avons attribué les différences de morphologies entre SOI et GOI à la présence de facettes spécifiquesThis work is devoted to the experimental study of the dewetting mechanisms of ultrathin solid films by which a metastable film transforms into an assembly of tridimensional crystallites. Using low energy Electron Microscopy (LEEM) we analyse, in situ and in real time, the morphology and the kinetics of the dewetting of Si/SiO2 (SOI) and Ge/SiO2 (GOI) systems obtained by molecular bonding (Smart Cut™ process). Further information has been obtained by Grazing Incidence Small Angle X–ray Scattering (GISAXS) and Atomic Force Microscopy (AFM) measurements. We show that the dewetting is driven by surface free energy minimization and mediated by surface diffusion. A complementary study of artificial well-oriented dewetting fronts obtained by lithography enables us to analyze the important role played by facets, the crystal anisotropy and the rim thickening mechanism. We show that the rim thickening proceeds in a layer-by-layer mode and is limited by 2D nucleation. Thanks to analytical models and Kinetics Monte Carlo simulations, numerical values of the pertinent physical parameters involved in the dewetting process are obtained and the morphological differences between SOI and GOI are attributed to the presence of specific facets
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BREED, ANIKET A. "DESIGN, SIMULATION AND ANALYSIS OF THE SWITCHING AND RF PERFORMANCE OF MULTI-GATE SILICON-ON-INSULATOR MOSFET DEVICE STRUCTURES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1121014432.
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Bazin, Alexandre. "III-V Semiconductor Nanocavitieson Silicon-On-Insulator Waveguide : Laser Emission, Switching and Optical Memory." Phd thesis, Université Paris-Diderot - Paris VII, 2013. http://tel.archives-ouvertes.fr/tel-01007643.
Full textAbstract:
La photonique sur silicium constitue une plateforme idéale pour transmettre et distribuer des signaux optiques au sein d'une puce et sur de longues distances sans pertes excessives. L'intégration de semiconducteurs III-V sur des circuits photonique en silicium est un projet excitant mais ambitieux, que nous avons mené en combinant le meilleur de l'optoélectronique des semiconducteurs III-V et des technologies photonique en siliicium-sur-isolant (SOI en anglais). Afin de pouvoir remplacer les interconnexions metalliques existantes par des interconnexion optiques, nous nous sommes efforcés d'utiliser les objets ayant les dimensions les plus petites et consommant les plus petites énergies comme peuvent l'être les nanocavités en Cristaux Photoniques incorporant des matériaux actifs en III-V. Cette thèse visait à conceptualiser, fabriquer et étudier expérimentalement des structures hybrides III-V/circuit photonique SOI, où une couche de III-V, reportée par collage adhésif à quelques centaines de nm du silicium, est gravée en une cavité optique de type cristal photonique " nanobeam " et résonante autour de 1.5 μm. Les principaux résultats de ce travail sont les démonstration 1) d'une efficacité de couplage entre la cavité et le guide d'onde SOI facilement ajustable, pouvant excéder 90% lorsque les conditions d'accord de phase sont remplies, 2) de l'émission laser en régime continue avec des puits quantiques via la passivation des surfaces, et 3) d'une mémoire optique de durée supérieure à 2s avec des énergies de commutations ultrafaibles (~0.4 fJ). Nous présentons aussi un modèle pour fabriquer des cavités " nanobeam " de facteurs Q très élevés, encapsulées dans un matériau bas indice.
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Farhi, Ghania. "Fabrication, simulation et caractérisation des propriétés de transport de composants à effet de champ latéral sur substrat de soi (Silicon-on-insulator)." Thèse, Université de Sherbrooke, 2014. http://hdl.handle.net/11143/6016.
Full textAbstract:
À la base de l’évolution de la technologie microélectronique actuelle, la réduction des dimensions critiques des MOSFET standards pour améliorer leurs performances électriques a atteint depuis quelques années ses limites physiques. L’utilisation de nanocomposants innovateurs ayant une configuration planaire, comme solution de remplacement, semble être une voie prometteuse pour certaines applications. Les diodes autocommutantes, Self-Switching Diodes (SSD), en font partie.
Les SSD sont des composants unipolaires à deux accès ayant une caractéristique I-V non-linéaire semblable à celle d’une diode bipolaire. Leur configuration planaire rend leur fabrication plus facile et réduit considérablement les capacités parasites intrinsèques.
Cette thèse porte sur la fabrication, la simulation et la caractérisation électrique de SSD fabriquées sur des substrats en SOI (Silicon-On-Insulator).
Les dispositifs SSD ont été réalisés au départ grâce à des gravures par FIB (Focussed Ion Beam). Cette technique polyvalente nous permet de contrôler en temps réel les conditions de gravure. Par la suite, nous avons procédé à une fabrication massive de SSD en utilisant la technique d’électrolithographie et de gravure sèche.
Les simulations effectuées principalement avec TCAD-Medici nous ont permis d’optimiser et d’investiguer en détails l’effet critique des paramètres géométriques (longueur, largeur et épaisseur du canal conducteur ainsi que la largeur des tranchées isolantes) et des paramètres physiques (densité surfacique aux niveaux des interfaces isolant/semiconducteur, densité des dopants et type de diélectrique dans les tranchées isolantes) des SSD sur les caractéristiques électriques, les valeurs de la tension seuil et les phénomènes de transport non linéaire qui ont lieu dans le canal conducteur de ce type de composants.
Les mesures expérimentales de caractéristiques I-V de SSD ayant des canaux conducteurs de largeurs et de longueurs variables confirment les prévisions de nos simulations.
Bien que le comportement électrique des SSD ressemble à celui d’un MISFET, nous démontrons le fait que l’on ne peut modéliser leurs caractéristiques I-V avec les mêmes expressions en nous basant sur le principe de fonctionnement spécifique à chacun de ces deux dispositifs.
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Truman, Sutanto Pagra. "Multifunktionsfeldeffekttransistoren zur Strömungs-, Chemo- und Biosensorik in Lab on a Chip-Systemen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1199907096113-76856.
Full textAbstract:
In dieser Arbeit wird eine neue Methode und ein neuartiges FET -Sensorelement zum Nachweis von Flüssigkeitsbewegungen vorgestellt, das zudem bei Bedarf auch als Chemo- oder Biosensor fungieren kann. Das Einsatzspektrum von FET-basierten Sensoren in Lab on a Chip-Systemen wird dadurch entscheidend erweitert. Bei dem entwickelten FET-Sensor Bauelement handelt es sich um einen normally-on n-leitenden Dünnschichtfeldeffekttransistor mit Ti-Au-Kontakten, basierend auf Silicon-on-Insulator- Substraten, wobei das natürliche Oxid des Siliziumfilms als Schnittstelle zum Elektrolyten bzw. zur Flüssigkeit verwendet wird. Der mit 10exp16 Bor Atomen pro cm³ p-dotierte Siliziumdünnfilm hat eine Dicke von nur 55 nm und ist durch eine 95 nm dicke Siliziumdioxidschicht vom darunterliegenden Siliziumsubstrat von 600 µm Dicke elektrisch isoliert. Aufgrund der geringen Schichtdicke durchdringt die feldempfindliche Raumladungs- bzw. Verarmungszone die gesamte Dünnschicht, so dass durch Anlegen einer Backgatespannung am Substrat der spezifische Widerstand und die Empfindlichkeit des Bauelements eingestellt werden können. Grundlegende ISFET-Funktionalitäten wie die Empfindlichkeit auf Änderungen der Ionenstärke und des pH-Wertes werden nachgewiesen und ein ENFET-Glukosesensor realisiert. Zudem wird im Hinblick auf die Separation von Emulsionen der Nachweis erbracht, dass die Benetzung mit Hexan und Toluol eine Änderung der spezifischen Leitfähigkeit bewirkt, und die Empfindlichkeit des Bauelements nach Beschichtung mit einem hydrophoben Methacrylatcopolymerfilm erhalten bleibt. Hinsichtlich der Verwendung des FET-Sensor Bauelements zum Nachweis von Flüssigkeitsbewegungen wird zunächst ein theoretisches Modell entwickelt, dessen Kernaussage ist, dass sich in einem rechteckigen Kanal der relative Bedeckungsgrad mit Flüssigkeit direkt proportional zum Drainstrom des FET-Sensors verhält. Basierend auf diesem theoretischen Modell, welches experimentell belegt wird, können mittels eines einzelnen FET-Sensors Füllstand und Füllgeschwindigkeit bzw. bei bekannter Füllgeschwindigkeit Kapillarvolumen und Kapillargeometrie bestimmt werden. Abweichungen von der direkten Proportionalität erlauben zudem, Rückschlüsse auf die Benetzungseigenschaften der Kapillaren und die Dynamik an der Halbleitergrenzfläche zu ziehen. Ist ein Sensorelement vollständig mit Flüssigkeit bedeckt, wird mittels Lösungsmitteltropfen als Markerobjekten die Strömungsgeschwindigkeit bestimmt. Ändert sich die Ionenkonzentration im Elektrolyten als Funktion der Strömungsgeschwindigkeit, so kann die Strömungsgeschwindigkeit durch Messung der Ionenkonzentration mittels FET-Sensor ebenfalls ermittelt werden. Als wichtigster Demonstrator für die Verwendung des FET-Sensors wird ein komplexes Lab on a Chip-System zur Separation von Emulsionen auf chemisch strukturierten Oberflächen entwickelt, bei dem der Separationsvorgang mittels FET-Sensorarray verfolgt werden kann. Zur einfachen Herstellung chemisch modifizierter Oberflächen für die Separationsexperimente werden die Abscheidung von nanoskaligen hydrophoben Methacrylatcopolymerfilmen und die selektive Fluorsilanisierung von Oberflächen sowie deren Lösungsmittelbeständigkeit in Wasser, Toluol und Aceton untersucht. Dabei zeigt sich, dass die Hydrophobie nach Lösungsmittelbehandlung weitestgehend erhalten bleibt, Wasserrückstände im Methacrylatfilm aber zu einer reversiblen Schichtdegradation führen können. Als Modellsystem werden Hexan-Wasser- bzw. Toluol-Wasser-Emulsionen verwendet, die auf Oberflächen getrennt werden, deren eine Seite hydrophil, und deren andere Seite hydrophob ist (Stufengradient). Der Separationsprozess beruht auf der großen Affinität des Wassers hin zu polaren Oberflächen, wobei das wenig selektive Lösungsmittel zur unpolaren Seite gedrängt wird. Zur Erlangung eines tieferen Verständnisses des Prozesses werden die Tropfenkoaleszenz und der Einfluss geometrischer Beschränkungen untersucht. Die Versuche werden sowohl auf offenen Oberflächen als auch im Spalt, unter Verwendung von hydrophilen und hydrophoben Oberflächen, durchgeführt. Es zeigt sich, dass sich die Dynamik der Tropfenkoaleszenz im Spalt umgekehrt zur Dynamik auf offenen Oberflächen verhält. Dies wird mittels eines hierzu entwickelten theoretischen Modells erklärt, welches die Minimierung der Oberflächenenergie und Hystereseeffekte einbezieht. Das Lab on a Chip-System schließlich besteht aus einem mit Siliziumnitrid beschichteten FET-Sensorchip, auf den eine Separationszelle aufgeklebt ist. Neben dem Einlass für die Emulsion ist ein weiterer Einlass vorhanden, durch den Salzsäure für eine pH-Reaktion zugegeben werden kann. Der gesamte Separationsprozess sowie die anschließende pH-Reaktion, lassen sich bequem am PC anhand der Änderung der Stromstärke der einzelnen Sensoren verfolgen und analysieren. Wichtige Ergebnisse hier sind: 1) Mittels eines quasi 1-dimensionalen Sensorarrays kann der Verlauf einer Flüssigkeitsfront in einem 2-dimensionalen Areal überwacht bzw. dargestellt werden. 2) Anhand der Signatur des Signalverlaufs bei pH-Änderung und Flüssigkeitsbewegung, können beide Prozesse unterschieden werden. Der Sensor kann also zum Nachweis von Flüssigkeitsbewegungen und zugleich als Chemosensor eingesetzt werden. Es wurde also nicht nur ein neuartiges, äußerst robustes, chemikalienbeständiges und biokompatibles Multifunktionssensorelement mit Abmessungen im Mikrometer- bis Millimeterbereich entwickelt, sondern auch eine neue Methode entwickelt, mit der es möglich ist, sowohl (bio-)chemische Reaktionen als auch die Bewegung von Flüssigkeiten in Lab on a Chip-Systemen nachzuweisen.
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Gallet, Antonin. "Hybrid III-V on silicon lasers for optical communications." Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT019.
Full textAbstract:
L’intégration photonique permet de réduire la taille et la consommation d’énergie des systèmes de communication par fibre optique par rapport aux systèmes assemblés à partir de composants unitaires. Cette technologie a récemment suscité un grand intérêt avec les progrès de l’intégration sur InP et le développement de la photonique sur silicium. Cette dernière challenge la plate-forme d’intégration sur InP car des composants à hautes performances et faibles coûts peuvent être fabriqués dans des fonderies originellement développées pour la microélectronique. Les lasers sont l'une des pièces maitresses des émetteurs-récepteurs pour les communications optiques. Leur intégration sur la plateforme silicium permet de développer des émetteurs-récepteurs comprenant les fonctions critiques d’émission de lumière, de modulation et de détection sur une même puce. L’intégration de matériaux III-V par collage moléculaire sur plaque silicium permet de produire de grands volumes : plusieurs dizaines voire centaines de composants sont réalisés par wafer. Dans cette thèse, j’ai étudié théoriquement et expérimentalement les propriétés des lasers accordables basés sur des résonateurs en anneau en silicium, des lasers à rétroaction distribuée modulés directement et des lasers à haut facteur de qualité qui présentent un faible bruit de phase et d’intensitéPhotonic integration reduces the size and energy consumption of fiber optic communication systems compared to systems assembled from discrete components. This technology has recently attracted a great interest with the progress of integration on InP and the development of silicon photonics. The latter challenges the integration platform on InP as high-performance and low-cost components can be manufactured in foundries originally developed for microelectronics. Lasers are one of the main parts of transceivers for optical communications. With their integration on the silicon platform, transceivers that include the critical functions of light emission, modulation and detection on the same chip can be made. In the heterogeneous integration platform, components are manufactured in high volumes: several tens or even hundreds of components are produced per wafer. In this thesis, I studied theoretically and experimentally the properties of tunable lasers based on silicon ring resonators, directly modulated distributed feedback lasers and low noise high-quality factor lasers
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Truman, Sutanto Pagra. "Multifunktionsfeldeffekttransistoren zur Strömungs-, Chemo- und Biosensorik in Lab on a Chip-Systemen." Doctoral thesis, Technische Universität Dresden, 2007. https://tud.qucosa.de/id/qucosa%3A25010.
Full textAbstract:
In dieser Arbeit wird eine neue Methode und ein neuartiges FET -Sensorelement zum Nachweis von Flüssigkeitsbewegungen vorgestellt, das zudem bei Bedarf auch als Chemo- oder Biosensor fungieren kann. Das Einsatzspektrum von FET-basierten Sensoren in Lab on a Chip-Systemen wird dadurch entscheidend erweitert. Bei dem entwickelten FET-Sensor Bauelement handelt es sich um einen normally-on n-leitenden Dünnschichtfeldeffekttransistor mit Ti-Au-Kontakten, basierend auf Silicon-on-Insulator- Substraten, wobei das natürliche Oxid des Siliziumfilms als Schnittstelle zum Elektrolyten bzw. zur Flüssigkeit verwendet wird. Der mit 10exp16 Bor Atomen pro cm³ p-dotierte Siliziumdünnfilm hat eine Dicke von nur 55 nm und ist durch eine 95 nm dicke Siliziumdioxidschicht vom darunterliegenden Siliziumsubstrat von 600 µm Dicke elektrisch isoliert. Aufgrund der geringen Schichtdicke durchdringt die feldempfindliche Raumladungs- bzw. Verarmungszone die gesamte Dünnschicht, so dass durch Anlegen einer Backgatespannung am Substrat der spezifische Widerstand und die Empfindlichkeit des Bauelements eingestellt werden können. Grundlegende ISFET-Funktionalitäten wie die Empfindlichkeit auf Änderungen der Ionenstärke und des pH-Wertes werden nachgewiesen und ein ENFET-Glukosesensor realisiert. Zudem wird im Hinblick auf die Separation von Emulsionen der Nachweis erbracht, dass die Benetzung mit Hexan und Toluol eine Änderung der spezifischen Leitfähigkeit bewirkt, und die Empfindlichkeit des Bauelements nach Beschichtung mit einem hydrophoben Methacrylatcopolymerfilm erhalten bleibt. Hinsichtlich der Verwendung des FET-Sensor Bauelements zum Nachweis von Flüssigkeitsbewegungen wird zunächst ein theoretisches Modell entwickelt, dessen Kernaussage ist, dass sich in einem rechteckigen Kanal der relative Bedeckungsgrad mit Flüssigkeit direkt proportional zum Drainstrom des FET-Sensors verhält. Basierend auf diesem theoretischen Modell, welches experimentell belegt wird, können mittels eines einzelnen FET-Sensors Füllstand und Füllgeschwindigkeit bzw. bei bekannter Füllgeschwindigkeit Kapillarvolumen und Kapillargeometrie bestimmt werden. Abweichungen von der direkten Proportionalität erlauben zudem, Rückschlüsse auf die Benetzungseigenschaften der Kapillaren und die Dynamik an der Halbleitergrenzfläche zu ziehen. Ist ein Sensorelement vollständig mit Flüssigkeit bedeckt, wird mittels Lösungsmitteltropfen als Markerobjekten die Strömungsgeschwindigkeit bestimmt. Ändert sich die Ionenkonzentration im Elektrolyten als Funktion der Strömungsgeschwindigkeit, so kann die Strömungsgeschwindigkeit durch Messung der Ionenkonzentration mittels FET-Sensor ebenfalls ermittelt werden. Als wichtigster Demonstrator für die Verwendung des FET-Sensors wird ein komplexes Lab on a Chip-System zur Separation von Emulsionen auf chemisch strukturierten Oberflächen entwickelt, bei dem der Separationsvorgang mittels FET-Sensorarray verfolgt werden kann. Zur einfachen Herstellung chemisch modifizierter Oberflächen für die Separationsexperimente werden die Abscheidung von nanoskaligen hydrophoben Methacrylatcopolymerfilmen und die selektive Fluorsilanisierung von Oberflächen sowie deren Lösungsmittelbeständigkeit in Wasser, Toluol und Aceton untersucht. Dabei zeigt sich, dass die Hydrophobie nach Lösungsmittelbehandlung weitestgehend erhalten bleibt, Wasserrückstände im Methacrylatfilm aber zu einer reversiblen Schichtdegradation führen können. Als Modellsystem werden Hexan-Wasser- bzw. Toluol-Wasser-Emulsionen verwendet, die auf Oberflächen getrennt werden, deren eine Seite hydrophil, und deren andere Seite hydrophob ist (Stufengradient). Der Separationsprozess beruht auf der großen Affinität des Wassers hin zu polaren Oberflächen, wobei das wenig selektive Lösungsmittel zur unpolaren Seite gedrängt wird. Zur Erlangung eines tieferen Verständnisses des Prozesses werden die Tropfenkoaleszenz und der Einfluss geometrischer Beschränkungen untersucht. Die Versuche werden sowohl auf offenen Oberflächen als auch im Spalt, unter Verwendung von hydrophilen und hydrophoben Oberflächen, durchgeführt. Es zeigt sich, dass sich die Dynamik der Tropfenkoaleszenz im Spalt umgekehrt zur Dynamik auf offenen Oberflächen verhält. Dies wird mittels eines hierzu entwickelten theoretischen Modells erklärt, welches die Minimierung der Oberflächenenergie und Hystereseeffekte einbezieht. Das Lab on a Chip-System schließlich besteht aus einem mit Siliziumnitrid beschichteten FET-Sensorchip, auf den eine Separationszelle aufgeklebt ist. Neben dem Einlass für die Emulsion ist ein weiterer Einlass vorhanden, durch den Salzsäure für eine pH-Reaktion zugegeben werden kann. Der gesamte Separationsprozess sowie die anschließende pH-Reaktion, lassen sich bequem am PC anhand der Änderung der Stromstärke der einzelnen Sensoren verfolgen und analysieren. Wichtige Ergebnisse hier sind: 1) Mittels eines quasi 1-dimensionalen Sensorarrays kann der Verlauf einer Flüssigkeitsfront in einem 2-dimensionalen Areal überwacht bzw. dargestellt werden. 2) Anhand der Signatur des Signalverlaufs bei pH-Änderung und Flüssigkeitsbewegung, können beide Prozesse unterschieden werden. Der Sensor kann also zum Nachweis von Flüssigkeitsbewegungen und zugleich als Chemosensor eingesetzt werden. Es wurde also nicht nur ein neuartiges, äußerst robustes, chemikalienbeständiges und biokompatibles Multifunktionssensorelement mit Abmessungen im Mikrometer- bis Millimeterbereich entwickelt, sondern auch eine neue Methode entwickelt, mit der es möglich ist, sowohl (bio-)chemische Reaktionen als auch die Bewegung von Flüssigkeiten in Lab on a Chip-Systemen nachzuweisen.
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Ehteshami, Nasrin. "Silicon Photonic Devices for Microwave Signal Generation and Processing." Thesis, Université d'Ottawa / University of Ottawa, 2016. http://hdl.handle.net/10393/34111.
Full textAbstract:
Silicon photonics as a one of the most promising photonic integration technologies has attracted many attentions in recent years. The major feature of this technology is its compatibility with complementary metal-oxide semiconductor (CMOS) processes which makes it possible to integrate optical and electronic devices in a same chip and reduce the cost significantly. Another reason of using silicon photonics is the high index contrast between the silicon core and silicon dioxide cladding which ensures the high density integration of photonic devices on a single chip. Monolithic integration with electronic and optical circuits makes silicon photonics technology suitable for numerous applications. One example is microwave photonics (MWP). MWP is an area that studies the interaction between microwave and optical signal for the generation, processing, control and distribution of microwave signals by means of photonics. Silicon photonics offers a reduction in footprint, losses, packaging cost and power dissipation in MWP systems.
This research in this thesis is focused on the design and fabrication of the silicon photonic devices for MWP signal processing and generation. Four MWP systems based on silicon photonic devices are proposed and experimentally demonstrated.
1) A single pass-band frequency-tunable MWP filter based on phase-modulation to intensity-modulation conversion in an optically pumped silicon-on-insulator (SOI) microring resonator (MRR) is designed and experimentally demonstrated. In the proposed filter, a phase-modulated optical signal is filtered by the SOI MRR, to have one first-order sideband suppressed by the MRR notch. The phase-modulated optical signal is converted to an intensity-modulated single-sideband (SSB) signal and detected at a photodetector (PD). The entire operation is equivalent to a single pass-band filter. The frequency tunability is achieved by tuning the resonance wavelength of the MRR, which is realized by optically pumping the MRR. A single pass-band MWP filter with a tunable center frequency from 16 to 23 GHz is experimentally demonstrated.
2) A broadband optically tunable MWP phase shifter with a tunable phase shift using three cascaded SOI MRRs that are optically pumped is designed and experimentally demonstrated. A microwave signal to be phase shifted is applied to an optical single-sideband (OSSB) modulator to generate an optical carrier and an optical sideband. The phase shift is introduced to the optical carrier by placing the optical carrier within the bandwidth of one resonance of the three cascaded MRRs. The experimental results show that by optically pumping the cascaded MRRs, a broadband MWP phase shifter with a bandwidth of 7 GHz with a tunable phase shift covering the entire 360o phase shift range is achieved.
3) A multi tap MWP filter with positive and negative coefficients using a silicon ring resonator modulator (RRM) is proposed and experimentally demonstrated. The RRM is designed and fabricated to operate based on the carrier depletion effect. The positive and negative coefficients are obtained by using opposite slopes of the modulation transmission response of the RRM. Two filter responses with two and three taps are experimentally demonstrated, showing the proof-of-principle for frequencies up to 18 GHz.
4) An approach to generate microwave signal based on enhanced four wave mixing (FWM) in an active silicon waveguide (SiWG) is studied. This SiWG is designed and fabricated, and the use of the active SiWG for MWP frequency multiplication to generate a frequency-sextupled millimeter-wave signal is experimentally demonstrated. Thanks to a reverse-biased p-n junction across the SiWG, the conversion efficiency of the FWM is improved, which leads to the improvement of the microwave frequency multiplication efficiency.
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Bachi, Joe. "Design and implementation of high efficiency power amplifiers for 5G Applications." Electronic Thesis or Diss., Institut polytechnique de Paris, 2022. http://www.theses.fr/2022IPPAT039.
Full textAbstract:
La complexité croissante des schémas de modulation due à l'évolution des normes de communication mobile a conduit à des signaux à fort rapport puissance de crête/puissance moyenne (PAPR). En conséquence, les architectures traditionnelles d'amplificateurs de puissance (PA) linéaires ne sont plus adaptées car elles présentent un faible rendement moyen lorsqu'elles fonctionnent avec de tels signaux. Une des solutions possibles à ce problème est l'utilisation d'architectures basées sur la modulation de charge qui sont capables de fournir un rendement moyen plus élevé. Ce travail se concentre sur l'analyse, la conception et la mise en œuvre des deux principales architectures à modulation de charge : Outphasing (OPA) et Doherty (DPA). L'architecture Outphasing est étudiée sous ses différentes formes et une nouvelle méthode de conception unifiée est proposée pour les combineurs OPA. Une seconde analyse est menée sur les combineurs DPA, aboutissant à une nouvelle méthode d'analyse capable de déterminer le back-off maximal réalisable par une architecture de combineur donnée en mode Doherty. Contrairement aux travaux existants, la méthode proposée détermine également les courants d'attaque requis aux entrées du combineur pour maintenir des conditions idéales de Doherty dans toute la région de Doherty. Afin de valider cette technique, un DPA en classe E à deux étages avec un combineur LC compact est conçu et implémenté en utilisant la technologie RFSOI en 130nm. Les performances mesurées sont en ligne avec l'état de l'art puisque le PA atteint un PAE maximum de 51% à une puissance de sortie de 32dBm sous une tension d'alimentation de 3,4V à 2,3GHz en mode CW. De 2,1 GHz à 2,5 GHz, le PA présente une puissance de sortie moyenne et un PAE supérieur à 26,9 dBm et 39% respectivement à -35 dBc E-UTRA ACLR lors de l'utilisation d'un signal de liaison montante LTE 10MHz-50RB QPSK avec prédistortion digitale (DPD) sans mémoire. À 2,3GHz, le PA atteint un Pout linéaire et un PAE de 28,85 dBm et 42,8% respectivement. Ensuite, une analyse de système est effectuée sur le système émetteur Outphasing (OTX) qui contient à la fois l'OPA RF ainsi que l'interface de traitement du signal et l'interface analogique connue sous le nom de séparateur de composantes signal (SCS). La conception et le fonctionnement de l'OPA en classe B et en classe E sont étudiés, ce qui aboutit à la conception d'un OPA de classe E à double entrée. Différentes architectures de DPD sont étudiées, notamment la DPD tabulée (look-up table) et les architectures basées sur la modélisation comportementale. Enfin, une architecture DPD IN-SCS est proposée comme une nouvelle solution potentielle permettant l'intégration du bloc DPD dans le SCS, fournissant une base pour de futures recherchesThe increasing complexity of modulation schemes brought on by the evolution of mobile communication standards has led to high peak to average power ratio (PAPR) signals. As a result, traditional linear power amplifier (PA) architectures are no longer suitable as they exhibit low average efficiency when operating with such signals. One of the possible solutions to this issue is load modulation-based architectures which are capable of providing higher average efficiency. This work focuses on the analysis, design, and implementation of the two main load modulation architectures: Outphasing (OPA) and Doherty (DPA). The Outphasing architecture is studied under its different forms and a new unified design method is proposed for OPA combiners. A second analysis is conducted on DPA combiners, resulting in a new analysis method capable of determining the maximum back-off achievable by a given combiner architecture in Doherty mode. Unlike existing works, the proposed method also determines the required driving currents at the inputs of the combiner to maintain ideal Doherty conditions throughout the Doherty region. In order to validate this technique, a twostage class-E DPA with compact LC combiner is designed and implemented using 130nm RF-SOI. Measured performance is in-line with the state of the art as the PA achieves a peak PAE of 51% at 32dBm output power under 3.4V supply voltage at 2.3GHz in CW mode. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at -35dBc E-UTRA ACLR when using a 10MHz50RB QPSK LTE uplink signal with memoryless digital predistortion (DPD). At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively. Next, a system analysis is performed on the Outphasing transmitter system (OTX) which contains both the RF OPA as well as the signal processing interface and analog interface known as the signal component separator (SCS). The design and operation of OPA in both class-B and class-E is studied resulting in a dual-input class-E OPA design. Different DPD architectures are studied including the look-up table DPD and the behavioural modelling-based architectures. Finally, an IN-SCS DPD architecture is put forward as a potential novel solution allowing the integration of the DPD block into the SCS providing abasis for future research
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Coudrain, Perceval. "Contribution au développement d'une technologie d'intégration tridimensionnelle pour les capteurs d'images CMOS à pixels actifs." Toulouse, ISAE, 2009. http://www.theses.fr/2009ESAE0005.
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Durant la dernière décennie, le marché des capteurs d'images électroniques a connu un essor considérable, appuyé par la démocratisation des applications nomades. Si le domaine a longtemps été dominé par les dispositifs CCD, les capteurs APS (Active Pixel Sensors) se sont depuis largement imposés, aidés par la pénétration des technologies CMOS. Une miniaturisation soutenue de la taille des pixels a conduit à des résolutions d'images élevées, mais a fait émerger des limitations sur les performances électro-optlques. Si celles-ci ont pu être partiellement compensées par des adaptations de la technologie, la perspective de pixels sub-microniques nécessite en revanche l'introduction d'architectures innovantes. Un pixel tridimensionnel est ici étudié, permettant de dissocier verticalement les fonctions de photo-détection et de lecture sur deux niveaux actifs. En plus de tirer les bénéfices d'une illumination par la face arrière, cette configuration permet une large augmentation de la surface photosensible et de la charge à saturation. Malgré l'engouement rencontré ces dernières années pour les technologies tridimensionnelles, la réalisation d'un pixel CMOS fortement miniaturisé (<2 µm) en 3D révèle une difficulté majeure, liée au micro-dimensionnement des interconnexions 3D entre les deux niveaux de circuit, incompatible avec les performances d'alignement lors du collage de circuits. Une construction séquentielle est ici proposée pour contrecarrer cette limitation. Les briques technologiques associées dans cette approche sont étudiées à partir de pixels de 1. 4 µm : transfert de couche SOI sur circuit par collage moléculaire, fabrication de transistors FDSOI à faible budget thermique (<700°C), gravure de contacts à fort facteur de forme. Les performances en bruit basse fréquence sont comparées à celles de technologies planaires sur la base de mesures de transistors élémentaires. Plusieurs solutions technologiques alternatives sont finalement investiguées.
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Massy, Damien. "Etude de la dynamique de fracture dans la technologie Smart Cut™." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAY101.
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La technologie Smart Cut™ est un procédé générique de transfert de couches minces utilisé pour la fabrication des substrats silicium sur isolant (SOI) à l’échelle industrielle. L’implantation d’ions légers dans un substrat de silicium oxydé mène à la formation d’une zone fragilisée enterrée au sein du cristal. Ce substrat implanté est ensuite solidarisé à un support mécanique grâce à la technique de collage par adhésion moléculaire. Sous l’effet de la température, les espèces implantées évoluent sous la forme de microfissures qui se développent de manière parallèle à la surface. Après recuit, une fracture se déclenche au niveau de la zone implantée et permet le report de la fine couche monocristalline. L’objet de cette thèse est d’étudier l’aspect dynamique de cette étape de fracture.Pour ce faire, la vitesse de rupture et la déformation des plaques à l’arrière du front de fracture ont tout d’abord été mesurées à l’aide d’un montage optique original qui a ensuite été étendu aux études sur plaque entière 300mm. Ces données ont ensuite été modélisées. Dans un deuxième temps, l’interaction entre le front de fracture et des ondes acoustiques émises dynamiquement au cours de sa propagation a été étudiée. Celle-ci conduit à l’apparition récurrente d’un motif périodique sur le faciès de rupture qui consiste en une très faible variation de rugosité sur de très grandes périodes (mm). Des mesures expérimentales permettent tout d’abord de mettre en évidence cette émission acoustique et d’étudier ses caractéristiques. La modélisation physique du phénomène puis sa simulation numérique permettent ensuite de retrouver la forme typique de ce motif. Enfin, des solutions technologiques sont proposées pour empêcher son apparition sur le faciès de rupture des plaques SOIThe Smart Cut™ technology is a generic way of transferring very thin layers of crystalline material onto a mechanical substrate. It is currently the industrial standard for Silicon On Insulator (SOI) manufacturing. The implantation of relatively high doses of gas ions in a thermally oxidized silicon substrate leads to the formation of a buried weakened layer in the crystal. The implanted wafer is then bonded onto a host substrate using direct wafer bonding. Under annealing, the implanted species evolve into microcracks lying parallel to the surface, and a controlled fracture process finally occurs along the implanted layer. The aim of this thesis is to study the dynamics of this fracture step.First of all, the fracture velocity and the deformation profile behind the crack tip have been measured using an original optical setup, which has been extended to full wafer studies. A model has been established to explain these data. Then, the interaction of the fracture front with self-generated acoustic waves has been studied. This interaction leads to the appearance of a macroscopic periodic pattern on post-split SOI wafers which is made of small variations of the SOI roughness on very large periods (mm). Experimental studies are first carried out to look at the fracture acoustic emission for different experimental conditions. Numerical simulations based on acoustic phase calculations are then performed to recover the typical pattern shape, with results consistent with experimental data. Finally, technologic solutions are proposed to prevent the pattern formation on the post-split SOI wafers
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Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.
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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.
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Pirro, Luca. "Caractérisation et modélisation électrique de substrats SOI avancés." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT096/document.
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Les substrats Silicium-sur-Isolant (SOI) représentent la meilleure solution pour obtenir des dispositifs microélectroniques ayant de hautes performances. Des méthodes de caractérisation électrique sont nécessaires pour contrôler la qualité SOI avant la réalisation complète de transistors. La configuration classique utilisée pour les mesures du SOI est le pseudo-MOFSET. Dans cette thèse, nous nous concentrons sur l'amélioration des techniques autour du Ψ-MOFSET, pour la caractérisation des plaques SOI et III-V. Le protocole expérimental de mesures statiques ID-VG a été amélioré par l'utilisation d'un contact par le vide en face arrière, permettant ainsi d'augmenter la stabilité des mesures. De plus, il a été prouvé que ce contact est essentiel pour obtenir des valeurs correctes de capacité avec les méthodes split-CV et quasi-statique. L'extraction des valeurs de Dit avec split-CV a été explorée, et un model physique nous a permis de démontrer que ceci n'est pas possible pour des échantillons SOI typiquement utilisés, à cause de la constante de temps reliée à la formation du canal. Cette limitation a été résolue un effectuant des mesures de capacité quasi-statique (QSCV). La signature des Dit a été mise en évidence expérimentalement et expliquée physiquement. Dans le cas d'échantillons passivés, les mesures QSCV sont plus sensibles à l'interface silicium-BOX. Pour les échantillons non passivés, un grand pic dû à des défauts d'interface apparait pour des valeurs d'énergie bien identifiées et correspondant aux défauts à l'interface film de silicium-oxyde natif. Nous présentons des mesures de bruit à basses fréquences, ainsi qu'un model physique démontrant que le signal émerge de régions localisées autour des contacts source et drainSilicon-on-insulator (SOI) substrates represent the best solution to achieve high performance devices. Electrical characterization methods are required to monitor the material quality before full transistor fabrication. The classical configuration used for SOI measurements is the pseudo-MOSFET. In this thesis, we focused on the enrichment of techniques in Ψ-MOSFET for the characterization of bare SOI and III-V wafers. The experimental setup for static ID-VG was improved using a vacuum contact for the back gate, increasing the measurement stability. Furthermore, this contact proved to be critical for achieving correct capacitance values with split-CV and quasi-static techniques (QSCV). We addressed the possibility to extract Dit values from split-CV and we demonstrated by modeling that it is impossible in typical sized SOI samples because of the time constant associated to the channel formation. The limitation was solved performing QSCV measurements. Dit signature was experimentally evidenced and physically described. Several SOI structures (thick and ultra-thin silicon films and BOX) were characterized. In case of passivated samples, the QSCV is mostly sensitive to the silicon film-BOX interface. In non-passivated wafers, a large defect related peak appears at constant energy value, independently of the film thickness; it is associated to the native oxide present on the silicon surface. For low-frequency noise measurements, a physical model proved that the signal arises from localized regions surrounding the source and drain contacts
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Petit, Antoine. "Initiation de la fracture dans la technologie Smart Cut." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALY019.
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L’objet de cette thèse est d’étudier l’initiation de la fracture dans la technologie Smart CutTM, utilisée pour la fabrication industrielle de substrats de type silicium sur isolant (SOI). Pour cela, des études statistiques ont permis de quantifier les variabilités temporelles et spatiales du phénomène d’initiation de la fracture. Ces études ont permis de déceler l’influence de certains paramètres de fabrication sur l’initiation de la fracture mais ont aussi révélé son caractère aléatoire. Puis, le phénomène de croissance des microfissures enterrées, qui conduit in fine au déclenchement de la fracture, a été caractérisé grâce à l’utilisation de la technique de microscopie confocale en lumière infra-rouge. Cela a montré l’existence d’un comportement particulier des microfissures situées dans les zones préférentielles d’initiation qui sont à l’origine de l’initiation spontanée de la fracture. Un modèle a été proposé pour montrer comment le développement particulier de ces microfissures et leur rupture en bord d’échantillon, ou sur un défaut de collage, peut déclencher une fracture. Ensuite, l’initiation mécanique, réalisée par application d’une contrainte au niveau de l’interface de collage des substrats, a été étudiée.Un nouveau dispositif, développé dans cette thèse, a permis de mesurer la force nécessaire pour initier la fracture. Ces résultats ont ensuite été mis en relation avec des mesures de la quantité de gaz présente à l’interface de fracture pour comprendre l’évolution de la force d’initiation en fonction de différents paramètres expérimentaux. Pour finir, un procédé d’initiation mécanique compatible avec une fabrication industrielle de substrats SOI, et permettant d’améliorer le contrôle de l’étape de fracture, a été développéThe purpose of this thesis is to study the fracture initiation in the Smart CutTM technology, used for the industrial production of silicon-on-insulator (SOI) substrates. For this purpose, statistical studies allowed us to quantify the temporal and spatial variability of the fracture initiation phenomenon. These studies helped to detect the influence of certainmanufacturing parameters on fracture initiation, but also revealed its randomnature. Then, the growth phenomenon of buried microcracks, which ultimately leads to fracture initiation, was characterized using the technique of confocal microscopy with infrared light. This showed the existence of a particular behaviour of the microcracks located in the preferential initiation zones which are at the origin of the spontaneous initiation of the fracture. A model has been proposed to showhowthe particular development of these microcracks and their rupture at the edge of the sample, or on a bonding defect, can trigger a fracture. Then, mechanical initiation, performed by applying stress at the bonding interface of the substrates, was studied. A new device, developed in this thesis, allowed to measure the force necessary to initiate the fracture. These results were then related to measurements of the gas quantity at the fracture interface in order to understand the evolution of the initiation force as a function of different experimental parameters. Finally, a mechanical initiation process compatible with an industrial SOI substrate fabrication, and allowing to improve the control of the fracture step, was developed
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Diab, Amer El Hajj. "Nouvelles méthodes pseudo-MOSFET pour la caractérisation des substrats SOI avancés." Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT060/document.
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Les architectures des dispositifs Silicium-Sur-Isolant (SOI) représentent des alternatives attractives par rapport à celles en Si massif grâce à l’amélioration des performances des transistors et des circuits. Dans ce contexte, les plaquettes SOI doivent être d’excellente qualité.Dans cette thèse nous développons des nouveaux outils de caractérisation électrique et des modèles pour des substrats SOI avancés. La caractérisation classique pseudo-MOSFET (-MOSFET) pour le SOI a été revisitée et étendue pour des mesures à basses températures. Les variantes enrichies de -MOSFET, proposées et validées sur des nombreuses géométries, concernent des mesures split C-V et des mesures bruit basse fréquence. A partir des courbes split C-V, une méthode d'extraction de la mobilité effective a été validée. Un modèle expliquant les variations de la capacité avec la fréquence s’accorde bien avec les résultats expérimentaux. Le -MOSFET a été aussi étendu pour les films SOI fortement dopés et un modèle pour l'extraction des paramètres a été élaboré. En outre, nous avons prouvé la possibilité de caractériser des nanofils de SiGe empilés dans des architectures 3D, en utilisant le concept -MOSFET. Finalement, le SOI ultra-mince dans la configuration -MOSFET s'est avéré intéressant pour la détection des nanoparticules d'orSilicon-On-Insulator (SOI) device architectures represent attractive alternatives to bulk ones thanks to the improvement of transistors and circuits performances. In this context, the SOI starting material should be of prime quality.In this thesis, we develop novel electrical characterization tools and models for advanced SOI substrates. The classical pseudo-MOSFET (-MOSFET) characterization for SOI was revisited and extended to low temperatures. Enriched variants of -MOSFET, proposed and demonstrated on numerous geometries, concern split C-V and low-frequency noise measurements. Based on split C-V, an extraction method for the effective mobility was validated. A model explaining the capacitance variations with the frequency shows good agreement with the experimental results. The -MOSFET was also extended to highly doped SOI films and a model for parameter extraction was derived. Furthermore, we proved the possibility to characterize SiGe nanowire 3D stacks using the -MOSFET concept. Finally thin film -MOSFET proved to be an interesting, technology-light detector for gold nanoparticles
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Benea, Licinius Pompiliu. "Mesures de potentiel hors-équilibre sur substrats SOI : implémentation et applications pour la détection biochimique." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT052.
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Dans cette thèse, nous proposons un nouveau paradigme pour la détection biochimique basé sur le potentiel hors équilibre dans des substrats de silicium sur isolant (SOI) utilisé dans la configuration Ψ-MOSFET. Ceci est typiquement utilisé pour la caractérisation SOI et il a la structure d’un transistor inversé dans lequel le courant à travers le film de silicium est mesuré par deux pointes métalliques à pression contrôlée et qui est commandé par la tension de grille arrière appliquée sur le substrat mécanique du SOI. Le canal est proche de la surface supérieure de cette structure, permettant une influence directe des charges déposées sur la conduction du pseudo-transistor. L’originalité de notre travail réside dans le fait qu’au lieu de mesurer un décalage dû à des charges sur les caractéristiques statiques courant-tension, nous avons développé une nouvelle méthode basée sur le potentiel hors équilibre, qui apparaisse en raison du manque de porteurs au moment de la transition entre les régimes d’accumulation et d’inversion. L'injection de charge à travers les sondes métalliques pour la formation de canaux est par conséquent essentielle pour obtenir cet effet. Etonnamment, les pointes métalliques posées sur le film de silicium présentent expérimentalement un comportement ohmique, ce que nous avons pu expliquer en utilisant l'apparition de la phase métallique métastable trouvée à hautes contraintes du silicium par nanoindentation, crée suite à la pression appliquée par les pointes. De plus, nous avons présenté une configuration simplifiée pour les mesures de potentiel, qui a montré une grande polyvalence et une grande stabilité en par rapport à la pression appliquée et la position des pointes. Les mesures ont été répliquées par des simulations TCAD, qui ont réussi montrer que l’influence des charges déposées sur le film de silicium pouvait être mesurée par cette méthode. Enfin, l’application de la méthode du potentiel hors équilibre à la biodétection a été réalisée par une étude incrémentale allant de méthodes de fonctionnalisation de base sur silicium jusqu’à la détection d’ADN. La réponse électrique était proportionnelle à la concentration en ADN et une limite de détection de 1 µM a été estimée à partir des résultats expérimentaux. La preuve de concept de cette nouvelle méthode de lecture peut être appliquée à d’autres dispositifs à effet de champ (nanofils) et à d’autres applications biochimiquesIn this thesis we propose a new paradigm for biochemical detection based on the out-of-equilibrium body potential in silicon on insulator (SOI) substrates was used in the Ψ-MOSFET configuration. This is typically used for SOI characterization and is an upside-down transistor in which the current though the silicon film is measured by two metallic pressure probes and which is driven by the back gate voltage applied on the bulk of the SOI. The channel is close to the top structure of the SOI, allowing a straightforward influence of any deposited charges on the conduction of the pseudo transistor. The originality of our work resides in the fact that instead of measuring a shift due to charges on the static I-V characteristics, we developed a new method based on the out-of-equilibrium body potential, which appears due to the lack of carriers at the transition between the accumulation and inversion regimes. Charge injection through the metallic probes for channel formation is consequently critical for this effect. Surprisingly, the metal probes on the silicon film show experimentally an ohmic behaviour, which we explained using the emergence of the metallic metastable high pressure phase of silicon by nanoindentation, due to the pressure applied by the pressure probes. Furthermore, we presented a simplified setup for the body potential measurements, which showed a great versatility and stability with regard to the pressure applied on the probes and the position of the probes. The measurements were replicated through TCAD simulations, which ultimately showed that the influence of deposited charges on the silicon film can be measured using this method. Finally, the application of the body potential method for biosensing was realized by an incremental study starting from basic silicon functionalization methods to the detection of DNA. The electric response was proportional to the DNA concentration and a limit of detection of 1µM was estimated from the experimental results. The proof of concept for this new reading method can be implemented to other field-effect devices (i.e. nanowires) and for other biochemical applications