Log in

Relevant bibliographies by topics / Silicon-on-insulator (SOI) / Journal articles

To see the other types of publications on this topic, follow the link: Silicon-on-insulator (SOI).

Journal articles on the topic 'Silicon-on-insulator (SOI)'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 June 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Silicon-on-insulator (SOI).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Tian, Li, Xiao Ying Li, Da Yong Qiao, and Bin Yan. "High-Surface-Quality and Wider-Modulation-Range Continuous Face-Sheet Micro Deformable Mirror Based on SOI." Advanced Materials Research 60-61 (January 2009): 185–88. http://dx.doi.org/10.4028/www.scientific.net/amr.60-61.185.

Full text

Abstract:

A new type of continuous face-sheet micro deformable mirror was designed and fabricated based on SOI (Silicon-on-Insulator) technology for high optical efficiency applications in adaptive optics system. SOI provided a Silicon-Insulator-Silicon structure, and the insulator-layer of the three-layer structure was taken as etch-stop layer in deep silicon etching, which made the suspended bulk silicon membrane obtained easily. And the reflective face did not suffer etch-step due to the protection of insulator-layer. The mirror was composed of 5-um-thick and 10-mm-diameter flexible bulk silicon membrane, and actuated by 69 electrostatic actuators which evaporated on glass substrate. SOI and glass wafer were bonded together by anodic bonding, forming a separation gap of 15um between the mirror face and electrostatic pad, which offered a maximum effectual displacement of 5um by considering the pull-in effect. Fabrication process was introduced in detail. Bulk silicon micromachining was employed, methods mainly include Inductivity Coupled Plasma (ICP) etching and Si/Glass anodic bonding technique.

APA, Harvard, Vancouver, ISO, and other styles

2

HADDAB, Y., V. MOSSER, M. LYSOWEC, J. SUSKI, L. DEMEUS, C. RENAUX, S. ADRIAENSEN, and D. FLANDRE. "LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES." Fluctuation and Noise Letters 04, no. 02 (June 2004): L345—L354. http://dx.doi.org/10.1142/s021947750400194x.

Full text

Abstract:

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

APA, Harvard, Vancouver, ISO, and other styles

3

Colinge, J. P. "Transconductance of Silicon-on-insulator (SOI) MOSFET's." IEEE Electron Device Letters 6, no. 11 (November 1985): 573–74. http://dx.doi.org/10.1109/edl.1985.26234.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Colinge, Jean-Pierre. "Silicon-on-lnsulator Technology: Past Achievements and Future Prospects." MRS Bulletin 23, no. 12 (December 1998): 16–19. http://dx.doi.org/10.1557/s0883769400029778.

Full text

Abstract:

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

APA, Harvard, Vancouver, ISO, and other styles

5

Schmid, J. H., P. Cheben, S. Janz, J. Lapointe, E. Post, A. Delâge, A. Densmore, B. Lamontagne, P. Waldron, and D. X. Xu. "Subwavelength Grating Structures in Silicon-on-Insulator Waveguides." Advances in Optical Technologies 2008 (July 13, 2008): 1–8. http://dx.doi.org/10.1155/2008/685489.

Full text

Abstract:

First implementations of subwavelength gratings (SWGs) in silicon-on-insulator (SOI) waveguides are discussed and demonstrated by experiment and simulations. The subwavelength effect is exploited for making antireflective and highly reflective waveguide facets as well as efficient fiber-chip coupling structures. We demonstrate experimentally that by etching triangular SWGs into SOI waveguide facets, the facet power reflectivity can be reduced from 31% to <2.5%. Similar structures using square gratings can also be used to achieve high facet reflectivity. Finite difference time-domain simulations show that >94% facet reflectivity can be achieved with square SWGs for 5 μm thick SOI waveguides. Finally, SWG fiber-chip couplers for SOI photonic wire waveguides are introduced, including design, simulation, and first experimental results.

APA, Harvard, Vancouver, ISO, and other styles

6

Placidi, Marcel, Marcin Zielinski, Gabriel Abadal, Josep Montserrat, and Phillippe Godignon. "SiC Freestanding Micromechanical Structures on Silicon-On-Insulator Substrates." Materials Science Forum 615-617 (March 2009): 617–20. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.617.

Full text

Abstract:

The fabrication of freestanding SiC microstructures on Silicon-On-Insulator (SOI) and semi-insulating Silicon substrates is reported. SiC layers were grown on SOI and semi-insulating Si by chemical vapour deposition (CVD) and to avoid the instability currently obtained in SOI structures, the growth process parameters have been optimized. Isotropic wet chemical etching of the Si sacrificial layer released the electrostatic SiC microstructures patterned by dry etching. Moreover a new concept for reducing the gap between resonators and electrodes by the uses of bistable mobile electrodes is introduced.

APA, Harvard, Vancouver, ISO, and other styles

7

NASTAUSHEV, Yu V., T. A. GAVRILOVA, M. M. KACHANOVA, O. V. NAUMOVA, I. V. ANTONOVA, V. P. POPOV, L. V. LITVIN, D. V. SHEGLOV, A. V. LATYSHEV, and A. L. ASEEV. "FIELD EFFECT NANOTRANSISTOR ON ULTRATHIN SILICON-ON-INSULATOR." International Journal of Nanoscience 03, no. 01n02 (February 2004): 155–60. http://dx.doi.org/10.1142/s0219581x04001936.

Full text

Abstract:

Peculiarities of the fabrication of field effect transistor (FET) at nanoscaled size on ultrathin silicon-on-insulator (SOI) was studied in details. Two types of FET transistor were successfully realized: in-plane-gate FET (IPGFET) with 40 nm minimum channel size and multichannel top-gate MOSFET on silicon-on-insulator. The deep submicron top-gate of Ti/Au embraces each of the conductive oxidized silicon wires placed with 400 nm pitch. The type and concentration of carries in a conductive channel of the ultrathin SOI was controlled by a bottom gate. The fabricated transistors demonstrated high transconductance and low threshold voltage. Some results of electron properties of the nano-FET transistors are presented.

APA, Harvard, Vancouver, ISO, and other styles

8

Hishinuma, Shinsuke, Naoki Kimori, Yuichiro Kumai, Kouki Oku, Tetsuya Takahashi, Daiki Irokawa, Emiko Sugizaki, et al. "Fabrication of Condenser Microphones on Silicon on Insulator Wafer." Advanced Materials Research 306-307 (August 2011): 193–200. http://dx.doi.org/10.4028/www.scientific.net/amr.306-307.193.

Full text

Abstract:

A silicon condenser microphone on an SOI (silicon on insulator) substrate using only one photo mask was fabricated. This microphone consists of a diaphragm with the thickness of 20 μm and the diameter of 2 mm, a SiO2 insulative spacer (4-μm-thick buried oxide), and a 450-μm-thick silicon back plate with the meshed structures having extremely small (60 μm) hexagonal shaped acoustic holes. The gap between the 20-μm-thick silicon diaphragm and the back plate is 4 μm, which is determined by the thickness of the buried oxide in the SOI wafer. This microphone was confirmed to function as a static pressure sensor. The SOI microphone was also connected to an amplifier circuit, and exposed to the sound pressure of 110 dB at the frequency of 1 kHz. The microphone clearly responded to the input sound, and the output ac voltage of approximately 40 V was detected.

APA, Harvard, Vancouver, ISO, and other styles

9

ZHANG, BO, JING CHEN, XI WANG, AIMIN WU, JIEXIN LUO, XI WANG, MIAO ZHANG, YUXIN WU, JIANJUN ZHU, and HUI YANG. "EPITAXIAL LATERAL OVERGROWTH OF GaN ON SILICON-ON-INSULATOR." Modern Physics Letters B 23, no. 15 (June 20, 2009): 1881–87. http://dx.doi.org/10.1142/s0217984909020047.

Full text

Abstract:

From a single process, GaN layers were laterally overgrown on maskless stripe-patterned (111) silicon-on-insulator (SOI) substrates by metalorganic chemical vapor deposition. The influence of stress on the behavior of dislocations at the coalescence during growth was observed using transmission electron microscopy (TEM). Improvement of the crystalline quality of the GaN layer was demonstrated by TEM and micro-Raman spectroscopy. Furthermore, the benefits of SOI substrates for GaN growth are also discussed.

APA, Harvard, Vancouver, ISO, and other styles

10

Givargizov, Eugene I., Alexander B. Limanov, Gennadi D. Prjakhin, and Vladimir I. Vaganov. "Silicon-on-insulator (SOI) structures for pressure sensors." Sensors and Actuators A: Physical 28, no. 3 (August 1991): 215–22. http://dx.doi.org/10.1016/0924-4247(91)85010-l.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Du, Li Dong, Zhan Zhao, Li Xiao, Meng Ying Zhang, and Zhen Fang. "A SOI-MEMS Piezoresistive Atmosphere Pressure Sensor." Key Engineering Materials 562-565 (July 2013): 394–97. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.394.

Full text

Abstract:

In this paper, a SOI-MEMS (silicon on insulator- micro electro mechanical system) pizeoresistive atmosphere pressure sensor is presented using anodic bonding. Differently from the prevailing fabrication process of silicon piezoresistive pressure sensor: the device layer monocrystalline of SOI silicon wafer is used as the strain gauge with a simple deep etching process; and the SiO2 layer of SOI silicon wafer as the insulator between strain gauge and substrate. The whole fabrication processes of the designed sensor are very simple, and can reduce the cost of sensor. The Pressure-Voltage characteristic test results suggest a precision within 0.14% in linear fitting. It is shown that the temperature coefficient is 2718ppm/°C from the Typical temperature curve of the pressure sensors.

APA, Harvard, Vancouver, ISO, and other styles

12

LEPKOWSKI, WILLIAM, SETH J. WILK, M. REZA GHAJAR, ANURADHA PARSI, and TREVOR J. THORNTON. "SILICON-ON-INSULATOR MESFETS AT THE 45NM NODE." International Journal of High Speed Electronics and Systems 21, no. 01 (March 2012): 1250012. http://dx.doi.org/10.1142/s0129156412500127.

Full text

Abstract:

Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (IDSAT≥ 100mA/mm ), high operating frequency (fmax> 35 GHz ) or enhanced breakdown voltage (VBD> 25 V ). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications.

APA, Harvard, Vancouver, ISO, and other styles

13

Feng, Song, and Bin Xue. "Research into Two Photonic-Integrated Waveguides Based on SiGe Material." Materials 13, no. 8 (April 16, 2020): 1877. http://dx.doi.org/10.3390/ma13081877.

Full text

Abstract:

SiGe (Silicon Germanium) is a common semiconductor material with many excellent properties, and many photonic-integrated devices are designed and fabricated with SiGe material. In this paper, two photonic-integrated SiGe waveguides are researched, namely the SiGe-SOI (Silicon Germanium-Silicon-On-Insulator) waveguide and the SiGe-OI (Silicon Germanium-On-Insulator) waveguide. In order to verify which structure has the better waveguide performance, two waveguide structures are built, and the effective refractive indexes and the loss characteristics of the two waveguides are analyzed and compared. By simulation, the SiGe-OI optical waveguide has better losses characteristics at a wavelength of 1.55 μm. Finally, SiGe-OI and SiGe-SOI waveguides are fabricated and tested to verify the correctness of theoretical analysis, and the experimental results show that the transmission losses of the SiGe-OI waveguide are respectively decreased by 36.6% and 28.3% at 400 nm and 600 nm waveguide width in comparison with the SiGe-SOI waveguide. The results also show that the SiGe-OI waveguide has better loss characteristics than those of the SiGe-SOI waveguide at the low Ge content.

APA, Harvard, Vancouver, ISO, and other styles

14

Jung, C. O., S. J. Krause, and S. R. Wilson. "Structural changes in silicon-on-insulator material during post-implantation annealing." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 736–37. http://dx.doi.org/10.1017/s0424820100145054.

Full text

Abstract:

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

APA, Harvard, Vancouver, ISO, and other styles

15

Goodson, K. E., M. I. Flik, L. T. Su, and D. A. Antoniadis. "Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits." Journal of Heat Transfer 117, no. 3 (August 1, 1995): 574–81. http://dx.doi.org/10.1115/1.2822616.

Full text

Abstract:

Field-effect transistors (FETs) in conventional electronic circuits are in contact with the high-thermal-conductivity substrate. In contrast, FETs in novel silicon-on-insulator (SOI) circuits are separated from the substrate by a thermally resistive silicon-dioxide layer. The layer improves the electrical performance of SOI circuits. But it impedes conduction cooling of transistors and interconnects, degrading circuit reliability. This work develops a technique for measuring the channel temperature of SOI FETs. Data agree well with the predictions of an analytical thermal model. The channel and interconnect temperatures depend strongly on the device and silicon-dioxide layer thicknesses and the channel–interconnect separation. This research facilitates the thermal design of SOI FETs to improve circuit figures of merit, e.g., the median time to failure (MTF) of FET–interconnect contacts.

APA, Harvard, Vancouver, ISO, and other styles

16

FAN, JIE, XIAORONG LUO, BO ZHANG, and ZHAOJI LI. "NOVEL HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE WITH COMPOSITE DIELECTRIC BURIED LAYER." Journal of Circuits, Systems and Computers 22, no. 10 (December 2013): 1340029. http://dx.doi.org/10.1142/s021812661340029x.

Full text

Abstract:

A novel silicon-on-insulator (SOI) high voltage device with a composite dielectric buried layer (CD SOI) is proposed in this paper. In the proposed structure, the composite dielectric buried layer consists of Si 3 N 4 dielectric and low-k (relative permittivity) dielectric. The electric field strength in the buried layer is enhanced by the low-k dielectric. The Si 3 N 4 dielectric in the buried layer not only modulates the electric field distribution in the drift region, but also provides a heat conduction path for the SOI layer and alleviates the self-heating effect (SHE). The breakdown voltage (BV) = 362 V for CD SOI is obtained by simulation on a 1 μm SOI layer over 2 μm buried layer, which is enhanced by 26% compared with that of conventional SOI.

APA, Harvard, Vancouver, ISO, and other styles

17

Estakhrian Haghighi, Amir Reza, and Mojtaba Mohamadi. "The Silicon Plates in Buried Oxide for Enhancement of the Breakdown Voltage in SOI MESFET." Applied Mechanics and Materials 538 (April 2014): 58–61. http://dx.doi.org/10.4028/www.scientific.net/amm.538.58.

Full text

Abstract:

This paper introduces a novel SOI MESFET which enhancement breakdown voltage (VBR) by modifying electric field distribution. To achieve high enhancement of the VBR utilized three Silicon plates in buried oxide of the silicon on insulator metal semiconductor field effect transistor (SOI MESFET). This change in the SOI MESFET structure leads to controlled electric field distribution , increase VBR and Output Resistance (RO). The numerical simulation results show that the VBR of the Silicon Plates SOI MESFET (SP-SOI MESFET) structure improves by 50% compared with that of the conventional SOI MESFET (C-SOI MESFET) structure. As a result, the SP-SOI MESFET structure has superior electrical performances in comparison with the conventional structure.

APA, Harvard, Vancouver, ISO, and other styles

18

Yu, Lin, Hossein Pajouhi, Molly R. Nelis, Jeffrey F. Rhoads, and Saeed Mohammadi. "Tunable, Dual-Gate, Silicon-on-Insulator (SOI) Nanoelectromechanical Resonators." IEEE Transactions on Nanotechnology 11, no. 6 (November 2012): 1093–99. http://dx.doi.org/10.1109/tnano.2012.2212028.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Baerg, W., J. C. Sturm, T. L. Hwa, H. Y. Lin, B. B. Siu, C. H. Ting, J. C. Tzeng, and J. F. Gibbons. "A seeded-channel silicon-on-insulator (SOI) MOS technology." IEEE Electron Device Letters 6, no. 12 (December 1985): 668–70. http://dx.doi.org/10.1109/edl.1985.26268.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Kan, S. C., T. T. H. Eng, S. S. Y. Sin, and G. K. L. Wong. "Silicon-on-insulator (SOI) movable integrated optical waveguide technology." Sensors and Actuators A: Physical 54, no. 1-3 (June 1996): 679–83. http://dx.doi.org/10.1016/s0924-4247(97)80037-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Amanti, Francesco, Greta Andrini, Fabrizio Armani, Fabrizio Barbato, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, et al. "Integrated Photonic Passive Building Blocks on Silicon-On-Insulator Platform." Photonics 11, no. 6 (May 23, 2024): 494. http://dx.doi.org/10.3390/photonics11060494.

Full text

Abstract:

Integrated photonics on Silicon-On-Insulator (SOI) substrates is a well developed research field that has already significantly impacted various fields, such as quantum computing, micro sensing devices, biosensing, and high-rate communications. Although quite complex circuits can be made with such technology, everything is based on a few ’building blocks’ which are then combined to form more complex circuits. This review article provides a detailed examination of the state of the art of integrated photonic building blocks focusing on passive elements, covering fundamental principles and design methodologies. Key components discussed include waveguides, fiber-to-chip couplers, edges and gratings, phase shifters, splitters and switches (including y-branch, MMI, and directional couplers), as well as subwavelength grating structures and ring resonators. Additionally, this review addresses challenges and future prospects in advancing integrated photonic circuits on SOI platforms, focusing on scalability, power efficiency, and fabrication issues. The objective of this review is to equip researchers and engineers in the field with a comprehensive understanding of the current landscape and future trajectories of integrated photonic components on SOI substrates with a 220 nm thick device layer of intrinsic silicon.

APA, Harvard, Vancouver, ISO, and other styles

22

Colinge, Jean-Pierre, and Robert W. Bower. "Silicon-on-lnsulator Technology." MRS Bulletin 23, no. 12 (December 1998): 13–15. http://dx.doi.org/10.1557/s0883769400029766.

Full text

Abstract:

Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.

APA, Harvard, Vancouver, ISO, and other styles

23

Kappert, Holger, Stefan Dreiner, Dirk Dittrich, Katharina Grella, Andreas Kelberer, Miriam Klusmann, Norbert Kordas, et al. "High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000154–58. http://dx.doi.org/10.4071/hitec-wa14.

Full text

Abstract:

Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper.

APA, Harvard, Vancouver, ISO, and other styles

24

Sakurai, Yoko, Shintaro Nomura, Kenji Shiraishi, Kenji Ohmori, and Keisaku Yamada. "Photoluminescence Characteristics of Ultra-Thin Silicon-on-Insulator at Low Temperatures." Key Engineering Materials 470 (February 2011): 39–42. http://dx.doi.org/10.4028/www.scientific.net/kem.470.39.

Full text

Abstract:

We have investigated C-V and photoluminescence (PL) characteristics of ultra-thin silicon-on-insulator (SOI) samples. Thickness dependence of a free exciton (FE) PL and an electron-hole droplet (EHD) PL has been investigated. We have found a remarkable enhancement of an EHD PL with decrease in the thickness of SOI samples.

APA, Harvard, Vancouver, ISO, and other styles

25

CRISTOLOVEANU, SORIN. "FAR–FUTURE TRENDS IN SOI TECHNOLOGY: A GUESS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 343–51. http://dx.doi.org/10.1142/s0129156402001307.

Full text

Abstract:

The horizon of the Silicon On Insulator (SOI) technology is explored based on the compilation of many expert viewpoints. An SOI panel was organized at WOFE'02 with the aim of 'guessing' the shape of SOI and its industrial place in 10 years from now. SOI is expected to gradually take the role of bulk-silicon CMOS, reach the final stages of the ITRS roadmap in microelectronics, and enter the nanoelectronics world. The debate exhaustively examined the strategic and critical aspects of SOI technology. Only a few issues were retained as serious challenges.

APA, Harvard, Vancouver, ISO, and other styles

26

CRISTOLOVEANU, S., T. ERNST, D. MUNTEANU, and T. OUISSE. "ULTIMATE MOSFETs ON SOI: ULTRA THIN, SINGLE GATE, DOUBLE GATE, OR GROUND PLANE." International Journal of High Speed Electronics and Systems 10, no. 01 (March 2000): 217–30. http://dx.doi.org/10.1142/s012915640000026x.

Full text

Abstract:

We tentatively present possible architectures of Silicon On Insulator (SOI) transistors for the final stages of the scaling of silicon microelectronics. The scaling trends for conventional partially depleted and fully depleted SOI MOSFETs are critically examined. A ground plane can considerably attenuate short-channel effects. The manufacturability of extremely thin MOSFETs is demonstrated. Based on quantum calculations, we discuss the merits of double-gate transistors with volume inversion.

APA, Harvard, Vancouver, ISO, and other styles

27

Yu, Ting, and DeGui Sun. "Thermodynamic insights into Henry's constant in hyperthermal oxidation of silicon for fabricating optical waveguides." Physical Chemistry Chemical Physics 23, no. 32 (2021): 17354–64. http://dx.doi.org/10.1039/d1cp01993g.

Full text

Abstract:

Hyperthermal oxidation of silicon is envisaged to be an alternative to silicon-on-insulator (SOI) waveguide fabrication for photonic integrated circuit (PIC) devices, and thus the local oxidation of silicon (LOCOS) technique has attracted attention.

APA, Harvard, Vancouver, ISO, and other styles

28

Li, Shixin, and Zhenhua Wu. "Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET." Nanomaterials 13, no. 11 (May 23, 2023): 1709. http://dx.doi.org/10.3390/nano13111709.

Full text

Abstract:

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

APA, Harvard, Vancouver, ISO, and other styles

29

Rushan, Ni, and Lin Chenglu. "XTEM analysis of buried layer structure of silicon-on-insulator materials." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (August 1990): 666–68. http://dx.doi.org/10.1017/s0424820100176460.

Full text

Abstract:

It Is well known that a buried silicon nitride or silicon oxide layer in silicon can be formed by high dose >150 KeV nitrogen or oxygen implantation into single crystal silicon followed by high temperature annealing. This is one of the techniques to produce silicon-on-insulator (SOI) structures which is promising for a variety of potential application in VLSI, high-voltage devices, high density CMOS circuits and possibly 3-dimensional integration, etc. The main concern is how to produce a buried dielective layer with good insulating properties and with a high quality single crystal silicon overlayer on it.In this paper the microstructures of buriea silicon nitride and silicon oxide layer of the SOI materials formed by N+ or O+ implantation in single-crystal silicon are studied oy means of cross-sectional transmission electron microscopy (XTEM) and infrared (IR) absorption measurements.

APA, Harvard, Vancouver, ISO, and other styles

30

Khaleefia, Zainab Salam, Sh S. Mahdi, and S. Kh Yaseen. "Prospect of CW Raman Laser in Silicon- on- Insulator Nano-Waveguides." Iraqi Journal of Physics (IJP) 18, no. 45 (May 30, 2020): 9–20. http://dx.doi.org/10.30723/ijp.v18i45.507.

Full text

Abstract:

Numerical analysis predicts that continuous-wave (CW) Raman lasing is possible in Silicon-On-insulator (SOI) nano-waveguides, despite of presence of free carrier absorption. The scope of this paper lies on lasers for communication systems around 1550 nm wavelength. Two types of waveguide structures Strip and Rib waveguides have been incorporated. The waveguide structures have designed to be 220 nm in height. Three different widths of (350, 450, 1000) nm were studied. The dependence of lasing of the SOI Raman laser on effective carrier lifetime was discussed, produced by tow photon absorption. At telecommunication wavelength of 1550 nm, Raman lasing threshold was calculated to be 1.7 mW in Rib SOI waveguide with dimensions width (W= 450 nm) and Length (L= 25 mm). The obtained Raman lasing is the lowest reported value at relatively high reflectivities. Raman laser in SOI nano-waveguides presents the important step towards integrated on-chip optoelectronic devices.

APA, Harvard, Vancouver, ISO, and other styles

31

Milosevic, Milan, Petar Matavulj, and Goran Mashanovich. "Single mode and polarization independence in the strained silicon-on-insulator rib waveguides." Chemical Industry 62, no. 3 (2008): 119–24. http://dx.doi.org/10.2298/hemind0803119m.

Full text

Abstract:

In this paper we investigate the most popular silicon waveguide structures in the form of a silicon-on-insulator (SOI) rib waveguide. Single mode and birefringence free conditions in these relatively small waveguides are discussed and the influence of the top oxide cladding stress is analyzed. Field profiles for a wide range of waveguide cross section shapes and dimensions are systematically considered. Design guidelines for this type of SOI waveguides are presented.

APA, Harvard, Vancouver, ISO, and other styles

32

Kennedy, Noel, Ray Duffy, Luke Eaton, Dan O’Connell, Scott Monaghan, Shane Garvey, James Connolly, Chris Hatem, Justin D. Holmes, and Brenda Long. "Phosphorus monolayer doping (MLD) of silicon on insulator (SOI) substrates." Beilstein Journal of Nanotechnology 9 (August 6, 2018): 2106–13. http://dx.doi.org/10.3762/bjnano.9.199.

Full text

Abstract:

This paper details the application of phosphorus monolayer doping of silicon on insulator substrates. There have been no previous publications dedicated to the topic of MLD on SOI, which allows for the impact of reduced substrate dimensions to be probed. The doping was done through functionalization of the substrates with chemically bound allyldiphenylphosphine dopant molecules. Following functionalization, the samples were capped and annealed to enable the diffusion of dopant atoms into the substrate and their activation. Electrical and material characterisation was carried out to determine the impact of MLD on surface quality and activation results produced by the process. MLD has proven to be highly applicable to SOI substrates producing doping levels in excess of 1 × 1019 cm−3 with minimal impact on surface quality. Hall effect data proved that reducing SOI dimensions from 66 to 13 nm lead to an increase in carrier concentration values due to the reduced volume available to the dopant for diffusion. Dopant trapping was found at both Si–SiO2 interfaces and will be problematic when attempting to reach doping levels achieved by rival techniques.

APA, Harvard, Vancouver, ISO, and other styles

33

Okajima, Yoshihiko, Masaru Amemiya, Kazuo Kato, and Shin'ichiro Asai. "VLS growth of silicon whiskers on a patterned silicon-on-insulator (SOI) wafer." Journal of Crystal Growth 165, no. 1-2 (July 1996): 37–41. http://dx.doi.org/10.1016/0022-0248(96)00158-3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Tyschenko, Ida E., K. S. Zhuravlev, A. G. Cherkov, Andrzej Misiuk, and V. P. Popov. "Сavity Effect in Hydrogen Ion Implanted Silicon-On-Insulator Structures." Solid State Phenomena 108-109 (December 2005): 477–82. http://dx.doi.org/10.4028/www.scientific.net/ssp.108-109.477.

Full text

Abstract:

Cavity effect on the room-temperature (RT) photoluminescence (PL) from emitting centers in the top silicon layer of silicon-on-insulator (SOI) structure has been studied. The lightemitting centers were produced by the implantation of H+ ions and subsequent annealing at the temperatures Ta = 450-1000 oC for 5 h in an Ar ambient under pressure P = 1 - 1.2×104 bar. It has been obtained that annealing under hydrostatic pressure higher than 6 kbar prevented the outdiffusion of hydrogen in the form of gas bubbles, which took place after annealing at Ta≥600 oC under atmospheric conditions. Absence of micro-pores and gas bubbles in the top surface region creates the conditions to retain the mirror quality of the SOI/air interface. A wavelength-selective effect of the formed cavity on visible PL has been observed from the H+ ion implanted SOI structures annealed under pressure of 12 kbar. The cavity enhancement of PL emission for 23-40 times has been found at the wavelength of 515 and 560 nm.

APA, Harvard, Vancouver, ISO, and other styles

35

Chen, Qing Hua, Yan Mei Li, Ying Jun Chen, and Wen Gang Wu. "Fabrication Comparison of the SCS-Based and SOI-Based Micromachining." Advanced Materials Research 926-930 (May 2014): 881–84. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.881.

Full text

Abstract:

The two different fabrications of the Micro-Electro-Mechanical Systems (MEMS) mirrors were compared: a single-crystal-silicon (SCS)-based micromachining and a silicon-on-insulator (SOI)- based micromachining. While the SOI parts had significantly smaller curved device appearance, they were outperformed in most areas by the SCS parts. This was due primarily to the smaller stress factor in the device layer in the SOI parts compared to the polysilicon layer used in the SCS parts.

APA, Harvard, Vancouver, ISO, and other styles

36

Satoh, Hiroaki, Yuki Matsuo, Hiroshi Inokawa, and Atsushi Ono. "Investigation of Adhesion Materials for Gold Line-and-Space Surface Plasmon Antenna on SOI-MOS Photodiode." Advanced Materials Research 222 (April 2011): 201–4. http://dx.doi.org/10.4028/www.scientific.net/amr.222.201.

Full text

Abstract:

In order to improve the light sensitivity of silicon-on-insulator metal-insulator-semiconductor (SOI-MOS) photodiode, differences caused by the adhesion materials for gold (Au) line-and-space (L/S) surface plasmon (SP) antenna in MOS structure are evaluated based on the electromagnetic simulation using finite difference time domain (FDTD) method.

APA, Harvard, Vancouver, ISO, and other styles

37

Lederer, Dimitri, and Jean-Pierre Raskin. "On-wafer wideband characterization: a powerful tool for improving the IC technologies." Journal of Telecommunications and Information Technology, no. 2 (June 25, 2023): 69–77. http://dx.doi.org/10.26636/jtit.2007.2.811.

Full text

Abstract:

In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage – SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.

APA, Harvard, Vancouver, ISO, and other styles

38

Dovgiy, V. V., I. T. Kohut, and V. I. Golota. "Design and Simulation Elements of Analytical Microsystem-on-Chip With the Structures "Silicon-on-Insulator"." Фізика і хімія твердого тіла 17, no. 2 (June 15, 2016): 275–80. http://dx.doi.org/10.15330/pcss.17.2.275-280.

Full text

Abstract:

In this paper the results of architecture development, layout designof analytical microsystem-on-chip with the structures "silicon-on-insulator" (SOI) and its elements schemotechnical computer simulation for determine their electrical and time characteristics are presented.

APA, Harvard, Vancouver, ISO, and other styles

39

Hanim, Abdul Razak, Haroon Hazura, Bidin Mardiana, Shaari Sahbudin, and P. Susthitha Menon. "Analysis of Silicon-On-Insulator (SOI) Buried Waveguide Phase Modulator." Advanced Materials Research 462 (February 2012): 532–35. http://dx.doi.org/10.4028/www.scientific.net/amr.462.532.

Full text

Abstract:

The analyses of the simulation of a single mode buried waveguide optical phase modulator based on SOI material are here reported. The structure has been simulated by Athena from Silvaco simulation package. The buried waveguide is created by doping phosphorus with concentration of 10e15 cm-3 into the substrate. The real refractive index and the absorption coefficient of the waveguide are changed using the free carrier dispersion effect via carrier injection of a pn junction. The efficiency, VπLπ is calculated and the performance is compared with that of the rib waveguide optical phase modulator of the same material and dimensions. Simulation shows that the device can be an efficient device for application in intensity modulation.

APA, Harvard, Vancouver, ISO, and other styles

40

Su, L. T., J. B. Jacobs, J. Chung, and D. A. Antoniadis. "Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's." IEEE Electron Device Letters 15, no. 5 (May 1994): 183–85. http://dx.doi.org/10.1109/55.291592.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Su, L. T., J. B. Jacobs, J. E. Chung, and D. A. Antoniadis. "Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's." IEEE Electron Device Letters 15, no. 9 (September 1994): 366–69. http://dx.doi.org/10.1109/55.311136.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Oliveira, R. M. de, M. Dalponte, and H. Boudinov. "Electrical activation of arsenic implanted in silicon on insulator (SOI)." Journal of Physics D: Applied Physics 40, no. 17 (August 16, 2007): 5227–31. http://dx.doi.org/10.1088/0022-3727/40/17/032.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Saavedra, A. F., K. S. Jones, M. E. Law, and K. K. Chan. "Kinetics of {311} defect dissolution in silicon-on-insulator (SOI)." Materials Science and Engineering: B 107, no. 2 (March 2004): 198–203. http://dx.doi.org/10.1016/j.mseb.2003.11.004.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Patel, Dax, Soham Sojitra, Jay Kadia, Bhavik Chaudhary, and Rutu Parekh. "Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters." Trends in Sciences 19, no. 7 (March 14, 2022): 3216. http://dx.doi.org/10.48048/tis.2022.3216.

Full text

Abstract:

A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively. HIGHLIGHTS Comparative study of Double Gate and Silicon on Insulator MOSFET Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET Contour plot for electron concentration and potential GRAPHICAL ABSTRACT

APA, Harvard, Vancouver, ISO, and other styles

45

Tian, Zhuo, and Bai Cheng Li. "Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology." Applied Mechanics and Materials 687-691 (November 2014): 3251–54. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3251.

Full text

Abstract:

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

APA, Harvard, Vancouver, ISO, and other styles

46

Luo, Ying, Xuezhe Zheng, Guoliang Li, Ivan Shubin, Hiren Thacker, Jin Yao, Jin-Hyoung Lee, et al. "Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI)." Micromachines 3, no. 2 (April 26, 2012): 345–63. http://dx.doi.org/10.3390/mi3020345.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Mardiana, B., Sahbudin Shaari, P. S. Menon, A. R. Hanim, H. Hazura, N. Arsad, and H. Abdullah. "Various Sloped Wall Effect on Silicon on Insulator (SOI) Phase Modulator." Advanced Science Letters 19, no. 5 (May 1, 2013): 1438–40. http://dx.doi.org/10.1166/asl.2013.4493.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Cafra, B., A. Alberti, L. Ottaviano, C. Bongiorno, G. Mannino, T. Kammler, and T. Feudel. "Thermal stability of nickel silicide on silicon on insulator (SOI) material." Materials Science and Engineering: B 114-115 (December 2004): 228–31. http://dx.doi.org/10.1016/j.mseb.2004.07.020.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

McDaid, L. J., S. Hall, W. Eccleston, and J. C. Alderman. "Interpretation of capacitance-voltage characteristics on silicon-on-insulator (SOI) capacitors." Solid-State Electronics 32, no. 1 (January 1989): 65–68. http://dx.doi.org/10.1016/0038-1101(89)90049-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

CUI, JIANGWEI, XUEFENG YU, and DIYUAN REN. "RELATIONSHIP BETWEEN SILICON-ON-INSULATOR KINK AND RADIATION EFFECTS." International Journal of Modern Physics E 20, no. 06 (June 2011): 1409–17. http://dx.doi.org/10.1142/s0218301311018435.

Full text

Abstract:

Relationship between the kink and radiation effects of SOI MOSFET is investigated. The experiment results show that radiation exposure can play an important role on the behavior of the kink. The mechanisms of both the kink and radiation effects are clearly illustrated and the way the radiation affects the behavior of the kink are described in detail.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!