Journal articles: 'Silvaco ATLAS'

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Kløw, Frode, Erik S. Marstein, and Sean Erik Foss. "Tunneling Contact Passivation Simulations using Silvaco Atlas." Energy Procedia 77 (August 2015): 99–105. http://dx.doi.org/10.1016/j.egypro.2015.07.015.

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Taouririt, Taki Eddine, Afak Meftah, Nouredine Sengouga, Marwa Adaika, Slimane Chala, and Amjad Meftah. "Effects of high-k gate dielectrics on the electrical performance and reliability of an amorphous indium–tin–zinc–oxide thin film transistor (a-ITZO TFT): an analytical survey." Nanoscale 11, no. 48 (2019): 23459–74. http://dx.doi.org/10.1039/c9nr03395e.

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This study is a numerical simulation obtained by using Silvaco Atlas software to investigate the effect of different types of dielectric layers, inserted between the channel and the gate, on the performance and reliability of an a-ITZO TFT.

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Islam, Md Rabiul, Md Kamrul Hasan, Md Abdul Mannan, M. Tanseer Ali, and Md Rokib Hasan. "Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor." AIUB Journal of Science and Engineering (AJSE) 18, no. 2 (August 31, 2019): 73–80. http://dx.doi.org/10.53799/ajse.v18i2.43.

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We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

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Иванов, П. А., А. С. Потапов, and Т. П. Самсонова. "Моделирование переходных процессов в полупроводниковых приборах на основе 4H-SiC (учет неполной ионизации легирующих примесей в модуле ATLAS программного пакета SILVACO TCAD)." Физика и техника полупроводников 53, no. 3 (2019): 407. http://dx.doi.org/10.21883/ftp.2019.03.47295.9014.

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AbstractTransient process in a resistor–capacitor (RC) circuit with a reverse-biased 4 H -SiC p – n diode as the capacitive element is simulated. Simulation is performed with the ATLAS software module from the SILVACO TCAD system for technology computer-aided design (TCAD). An alternative way, to that in ATLAS, to set the parameters of doping impurities partly ionized in 4 H -SiC at room temperature is suggested. (The INCOMPLETE physical model available in the ATLAS module, which describes the incomplete ionization of doping impurities in semiconductors, is unsuitable for simulating the dynamic characteristics of devices.) The simulation results are discussed in relation to previously obtained experimental results.

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Cazarre, A., N. Nolhier, F. Morancho, P. Austin, and P. Calmon. "Initiation à la simulation bidimensionnelle Environnement SILVACO ( ATHENA - ATLAS)." J3eA 4 (2005): 003. http://dx.doi.org/10.1051/j3ea:200515.

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Munir, Tarriq, Azlan Abdul Aziz, Mat Johar Abdullah, and Mohd Fadzil Ain. "Temperature Dependent DC and RF Performance of n-GaN Schottky Diode: A Numerical Approach." Advanced Materials Research 895 (February 2014): 439–43. http://dx.doi.org/10.4028/www.scientific.net/amr.895.439.

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This paper reports the temperature dependent DC and RF characteristics of n-GaN Schottky diode simulated using Atlas/Blaze developed by Silvaco. It was found that as the temperature increases from 300K to 900K the forward current decreases due to lowering of the Schottky barrier with an increase in series-resistance and ideality factor. These observations indicates that tunneling behavior dominates the current flow rather than thermionic emission. Furthermore, the breakdown voltage decreases in reverse bias and insertion loss for RF behavior increases with respect to temperature due to the increase in capacitance near diode junction.Keywords: Atlas/Blaze, Schottky barrier, series resistance, ideality factor, insertion loss.

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Boukortt, N., S. Patanè, and B. Hadri. "Development of High-Efficiency PERC Solar Cells Using Atlas Silvaco." Silicon 11, no. 1 (May 21, 2018): 145–52. http://dx.doi.org/10.1007/s12633-018-9838-8.

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Rolland, Gwen, Christophe Rodriguez, Guillaume Gommé, Abderrahim Boucherif, Ahmed Chakroun, Meriem Bouchilaoun, Marie Clara Pepin, et al. "High Power Normally-OFF GaN/AlGaN HEMT with Regrown p Type GaN." Energies 14, no. 19 (September 24, 2021): 6098. http://dx.doi.org/10.3390/en14196098.

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In this paper is presented a Normally-OFF GaN HEMT (High Electron Mobility Transistor) device using p-doped GaN barrier layer regrown by CBE (Chemical Beam Epitaxy). The impact of the p doping on the device performance is investigated using TCAD simulator (Silvaco/Atlas). With 4E17 cm−3 p doping, a Vth of 1.5 V is achieved. Four terminal breakdowns of the fabricated device are investigated, and the origin of the device failure is identified.

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DWIVEDI, A. D. D., and POOJA KUMARI. "TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs." Surface Review and Letters 27, no. 05 (August 23, 2019): 1950145. http://dx.doi.org/10.1142/s0218625x19501452.

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This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

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Dubey, Sarvesh, and Rahul Mishra. "Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 9, no. 01 (June 25, 2017): 67–72. http://dx.doi.org/10.18090/samriddhi.v9i01.8340.

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The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

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Kang, J., X. He, D. Vasileska, and D. K. Schroder. "Optimization of FIBMOS Through 2D Silvaco ATLAS and 2D Monte Carlo Particle-based Device Simulations." VLSI Design 13, no. 1-4 (January 1, 2001): 251–56. http://dx.doi.org/10.1155/2001/45747.

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Focused Ion Beam MOSFETs (FIBMOS) demonstrate large enhancements in core device performance areas such as output resistance, hot electron reliability and voltage stability upon channel length or drain voltage variation. In this work, we describe an optimization technique for FIBMOS threshold voltage characterization using the 2D Silvaco ATLAS simulator. Both ATLAS and 2D Monte Carlo particle-based simulations were used to show that FIBMOS devices exhibit enhanced current drive capabilities when compared to normal MOSFETs. It was also found that the device performance is very much dependent upon the FIB implant profile. High and narrow doping of the FIB implant leads to high drain current and low hot carrier reliability, whereas low and wide doping gives rise to lower drain current and higher hot carrier reliability.

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Mehrabian, Masood, and Sina Dalir. "11.73% efficient perovskite heterojunction solar cell simulated by SILVACO ATLAS software." Optik 139 (June 2017): 44–47. http://dx.doi.org/10.1016/j.ijleo.2017.03.077.

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Sharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj, and Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET." Journal of Nanoelectronics and Optoelectronics 13, no. 10 (October 1, 2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.

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In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

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Tobbeche, S., and M. N. Kateb. "Two-Dimensional Modelling and Simulation of Crystalline Silicon n⁺pp⁺ Solar Cell." Applied Mechanics and Materials 260-261 (December 2012): 154–62. http://dx.doi.org/10.4028/www.scientific.net/amm.260-261.154.

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In this work, we present the simulation results of the technological parameters and the electrical characteristics of a crystalline silicon n+pp+ solar cell, using two-dimension (2D) software, namely TCAD Silvaco (Technology Computer Aided Design). TCAD Silvaco Athena is used to simulate various stages of the technology manufacturing, while TCAD Silvaco Atlas is used for the simulation of the electrical characteristics and the spectral response of the solar cell. The J-V characteristics and the external quantum efficiency (EQE) are simulated under AM 1.5 illumination. The conversion efficiency(η)of 16.06% is reached and the other characteristic parameters are simulated: the open circuit voltage (Voc) is of 0.63 V, the short circuit current density (Jsc) equals 30.54 mA/cm² and the form factor (FF) is of 0.83 for the n+pp+ solar cell with a silicon nitride antireflection layer (Si3N4). In order to highlight the importance of the back surface field (BSF), a comparison between two cells, one without BSF (structure n+p), the other with one BSF (structure n+pp+), was made. By creating a BSF on the rear face of the cell the short circuit current density increases from 28.55 to 30.54 mA/cm2, the open circuit voltage from 0.6 to 0.63 V and the conversion efficiency from 14.19 to 16.06%. A clear improvement of the spectral response is obtained in wavelengths ranging from 0.65 to 1.1 µm for the solar cell with BSF.

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PICOS, R., E. GARCIA, M. ESTRADA, A. CERDEIRA, and B. IÑIGUEZ. "EFFECT OF PROCESS VARIATIONS ON AN OTFT COMPACT MODEL PARAMETERS." International Journal of High Speed Electronics and Systems 20, no. 04 (December 2011): 815–28. http://dx.doi.org/10.1142/s0129156411007070.

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We have studied the effect of some of the possible deviations on the values of the extracted parameters of a specific OTFT model, considering OTFTs designed using P 3 HT as semiconductor layer, PMMA as insulator, bottom gate, and top gold contacts. Specifically, we have studied the influence of misposition or misalignment of the masks, the effect of imperfections of etching, and the effect of variations on the layer deposition process. These effects have been simulated using the Silvaco Athena software, and they have been modeled as horizontal shifts of the etching windows and variations of the layers thickness. Once the devices were defined, they were simulated using Silvaco Atlas, and parameter extraction was performed using a specifically developed algorithm. We have found a strong correlation among some of the physical parameters and the model parameters that may offer useful insight for process optimization. Moreover, strong correlations have been found also among the model parameters. We have used these results to develop a Monte Carlo model, suitable for statistical circuit simulation.

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Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

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In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

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Mohd Said, Muzalifah, Zul Atfyi Fauzan, and Nur Fatihah Azmi. "NMOS Low Boron Activation in Pre-Amorphise Silicon." Advanced Materials Research 875-877 (February 2014): 734–38. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.734.

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The high demand of smaller and compact size of MOSFETs has leads to desirable for ultra shallow junction formation with low sheet resistance and good electrical performances. These two characteristics are required to suppress short channel effects and to increase the efficiency of device. In this paper, Pre-amorphise implantation (PAI) PMOS with different doses of Boron and the basic PMOS structure are done by using ATHENA and the performance of devices is compared by using ATLAS software package from Silvaco TCAD. Comparison done in electrical characteristic, I-V curve Ion and Ioff has showed PMOS with PAI technology with low boron doses resulted in increasing electrical performance characteristic.

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Abd Rahim, Alhan Farhanah, N. M. Sah, I. H. Hamzah, Siti Noraini Sulaiman, and Musa Mohamed Zahidi. "Study on the Effect of Porous Silicon Sizes for Potential Visible Photodetector." Applied Mechanics and Materials 815 (November 2015): 121–30. http://dx.doi.org/10.4028/www.scientific.net/amm.815.121.

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In this work, the characterization of porous silicon (PS) for potential visible light emission was investigated by simulation. SILVACO TCAD simulator was used to simulate PS by using process simulator, ATHENA and device simulator, ATLAS. Different pore diameter sizes of the PS structures were constructed. The structural, optical and electrical characteristics of the structures PS were investigated by current-voltage (I-V), current gain, spectral response and the energy band gap. It was observed that PS enhances the current gain compare to bulk Si and exhibited photo emission in the visible spectrum which constitutes to the quantum confinement effect of the Si in the PS structures.

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Sadoun, Ali. "Extraction of the electrical parameters of the Au/InSb/InP Schottky diode in the temperature range (300 K- 425 K)." International Journal of Energetica 5, no. 1 (July 6, 2020): 30. http://dx.doi.org/10.47238/ijeca.v5i1.120.

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In this work, we have presented a theoretical study of Au/InSb/InP Schottky diode based on current-voltage (I-V) measurement in the temperature range ( 300 K- 425 K). Electrical parameters of Au/InSb/InP such as barrier height (Φb), ideality factor and series resistance have been calculated by employing the conventional (I-V), Norde, Cheung and Chattopadhyay methods. Measurements show that the Schottky barrier height (SBH), ideality factor and series resistance, RS for Au/InSb/InP Schottky diode in the temperature range (300 K–425 K) are 0.602-0.69eV, 1.683-1.234 and 84.54-18.95 (Ω), respectively. These parameters were extracted using Atlas-Silvaco-Tcad logical.

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Jaafar, Hind, Abdellah Aouaj, Ahmed Bouziane, and Benjamin Iñiguez. "An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET." Nanoscience &Nanotechnology-Asia 9, no. 2 (June 25, 2019): 291–97. http://dx.doi.org/10.2174/2210681208666180813122145.

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Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

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Smaani, Billel, Mourad Bella, and Saϊda Latreche. "Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor." Applied Mechanics and Materials 492 (January 2014): 306–10. http://dx.doi.org/10.4028/www.scientific.net/amm.492.306.

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In this paper, a compact modeling of lightly doped nanoscale Double Gate (DG) MOSFET transistor is presented. In the first time, a DG MOSFET transistor with long channel is considered. In this case, by using 1-D Poissons equation and applying the Gauss law at the interface of Silicone/Oxide, the static behavior of the long channel DG MOSFET can be observed by simple relationships between charges-voltages and charges-drain current. In second time, the dynamic behavior of the device is described through the intrinsic trans-capacitances. The present results (obtained using MATLAB) are validated by comparing them with those obtained using commercial software (Silvaco Atlas-TCAD).

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Takata, Masashi, Kenichiro Takagi, Takashi Nagase, Takashi Kobayashi, and Hiroyoshi Naito. "Effects of Bimolecular Recombination on Impedance Spectra in Organic Semiconductors: Analytical Approach." Journal of Nanoscience and Nanotechnology 16, no. 4 (April 1, 2016): 3322–26. http://dx.doi.org/10.1166/jnn.2016.12289.

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An analytical expression for impedance spectra in the case of double injection (both electrons and holes are injected into an organic semiconductor thin film) has been derived from the basic transport equations (the current density equation, the continuity equation and the Possion’s equation). Capacitance-frequency characteristics calculated from the analytical expression have been examined at different recombination constants and different values of mobility balance defined by a ratio of electron mobility to hole mobility. Negative capacitance appears when the recombination constant is lower than the Langevin recombination constant and when the value of the mobility balance approaches unity. These results are consistent with the numerical results obtained by a device simulator (Atlas, Silvaco).

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Nadimi, M., and A. Sadr. "Computer Modeling of MWIR Homojunction Photodetector Based on Indium Antimonide." Advanced Materials Research 383-390 (November 2011): 6806–10. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.6806.

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High operating temperatures infrared photodetectors are needed for improving the performance of existing military and civilian infrared systems. To obtain high device performance at higher temperatures, the thermally generated noise required to be reduced. Minority-carrier extraction and exclusion techniques are the approaches for decreasing the thermal noise of infrared systems. In the present work, an InSb extraction diode was studied and simulated for operation in the MWIR region. The simulation was performed using ATLAS device simulator from SILVACO®. The energy band diagram, doping profile, electric field profile, dark current and spectral response were calculated as a function of device thickness, applied reverse voltage and operating wavelength. The simulated photodetector exhibited a zero bias resistance-area product, R0A = 1.6×〖10〗^(-3) Ω〖.cm〗^2 at 240K.

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Mao, Hong-kai, Ying Wang, Xue Wu, and Fang-wen Su. "Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss." Micromachines 10, no. 12 (November 26, 2019): 815. http://dx.doi.org/10.3390/mi10120815.

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In this work, an insulated gate bipolar transistor (IGBT) is proposed that introduces a portion of the p-polySi/p-SiC heterojunction on the collector side to reduce the tail current during device turn-offs. By adjusting the doping concentration on both sides of the heterojunction, the turn-off loss is further reduced without sacrificing other characteristics of the device. The electrical characteristics of the device were simulated through the Silvaco ATLAS 2D simulation tool and compared with the traditional structure to verify the design idea. The simulation results show that, compared with the traditional structure, the turn-off loss of the proposed structure was reduced by 58.4%, the breakdown voltage increased by 13.3%, and the forward characteristics sacrificed 8.3%.

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Liu, Yanli, Dunjun Chen, Kexiu Dong, Hai Lu, Rong Zhang, Youdou Zheng, Zhilin Zhu, Guangfen Wei, and Zhonghai Lin. "Temperature Dependence of the Energy Band Diagram of AlGaN/GaN Heterostructure." Advances in Condensed Matter Physics 2018 (2018): 1–4. http://dx.doi.org/10.1155/2018/1592689.

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Temperature dependence of the energy band diagram of AlGaN/GaN heterostructure was investigated by theoretical calculation and experiment. Through solving Schrodinger and Poisson equations self-consistently by using the Silvaco Atlas software, the energy band diagram with varying temperature was calculated. The results indicate that the conduction band offset of AlGaN/GaN heterostructure decreases with increasing temperature in the range of 7 K to 200 K, which means that the depth of quantum well at AlGaN/GaN interface becomes shallower and the confinement of that on two-dimensional electron gas reduces. The theoretical calculation results are verified by the investigation of temperature dependent photoluminescence of AlGaN/GaN heterostructure. This work provides important theoretical and experimental basis for the performance degradation of AlGaN/GaN HEMT with increasing temperature.

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Chawla, Rashmi, Poonam Singhal, and Amit Kumar Garg. "Design and Analysis of Multi Junction Solar Photovoltaic Cell with Graphene as an Intermediate Layer." Journal of Nanoscience and Nanotechnology 20, no. 6 (June 1, 2020): 3693–702. http://dx.doi.org/10.1166/jnn.2020.17512.

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An efficacious Intermediate Layer (IML) is important for multi junction solar Photo Voltaic Cell (PVC) owing to its good electrical conductivity and optical transparency. In this research work, the use of Graphene as an IML with varied thickness on InGaP/GaAs/InGaAs multi-junction solar PVCs is investigated using virtual fabrication TCAD tool SILVACO-Atlas. The detail absorption rate from wavelength 300 nm (ultraviolet)-2500 nm (middle infra-red region) is determined and the effected modelling stages are recounted. The results after simulation are further confirmed with experimental data to prove accuracy of the research work proposed. The performance parameters with Jsc = 33.4 mA/cm2, Voc = 1.27 V, fill factor (FF) = 99.5% and conversion efficiency of 30.91% (1 sun) are obtained under AM1.5G illumination.

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Mehrabian, Masood, Sina Dalir, and Hossein Shokrvash. "Numerical simulation of CdS quantum dot sensitized solar cell using the Silvaco-Atlas software." Optik 127, no. 20 (October 2016): 10096–101. http://dx.doi.org/10.1016/j.ijleo.2016.08.016.

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Joseph Mebelson, T., and K. Elampari. "A study of electrical and optical characteristics of CZTSe solar cell using Silvaco Atlas." Materials Today: Proceedings 46 (2021): 2540–43. http://dx.doi.org/10.1016/j.matpr.2021.01.758.

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Hazdra, Pavel, Stanislav Popelka, and Adolf Schöner. "Local Lifetime Control in 4H-SiC by Proton Irradiation." Materials Science Forum 924 (June 2018): 436–39. http://dx.doi.org/10.4028/www.scientific.net/msf.924.436.

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The effect of local lifetime control by proton irradiation on the OCVD response of a 10 kV SiC PiN diode was investigated. Carrier lifetime was reduced locally by irradiation with 800 keV protons at fluences up to 1x1011cm-2. Radiation defects were characterized by DLTS and C-V profiling; excess carrier dynamics were measured by the OCVD and analyzed using the calibrated device simulator ATLAS from Silvaco, Inc. Results show that proton implantation followed by low temperature annealing can be used for controllable local lifetime reduction in SiC devices. The dominant recombination centre is the Z1/2defect, whose distribution can be set by irradiation energy and fluence. The local lifetime reduction, which improves diode recovery, can be monitored by OCVD response and simulated using the SRH model accounting for the Z1/2defect.

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Michael, Sherif, and Andrew Bates. "The design and optimization of advanced multijunction solar cells using the Silvaco ATLAS software package." Solar Energy Materials and Solar Cells 87, no. 1-4 (May 2005): 785–94. http://dx.doi.org/10.1016/j.solmat.2004.07.051.

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Hazdra, Pavel, and Stanislav Popelka. "Lifetime Control in SiC PiN Diodes Using Radiation Defects." Materials Science Forum 897 (May 2017): 463–66. http://dx.doi.org/10.4028/www.scientific.net/msf.897.463.

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Application of radiation defects for lifetime control in contemporary SiC PiN diodes was investigated using the calibrated device simulator ATLAS from Silvaco, Inc. Recombination models accounting for the effect of deep levels introduced by the irradiation were set according to experimental results obtained by C-V and DLTS measurements performed on low-doped n-type SiC epilayers irradiated with 4.5 MeV electrons and 670 keV protons. Global (4.5 MeV electron irradiation) and local (700 keV proton irradiation) lifetime reduction was then applied on the 2A/10kV SiC PiN diode and the ON-state and reverse recovery characteristics were simulated and compared. Results show that the proton irradiation can substantially improve the trade‑off between the diode ON‑state and turn‑OFF losses. Compared to the electron irradiation, the local lifetime killing by protons allows achieving better trade-off and softer recovery curves.

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Chander, Subhash, Partap Singh, Samuder Gupta, D. S. Rawal, and Mridula Gupta. "Self heating Effects in GaN High Electron Mobility Transistor for Different Passivation Material." Defence Science Journal 70, no. 5 (October 8, 2020): 511–14. http://dx.doi.org/10.14429/dsj.70.16360.

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In this paper effect of self-heating has been studied of AlGaN/GaN high electron mobility transistor (HEMT) for different passivation layers which is promising device for high power at high frequencies. The different passivation layers used are aluminium oxide (Al2O3), silicon nitride (SiN) and silicon dioxide (SiO2). The device GaN HEMT has been simulated and characterised for its thermal behaviour by the distribution of lattice temperature inside the device using device simulation tool ATLAS from SILVACO. The transfer and output characteristics with and without self-heating has been studied for electrical characterisation. The channel temperature for different passivation observed is 448 K, 456 K and 471 K forAl2O3, SiN and SiO2 respectively. The observed different temperatures are due to difference in their thermal conductivity. This channel temperature information is critical to study the reliability of the device at high power levels.

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Das, Banasree, and Manas Kumar Parai. "Influence on Characteristics of RTD Due to Variation of Different Parameters and Material Properties." International Journal of High Speed Electronics and Systems 26, no. 04 (December 2017): 1740022. http://dx.doi.org/10.1142/s0129156417400225.

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In this paper, novel features offered by Resonant Tunneling Diode (RTD) are reviewed by simulating it under different conditions. GaAs/AlGaAs based RTD is used as the reference one to obtain the characteristics due to parametric variations. To fulfil this purpose a simple model of resonant electronic transport through a double-barrier structure is developed. I-V characteristics are studied by varying barrier parameters and well width. Different peak and valley currents are measured under these conditions. For the same set of parameters both symmetric and asymmetric cases are considered. Different materials of lower effective mass are also taken into consideration to improve Peak to Valley Ratio (PVR). The Indium (In) based materials are considered to compare the characteristics obtained from the conventional GaAs based RTD structure. All these proposed structures are simulated using Silvaco Atlas software.

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Tayoub, Hadjira, Baya Zebentouta, and Zineb Benamara. "TCAD Simulation of the Electrical Characteristics of Polycrystalline Silicon Thin Film Transistor." Pakistan Journal of Scientific & Industrial Research Series A: Physical Sciences 63, no. 2 (July 15, 2020): 89–93. http://dx.doi.org/10.52763/pjsir.phys.sci.63.2.2020.89.93.

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Low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied because of their high performance in Active Matrix Liquid Crystal Displays (AMLCD's) and Active Matrix Organic Light-Emitting Diode (AMOLED) applications. The purpose of this work is to simulate the impact of varying the electrical and physical parameters (the interface states, active layer's thickness and BBT model) in the transfer characteristics of poly-Si TFT to extract the electrical parameters like the threshold voltage, the mobility and to evaluate the device performance. The device was simulated using ATLAS software from Silvaco, the results show that the electrical and physical parameters of poly-Si TFT affect significantly its transfer characteristics, choosing suitable parameters improve high-performance transistor. Such results make the designed structure a promising element for large-scale electronics applications.

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Drăgan, Florin, Ørnulf Nordseth, Laurențiu Fara, Constantin Dumitru, Dan Crăciunescu, Vlad Muscurel, and Paul Sterian. "Optical Modeling and Simulation of Tandem Metal Oxide Solar Cells." Annals of West University of Timisoara - Physics 60, no. 1 (August 1, 2018): 56–66. http://dx.doi.org/10.2478/awutp-2018-0006.

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AbstractAn investigation of silicon-based tandem solar cells incorporating Al-doped ZnO (AZO) and Cu2O metal oxides, via two of the most efficient methods of optical modeling, specifically ray tracing and transfer matrix algorithms, was performed. The simulations were conducted based on specialized software, namely Silvaco Atlas and MATLAB, as well as on OPAL2 simulation platform. The optical analysis involved the calculation of the spectral curves for reflectance, absorptance and transmittance for different thicknesses of the thin film layers constituting the cell. It was established the optimum thickness of the AZO layer based on the minimum reflectance and maximum transmittance. Moreover, several materials were investigated in order to determine the optimum buffer layer for the tandem solar cell, based on optical modeling. The optical parameters of the ZnO/Cu2O top subcell were optimized, in order to achieve the highest conversion efficiency of such heterojunction solar cell.

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Attari, Kamal, Lahcen Amhaimar, Ali El yaakoubi, Adel Asselman, and Mounir Bassou. "The Design and Optimization of GaAs Single Solar Cells Using the Genetic Algorithm and Silvaco ATLAS." International Journal of Photoenergy 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/8269358.

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Single-junction solar cells are the most available in the market and the most simple in terms of the realization and fabrication comparing to the other solar devices. However, these single-junction solar cells need more development and optimization for higher conversion efficiency. In addition to the doping densities and compromises between different layers and their best thickness value, the choice of the materials is also an important factor on improving the efficiency. In this paper, an efficient single-junction solar cell model of GaAs is presented and optimized. In the first step, an initial model was simulated and then the results were processed by an algorithm code. In this work, the proposed optimization method is a genetic search algorithm implemented in Matlab receiving ATLAS data to generate an optimum output power solar cell. Other performance parameters such as photogeneration rates, external quantum efficiency (EQE), and internal quantum efficiency (EQI) are also obtained. The simulation shows that the proposed method provides significant conversion efficiency improvement of 29.7% under AM1.5G illumination. The other results were Jsc = 34.79 mA/cm2, Voc = 1 V, and fill factor (FF) = 85%.

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Duan, Xiaoling, Jincheng Zhang, Jiabo Chen, Tao Zhang, Jiaduo Zhu, Zhiyu Lin, and Yue Hao. "High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor." Micromachines 10, no. 1 (January 21, 2019): 75. http://dx.doi.org/10.3390/mi10010075.

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A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

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Manoua, Mohamed, Tariq Jannane, Otmane Abouelala, Nejma Fazouan, Abdelmajid Almaggoussi, Najoua Kamoun, and Ahmed Liba. "Modeling and optimization of n-ZnO/p-Si heterojunction using 2-dimensional numerical simulation." European Physical Journal Applied Physics 90, no. 1 (April 2020): 10101. http://dx.doi.org/10.1051/epjap/2020190333.

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In this work, n-ZnO/p-Si heterojunction was investigated using two-dimensional numerical simulation. The effect of Zinc Oxide thickness, carrier concentration in Zinc Oxide layer, minority carrier lifetime of bulk Silicon and the interface states density on electrical properties were studied in dark and under illumination conditions. This study aimed to optimize these parameters in order to obtain n-ZnO/p-Si solar cell with high conversion efficiency and low cost. The simulation was carried out by Atlas silvaco software. As results, a very low saturation current Is, low series resistance Rs, an ideality factor n between 1 and 1.5 were obtained for optimal charge carrier concentrations in the range [5 × 1019–5 × 1021 cm−3] and a thickness of Zinc Oxide between 0.6 and 2 µm. Moreover, a photovoltaic conversion efficiency of 24.75% was achieved without interfacial defect, which decreases to 5.49% for an interface defect density of 5 × 1014 cm−2.

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Sahoo, G. S., and G. P. Mishra. "Design and modeling of an SJ infrared solar cell approaching upper limit of theoretical efficiency." International Journal of Modern Physics B 32, no. 02 (January 16, 2018): 1850014. http://dx.doi.org/10.1142/s0217979218500145.

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Recent trends of photovoltaics account for the conversion efficiency limit making them more cost effective. To achieve this we have to leave the golden era of silicon cell and make a path towards III–V compound semiconductor groups to take advantages like bandgap engineering by alloying these compounds. In this work we have used a low bandgap GaSb material and designed a single junction (SJ) cell with a conversion efficiency of 32.98%. SILVACO ATLAS TCAD simulator has been used to simulate the proposed model using both Ray Tracing and Transfer Matrix Method (under 1 sun and 1000 sun of AM1.5G spectrum). A detailed analyses of photogeneration rate, spectral response, potential developed, external quantum efficiency (EQE), internal quantum efficiency (IQE), short-circuit current density (J[Formula: see text]), open-circuit voltage (V[Formula: see text]), fill factor (FF) and conversion efficiency ([Formula: see text]) are discussed. The obtained results are compared with previously reported SJ solar cell reports.

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Jaafar, Hind, Abdellah Aouaj, and Benjamin Iñiguez. "A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (March 1, 2020): 34. http://dx.doi.org/10.11591/ijres.v9.i1.pp34-41.

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A compact model for dual-material gate graded-channel and dual-oxide thickness with two dielectric constant different cylindrical gate (DMG-GC- DOTTDCD) MOSFET was investigated in terms of transconductance, drain conductance and capacitance. Short channel effects are modeled with simple expressions, and incorporated into the core of the model (at the drain current). The design effectiveness of DMG-GC-DOTTDCD was monitored in comparing with the DMG-GC-DOT transistor, the effect of variations of technology parameters, was presented in terms of gate polarization and drain polarization. The results indicate that the DMG-GC-DOTTDCD devices have characteristics higher than the DMG-GC-DOT MOSFET. To validate the proposed model, we used the results obtained from the simulation of the device with the SILVACO-ATLAS-TCAD software.

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Sara, Bechlaghem, Zebentout Baya, and Benamara Zineb. "Investigation of Cu(In, Ga)Se2 solar cell performance with non-cadmium buffer layer using TCAD-SILVACO." Materials Science-Poland 36, no. 3 (September 1, 2018): 514–19. http://dx.doi.org/10.2478/msp-2018-0054.

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AbstractThe purpose of this work is to achieve the best efficiency of Cu(In, Ga)Se2 solar cells by replacing the CdS buffer layer with other nontoxic materials. The simulation tool used in this study is Silvaco-Atlas package based on digital resolution 2D transport equations governing the conduction mechanisms in semiconductor devices. The J-V characteristics are simulated under AM1.5G illumination. Firstly, we will report the modeling and simulation results of CdS/CIGS solar cell, in comparison with the previously reported experimental results [1]. Secondly, the photovoltaic parameters will be calculated with CdS buffer layer and without any buffer layer to understand its impact on the output parameters of solar cells. The simulation is carried out with the use of electrical and optical parameters chosen judiciously for different buffers (CdS, ZnOS and ZnSe). In comparison to simulated CdS/CIGS, the best photovoltaic parameters have been obtained with ZnOS buffer layer. The structure has almost the same open circuit voltage Voc and fill factor FF, and higher short circuit current density Jsc, which results in slightly higher conversion efficiencies.

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Jankovic, Nebojsa. "Numerical simulations of N-type CdSe poly-TFT electrical characteristics with trap density models of Atlas/Silvaco." Microelectronics Reliability 52, no. 11 (November 2012): 2537–41. http://dx.doi.org/10.1016/j.microrel.2012.03.031.

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Elbar, M., and S. Tobbeche. "Numerical Simulation of CGS/CIGS Single and Tandem Thin-film Solar Cells using the Silvaco-Atlas Software." Energy Procedia 74 (August 2015): 1220–27. http://dx.doi.org/10.1016/j.egypro.2015.07.766.

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Linares Aranda, Mónico, W. Calleja Arriaga, A. Torres Jacome, and C. R. Báez Álvarez. "A modular and generic monolithic integrated MEMS fabrication process." Superficies y Vacío 30, no. 3 (November 26, 2017): 30–39. http://dx.doi.org/10.47566/2017_syv30_1-030030.

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A modular and generic, monolithic integrated MEMS fabrication process is presented to integrate microelectronics (CMOS) with mechanical microstructures (MEMS). The proposed monolithic integrated fabrication process is designed using an intra-CMOS approach (to fabricate the mechanical microstructures into trenches without the need of planarization techniques) and a CMOS module (to fabricate the electronic devices) with a 3 ?m length as minimum feature. The microstructures module is made up to three polysilicon layers, and aluminum as electrical interconnecting material. From simulation results, using the SILVACO® suite (Athena and Atlas frameworks), no significant degradation on the CMOS performance devices was observed after MEMS manufacturing stage; however, the thermal budget of the modules plays a crucial role, because it set the conditions for obtaining the complete set of devices fabricated near their optimal point. Finally, to evaluate and to support the development of the proposed integrated MEMS process, a modular test chip that includes electrical test structures, mechanical test structures, interconnection reliability test structures and functional micro-actuators, was also designed.

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Taberkit, Amine Mohammed, Ahlam Guen-Bouazza, and Benyounes Bouazza. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (February 1, 2018): 421. http://dx.doi.org/10.11591/ijece.v8i1.pp421-428.

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The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

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Ziko, Mehadi Hasan, Ants Koel, Toomas Rang, and Jana Toompuu. "Analysis of Barrier Inhomogeneities of P-Type Al/4H-SiC Schottky Barrier Diodes." Materials Science Forum 1004 (July 2020): 960–72. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.960.

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The diffusion welding (DW), known as direct bonding technique could be more used as an alternative approach to develop silicon carbide (SiC) Schottky rectifiers to existing mainstream metallization contact technologies. Measured results for p-type 4H-SiC Schottky barrier diodes (SBD) arepresented. And comprehensive numerical study to characterize the device has been performed. The simulations are carried out with ATLAS software (Silvaco). The measured and numerically simulated forward current-voltage (I–V) and capacitance-voltage (C–V) characteristics in a large temperaturerange are analyzed. Some of the measured p-type 4H-SiC Schottky diodes show deviation in specific ranges of their electrical characteristics. This deviation, especially due to excess current, dominates at low voltages (less than 1 V) and temperatures (less than room temperature). To verify the existence of electrically active defects under the Schottky contact, which influences the Schottky barrier height (SBH) and its inhomogeneity, the deep level transient spectroscopy (DLTS) technology was applied. DLTS measurements show the presence of a deep-level defect with activation energy corresponding typically for multilevel trap clusters.

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Thakur, Rajiv Ranjan, and Nidhi Chaturvedi. "Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications." Nano 16, no. 08 (July 2021): 2150096. http://dx.doi.org/10.1142/s179329202150096x.

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In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text] tuning using metal contact length ([Formula: see text], (ii) threshold voltage ([Formula: see text] tuning using metal electrode work functions ([Formula: see text] and (iii) threshold voltage ([Formula: see text] tuning using metal contact width ([Formula: see text]. The device has an [Formula: see text]/[Formula: see text] ratio of 105, suppressed off-state leakage in the range of 10[Formula: see text]–10[Formula: see text]A. The simulation work has been carried out on a commercially available ATLAS device simulator from Silvaco.

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Boukortt, Nour El Islam, Baghdad Hadri, Alina Caddemi, Giovanni Crupi, and Salvatore Patane. "3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO." Transactions on Electrical and Electronic Materials 16, no. 3 (June 25, 2015): 156–61. http://dx.doi.org/10.4313/teem.2015.16.3.156.

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Michael, Sherif. "A novel approach for the modeling of advanced photovoltaic devices using the SILVACO/ATLAS virtual wafer fabrication tools." Solar Energy Materials and Solar Cells 87, no. 1-4 (May 2005): 771–84. http://dx.doi.org/10.1016/j.solmat.2004.07.050.

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Swain, Sanjit K., Sudhansu M. Biswal, Satish K. Das, Sarosij Adak, and Biswajit Baral. "Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 419–24. http://dx.doi.org/10.2174/2210681209666190919094434.

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Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result:: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer. Conclusion:: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.

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Journal articles on the topic 'Silvaco ATLAS'

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