Journal articles: 'Silvaco TCAD tool'

1

Akansha, Ephraim* Neelesh Agrawal Anil Kumar A.K. Jaiswal. "STUDY OF ELECTRICAL CHARACTERISTIC OF NEW P-TYPE TRENCHED UMOSFET." Global Journal of Engineering Science and Research Management 4, no. 8 (2017): 20–25. https://doi.org/10.5281/zenodo.841194.

Full text

Abstract:

In this paper p-type trenched UMOSFET was designed without super junction and constructed like any other conventional MOSFET. Characteristic curve was studied between drain current verses drain voltage and drain current verses gate voltage. The trench was designed under TCAD simulation tool Silvaco software using etching process. The specific channel length of the p-type UMOSFET has been concentrated as 0.9 microns. The device structures are designed using Silvaco Athena and characteristics were examined using Silvaco Atlas.

APA, Harvard, Vancouver, ISO, and other styles

2

KUMARI, RITI, MANISH GOSWAMI, and B. R. SINGH. "THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs." International Journal of Nanoscience 11, no. 02 (2012): 1250021. http://dx.doi.org/10.1142/s0219581x12500214.

Full text

Abstract:

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.

APA, Harvard, Vancouver, ISO, and other styles

3

Chowdhury, Md. Iqbal Bahar. "Investigation of an InGaN Based Quantum Well Solar Cell Using Silvaco TCAD." Journal of Advance Electrical Engineering and Devices 2, no. 2 (2024): 30–41. https://doi.org/10.5281/zenodo.15307137.

Full text

Abstract:

This work aims to investigate a Quantum Well Solar Cell (QWSC) that employs the same alloy material for all the layers of the solar cell structure. Silvaco TCAD software tool is used to implement the desired QWSC, where the same III-V group-based Indium Gallium Nitride (InGaN) alloy has been proposed as the material for its different layers, because of its ability to have a widely varying band-gap due to varying compositions. The same alloy with different combinations provides a band gap appropriate for each layer while reducing lattice-mismatch between the layers to the minimum, thereby helping achieve high conversion efficiency. The same InGaN material is used as the Quantum Wells (QWs) embedded in the intrinsic InGaN-based absorber layer. This absorber layer is sandwiched between the heavily doped base and emitter regions to provide a uniform field to help escape all the photogenerated carriers from the QWs. Extensive simulation runs have been conducted in the Silvaco TCAD environment to investigate the effects of number, width and depth of these QWs on the various performance metrics of the proposed QWSC, which include short circuit current density, open circuit voltage, fill factor and conversion efficiency. The role of the Back-Surface Field (BSF) layer on these performance metrics has also been investigated. The performance metrics of the proposed QWSC are also compared with those of a GaAs/InAs-based QWSC implemented in Silvaco with a similar structure and state-of-the-art QWSCs mentioned in the literature. These investigations reveal that the proposed QWSC is promising for realizing a high-efficiency solar cell. 

APA, Harvard, Vancouver, ISO, and other styles

4

Sharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj, and Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET." Journal of Nanoelectronics and Optoelectronics 13, no. 10 (2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.

Full text

Abstract:

In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

APA, Harvard, Vancouver, ISO, and other styles

5

Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

Full text

Abstract:

In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

APA, Harvard, Vancouver, ISO, and other styles

6

Sanjay, Sharma, Yadav R.P., and Janyani Vijay. "Substrate Current Evaluation for Lightly and Heavily Doped MOSFETs at 45 nm process Using Physical Models." Bulletin of Electrical Engineering and Informatics 5, no. 1 (2016): 120–25. https://doi.org/10.11591/eei.v5i1.556.

Full text

Abstract:

Substrate noise is a major integration issue in mixed signal circuits; particularly at radio frequency (RF) it becomes a key issue. In deep sub micron MOSFETs hot carrier effect induces device degradation. The impact ionization phenomenon is one of the main hot carrier effects. The paper covers the process and device level simulation of MOSFETs by TCAD and the substrate current comparison in lightly and heavily doped MOS. PMOS and NMOS devices are virtually fabricated with the help of ATHENA process simulator. The modeled devices include the hot carrier effects. The MOS devices are implemented on lightly and heavily doped substrates and substrate current is evaluated and compared with the help of ATLAS device simulator. Substrate current is better in lightly doped substrate than in heavily doped one. Drain current is also better in lightly doped than heavily doped substrates. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.

APA, Harvard, Vancouver, ISO, and other styles

7

Chowdhury, Md. Iqbal Bahar. "Investigation of quantum efficiency of GaAs/InAs-based quantum well solar cell." Journal of Instrumentation and Innovation Sciences 6, no. 1 (2021): 41–48. https://doi.org/10.5281/zenodo.15302363.

Full text

Abstract:

This work investigates the quantum efficiency of a single-junction gallium arsenide/indium arsenide (GaAs/InAs)- based quantum well solar cell (QWSC), where GaAs (InAs) acts as barrier (quantum well) material. The investigation involves a number of simulations carried out by Silvaco TCAD software tool. The effects of InAs-QWs on the carrier absorption and the carrier recombination have been thoroughly analyzed. The physics-based analysis reveals that there is a maximum limit of the number of InAs-QWs that can be inserted in the intrinsic absorber layer to achieve optimum quantum efficiency and this limit is set by the competition of the photon absorption and the losses incurred optically as well as electronically in the cell.

APA, Harvard, Vancouver, ISO, and other styles

8

Ngah, N. A., Amiza Rasmi, Ashaari Yusof, et al. "Design and Simulation of Top Illuminated InGaAs PIN Photodetector for Millimeter-Wave Applications." Key Engineering Materials 744 (July 2017): 422–27. http://dx.doi.org/10.4028/www.scientific.net/kem.744.422.

Full text

Abstract:

This paper proposed a newdesign of top illuminated PIN photodetector at 1550nm wavelength for millimeter-wave applications. Device topology, structure and fabrication methods were considered in designing the photodetector. The combination material of InP/InGaAsP/InGaAs/InGaAsP was used in designing the top illuminated PIN photodetector. This PIN photodetector was targeted to produce at least 0.60A/W of responsivity with a dark current of <100nA. The design, layout, and electrical characteristics of this photodetector were carried out using SILVACO TCAD tool. The simulated results show higher responsivity value than targeted, device frequency response of -3dBm at 40GHz with targeted dark current achievable within the wavelength absorption bands specification. The results are compared with similar designs from other reported works.

APA, Harvard, Vancouver, ISO, and other styles

9

Chandra, Varun, Nidhi Sinha, and Garima Mathur. "Modeling, Numerical Simulation and Performance Optimization of P3HT:PC₇₀BM Based Bulk Hetero Junction Organic Solar Cells." Journal of Nanoelectronics and Optoelectronics 17, no. 4 (2022): 579–87. http://dx.doi.org/10.1166/jno.2022.3242.

Full text

Abstract:

In this paper we had presented the modeling and simulation of organic solar cell based on P3HT:PC70BM using TCAD tool Silvaco ATLAS™ using Aluminum and Silver as cathodes. The Poole-Frenkel model was used to estimate the organic solar cell characteristics in combination with Langevin recombination model. The main challenges faced during the modeling were the repetitive iteration which was needed to obtain a numerical solution for the figure of merits. The optimized thickness shows the considerable change in efficiency, fill factor and open-circuit voltage. The efficiency obtained is 8.14% with short circuit current density of 20.17 mA/cm2, open circuit voltage as 707.97 mV approximately and fill factor is 55.47% which is higher than the reported works in literature.

APA, Harvard, Vancouver, ISO, and other styles

10

Chawla, Rashmi, Poonam Singhal, and Amit Kumar Garg. "Design and Analysis of Multi Junction Solar Photovoltaic Cell with Graphene as an Intermediate Layer." Journal of Nanoscience and Nanotechnology 20, no. 6 (2020): 3693–702. http://dx.doi.org/10.1166/jnn.2020.17512.

Full text

Abstract:

An efficacious Intermediate Layer (IML) is important for multi junction solar Photo Voltaic Cell (PVC) owing to its good electrical conductivity and optical transparency. In this research work, the use of Graphene as an IML with varied thickness on InGaP/GaAs/InGaAs multi-junction solar PVCs is investigated using virtual fabrication TCAD tool SILVACO-Atlas. The detail absorption rate from wavelength 300 nm (ultraviolet)-2500 nm (middle infra-red region) is determined and the effected modelling stages are recounted. The results after simulation are further confirmed with experimental data to prove accuracy of the research work proposed. The performance parameters with Jsc = 33.4 mA/cm2, Voc = 1.27 V, fill factor (FF) = 99.5% and conversion efficiency of 30.91% (1 sun) are obtained under AM1.5G illumination.

APA, Harvard, Vancouver, ISO, and other styles

11

Yadav, Sunil Kumar, C. S. Raghuvanshi, Hari Om Sharan, Samir Kumar Mishra, and Raghvendra Singh. "Optimization of the Multilayer Energy efficiency OLED for Customizable Electronics Application’s." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 1 (2020): 1155–62. http://dx.doi.org/10.61841/turcomat.v11i1.14592.

Full text

Abstract:

In this Research Paper of the Organic light Emitting diode performance on electro-luminescence postulates, Organic light Emitting diode is industrially convenient due to its low power consumption; it may be utilized as a display. The paper objective is design a high efficiency OLEDs, addressing both electrical and optical facet. The tool, Silvaco TCAD is being used to measure the luminescence intensity of bi-layer and triple-layer OLED technologies. The electrical and optical aspects of 2-layer and 3-layer OLEDs, similarly luminescence power versus anode voltage and current value, while also exciton state, have been modeled. The operational distribution about Langevin recombination inside complexes, as well as the physical design, technologies, and concepts of OLED, have been investigated.

APA, Harvard, Vancouver, ISO, and other styles

12

Firas, Natheer Abdul-kadir, khaleel Mohammad Khalid, and Hashim Yasir. "Investigation and design of ion-implanted MOSFET based on (18 nm) channel length." TELKOMNIKA Telecommunication, Computing, Electronics and Control 18, no. 5 (2020): 2635~2641. https://doi.org/10.12928/TELKOMNIKA.v18i5.15958.

Full text

Abstract:

The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.

APA, Harvard, Vancouver, ISO, and other styles

13

Salem, Marwa S., Omar M. Saif, Ahmed Shaker, et al. "Performance Optimization of the InGaP/GaAs Dual-Junction Solar Cell Using SILVACO TCAD." International Journal of Photoenergy 2021 (February 18, 2021): 1–12. http://dx.doi.org/10.1155/2021/8842975.

Full text

Abstract:

In this work, an optimization of the InGaP/GaAs dual-junction (DJ) solar cell performance is presented. Firstly, a design for the DJ solar cell based on the GaAs tunnel diode is provided. Secondly, the used device simulator is calibrated with recent experimental results of an InGaP/GaAs DJ solar cell. After that, the optimization of the DJ solar cell performance is carried out for two different materials of the top window layer, AlGaAs and AlGaInP. For AlGaAs, the optimization is carried out for the following: aluminum (Al) mole fraction, top window thickness, top base thickness, and bottom BSF doping and thickness. The electrical performance parameters of the optimized cell are extracted: J SC = 18.23 mA / c m 2 , V OC = 2.33 V , FF = 86.42 % , and the conversion efficiency ( η c ) equals 36.71%. By using AlGaInP as a top cell window, the electrical performance parameters for the optimized cell are J SC = 19.84 mA / c m 2 , V OC = 2.32 V , FF = 83.9 % , and η c = 38.53 % . So, AlGaInP is found to be the optimum material for the InGaP/GaAs DJ cell top window layer as it gives 4% higher conversion efficiency under 1 sun of the standard AM1.5G solar spectrum at 300 K in comparison with recent literature results. All optimization steps and simulation results are carried out using the SLVACO TCAD tool.

APA, Harvard, Vancouver, ISO, and other styles

14

Verma, Akshay, and Nitesh Kashyap. "Thickness Dependency Analysis of IGZO-Based Thin Film Transistor." International Journal of Microsystems and IoT 2, no. 10 (2024): 1269–75. https://doi.org/10.5281/zenodo.14168632.

Full text

Abstract:

This paper highlights the thin film transistors used in the latest applications and devices. The working principle of thin film transistors with various device structures can be used to fabricate thin film transistors. Progress in the latest materials that are being used in applications like LCDs, sensors, RFID tags, Displays, etc. The remarkable characteristics of Indium-Gallium-Zinc Oxide (IGZO) thin films, for instance, their transparency and high mobility, have generated significant interest in the application part of Thin-Film Transistors (TFTs). The operation of a-IGZO TFTs taking four different insulators [Si3N4, SiO2, HfO2, and Al2O3] into consideration by varying insulator thicknesses is studied by simulating it over Silvaco [Atlas] TCAD Tool.

APA, Harvard, Vancouver, ISO, and other styles

15

Tayade, Vinod Pralhad, and Swapnil Laxman Lahudkar. "Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs." Advances in Technology Innovation 7, no. 1 (2021): 18–29. http://dx.doi.org/10.46604/aiti.2021.8098.

Full text

Abstract:

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

APA, Harvard, Vancouver, ISO, and other styles

16

Kashyap, Savita, Nikhil Shrivastav, Rahul Pandey, Jaya Madan, and Rajnish Sharma. "Double POLO Carrier Selective Contact Based PERC Solar Cell for 25.5% Conversion Efficiency: A Simulation Study." ECS Transactions 107, no. 1 (2022): 6365–70. http://dx.doi.org/10.1149/10701.6365ecst.

Full text

Abstract:

Polycrystalline Silicon on Oxide (POLO) passivating contacts have emerged as a carrier selective contact for high-efficiency Si-based photovoltaic (PV) devices. In this paper, double POLO PERC (Passivated Emitter and Rear Contact) device is designed by employing POLO contacts on both contact sides to reduce the contact recombination losses through Silvaco-TCAD tool. The performance of the double POLO PERC device has been studied by using the PV parameters and current-density (J-V) curve. The impact of tunnel oxide thickness variation (1 nm, 1.25 nm, 1.5 nm) in the tunnel oxide layer is also analyzed. The performance of textured double POLO PERC solar cell is optimized at 1.5 nm thickness (TOX), which reflects optimum conversion efficiency of 25.5%. Reported study of double POLO PERC device may open up a door for further improvement in PERC device performance.

APA, Harvard, Vancouver, ISO, and other styles

17

Zhou, Kai, Songming Miao, Xuanze Zhou, Guangwei Xu, Lingfei Wang та Shibing Long. "A core drain current model for β-Ga₂O₃ power MOSFETs based on surface potential". AIP Advances 13, № 1 (2023): 015202. http://dx.doi.org/10.1063/5.0134215.

Full text

Abstract:

For the first time, a core drain current model based on surface potential without any implicit functions is developed for beta-phase gallium oxide ( β-Ga2O3) power metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential solution is analytically deduced by solving the Poisson equation with appropriate simplification assumptions in accumulation, partial-depletion, and full-depletion modes. Then, the drain current expression is analytically derived from the Pao–Sah integral as a function of the mobile charge density obtained from the surface potential at the source and drain terminals. In addition, nonlinear resistors in the source/drain access region are considered. It continuously predicts the characteristics of β-Ga2O3 power MOSFETs in all operation modes, including accumulation mode, partial-depletion mode, and full-depletion mode. Furthermore, the validity of the model is verified by comparing the results of the model with the numerical simulations carried out with the technology computer-aided design (TCAD) tool ATLAS Device Simulator from Silvaco. Good agreement between the proposed model and TCAD simulations is shown for β-Ga2O3 power MOSFETs with different intrinsic channel lengths, channel doping concentrations, and channel thicknesses. Ultimately, the Gummel symmetry test and the harmonic balance simulation test are performed to validate the model’s robustness and convergence.

APA, Harvard, Vancouver, ISO, and other styles

18

Hossain, Md Mosabbir, Kh Shakil Ahmed, Kazi Mysoon Rubyat, et al. "Simulation-Driven Fabrication and Performance Evaluation of n-MOSFET using Silvaco Athena and Atlas: From Process to Parameters." Journal of Microprocessor and Microcontroller Research 1, no. 3 (2014): 21–43. http://dx.doi.org/10.46610/jommr.2024.v01i03.003.

Full text

Abstract:

In this work, an n-channel MOSFET of Silvaco TCAD has been fabricated and analyzed using commercially available simulation software tools, namely Athena and Atlas. The fabrication of NMOS has been done through a series of fabrication steps, which include wafer selection with appropriate orientation and phosphorus doping, oxide diffusion, boron-implantation for p-well formation, polysilicon deposition, phosphorus-implantation for heavily doped n+-regions, aluminum-deposition for source/drain contact and extraction of unused materials-all of these steps has been performed through the Athena tool. Afterward, Atlas performs several simulations to deduce the transfer characteristics curves (the ID vs. VGS curves). The various performance parameters of the fabricated device, which include the on current (Ion), the off current (Ioff), the on/off ratio, the threshold voltage (Vth), the subthreshold swing, and the Drain-Induced Barrier Lowering (DIBL), are also determined using the Atlas tool. These simulation-basedanalyses provide a better understanding of an NMOS device's fabrication process and a clearer physical insight into its characteristiccurves and performance parameters.

APA, Harvard, Vancouver, ISO, and other styles

19

Zhang, Wenting, Junliang Shang, Shuang Li, Hu Liu, Mengqi Ma, and Dongping Ma. "Nonvolatile Organic Floating-Gate Memory Using N2200 as Charge-Trapping Layer." Applied Sciences 15, no. 5 (2025): 2278. https://doi.org/10.3390/app15052278.

Full text

Abstract:

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 103.

APA, Harvard, Vancouver, ISO, and other styles

20

Sara, Bechlaghem, Zebentout Baya, and Benamara Zineb. "Investigation of Cu(In, Ga)Se2 solar cell performance with non-cadmium buffer layer using TCAD-SILVACO." Materials Science-Poland 36, no. 3 (2018): 514–19. http://dx.doi.org/10.2478/msp-2018-0054.

Full text

Abstract:

AbstractThe purpose of this work is to achieve the best efficiency of Cu(In, Ga)Se2 solar cells by replacing the CdS buffer layer with other nontoxic materials. The simulation tool used in this study is Silvaco-Atlas package based on digital resolution 2D transport equations governing the conduction mechanisms in semiconductor devices. The J-V characteristics are simulated under AM1.5G illumination. Firstly, we will report the modeling and simulation results of CdS/CIGS solar cell, in comparison with the previously reported experimental results [1]. Secondly, the photovoltaic parameters will be calculated with CdS buffer layer and without any buffer layer to understand its impact on the output parameters of solar cells. The simulation is carried out with the use of electrical and optical parameters chosen judiciously for different buffers (CdS, ZnOS and ZnSe). In comparison to simulated CdS/CIGS, the best photovoltaic parameters have been obtained with ZnOS buffer layer. The structure has almost the same open circuit voltage Voc and fill factor FF, and higher short circuit current density Jsc, which results in slightly higher conversion efficiencies.

APA, Harvard, Vancouver, ISO, and other styles

21

Amine, Mohammed Taberkit, Guen-Bouazza Ahlam, and Bouazza Benyounes. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 421–28. https://doi.org/10.11591/ijece.v8i1.pp421-428.

Full text

Abstract:

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

APA, Harvard, Vancouver, ISO, and other styles

22

Nawaz, Muhammad, and Filippo Chimento. "On the Assessment of Temperature Dependence of 10 - 20 kV 4H-SiC IGBTs Using TCAD." Materials Science Forum 740-742 (January 2013): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1085.

Full text

Abstract:

This paper addresses and evaluates the temperature dependence performance of silicon carbide (4H-SiC) based insulated gate bipolar transistors (IGBTs) using two dimensional numerical computer aided design tool (i.e., Atlas TCAD from Silvaco). Using identical set of device physical parameters (doping, thicknesses), simulated structure was first caliberated with the experimental data. A minority carrier life time in the drift layer of 1.0 – 1.6 µs and contact resistivity of 0.5 - 1.0 x 10-4 Ω-cm2 produces a close match with the experimental device. A set of n type IGBT structures were then numerically simulated to extract the conduction losses for various blocking voltage classes. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 oC) due to decrease in the carrier mobility. Compared with Si based IGBTs, numerical simulation predicts lower VCEON and RON values for 4H-SiC based IGBTs for higher voltage classes and hence potential for achieving smaller conduction losses for SiC based IGBTs.

APA, Harvard, Vancouver, ISO, and other styles

23

Taberkit, Amine Mohammed, Ahlam Guen-Bouazza, and Benyounes Bouazza. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 421. http://dx.doi.org/10.11591/ijece.v8i1.pp421-428.

Full text

Abstract:

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

APA, Harvard, Vancouver, ISO, and other styles

24

Abushattal, Ahmad A., Antonio García Loureiro, and Nour El I. Boukortt. "Ultra-High Concentration Vertical Homo-Multijunction Solar Cells for CubeSats and Terrestrial Applications." Micromachines 15, no. 2 (2024): 204. http://dx.doi.org/10.3390/mi15020204.

Full text

Abstract:

This paper examines advances in ultra-high concentration photovoltaics (UHCPV), focusing specifically on vertical multijunction (VMJ) solar cells. The use of gallium arsenide (GaAs) in these cells increases their efficiency in a range of applications, including terrestrial and space settings. Several multijunction structures are designed to maximize conversion efficiency, including a vertical tunnel junction, which minimizes resistive losses at high concentration levels compared with standard designs. Therefore, careful optimization of interconnect layers in terms of thickness and doping concentration is needed. Homo-multijunction GaAs solar cells have been simulated and analyzed by using ATLAS Silvaco 5.36 R, a sophisticated technology computer-aided design (TCAD) tool aimed to ensure the reliability of simulation by targeting a high conversion efficiency and a good fill factor for our proposed structure model. Several design parameters, such as the dimensional cell structure, doping density, and sun concentrations, have been analyzed to improve device performance under direct air mass conditions AM1.5D. The optimized conversion efficiency of 30.2% has been achieved with investigated GaAs solar cell configuration at maximum concentration levels.

APA, Harvard, Vancouver, ISO, and other styles

25

Raghav, Pooja, Manisha Bharti, and Neha Paras. "Detection of Herpes Biomolecule using Ge-based Dielectrically Modulated TFET." International Journal of Microsystems and IoT 2, no. 10 (2024): 1246–53. https://doi.org/10.5281/zenodo.14167709.

Full text

Abstract:

In this, dielectrically modulated TFET architecture based on Germanium is proposed for label-free detection of herpes virus. Comprehensive numerical device simulations performed on Silvaco 2D TCAD tool are used to study the performance of these biosensor. By altering the gate voltage, the effectiveness of this biosensor is evaluated based on current sensitivity. This paper will primarily focus on examining the biosensor's sensitivity and performance of a tunnel field-effect transistor (TFET) device. A detailed analysis of the device's ON current, OFF current and subthreshold swing has been conducted. For the specific case of k=70, the full cavity Ge-DMTFET exhibits an impressive sensitivity of 7.29 x 108, accompanied by an outstanding ION/IOFF ratio of 2.11 × 108 and a subthreshold swing of 56.366 mV/dec. The suggested TFET has a lower subthreshold slope, a higher ION/IOFF current ratio, and greater sensitivity as a result of its unique design. As a label-free biosensor, presence and absence of charge of different biomolecules are taken into account when evaluating the sensitivity of the device.

APA, Harvard, Vancouver, ISO, and other styles

26

B, Kalivaraprasad, S. Ravi Chand, S. Koteswari, P. Madhu Sudhan Reddy, K. Sai Anurag, and K. Palanivel Rajan. "Design and Modelling of Tunnel Field Effect Transistor- using TCAD Modeling." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 4s (2023): 224–31. http://dx.doi.org/10.17762/ijritcc.v11i4s.6532.

Full text

Abstract:

The purpose of this research was to suggest a junction-less strategy for a vertical Tunnel Field Effect Transistor, which would increase the device's efficiency. In this study, we examine the similarities and differences between a negative capacitor TFET and a vertically generated TFET with a source pocket and a heterostructure-based nanowire gate. And how the channel transit impacts the output qualities of a sub-100 nanometer sized device. The Silvaco TCAD (a commercially available tool) was used to simulate a tri-layer high-K dielectric made of hafnium zirconium oxide (HZO) and titanium dioxide (TiO2) materials as gate stacking to the V-TFET and GAA-NC-TFET structures, and the tunnelling and transport parameters were calibrated experimentally. A short bandgap material, GaSb, in the home region to enhance carrier tunnelling via the mentioned three source (GaSb)-channel (Si) heterojunction at varying biases were utilized. Motion, tube length, and saturating velocity are only few of the transport channel characteristics that are investigated. As a result of the building's vertical orientation, the electric field is enhanced, allowing for an ION current of up to 104 Am2. The most unexpected result of this device is that a high ION/IOFF may increase mobility and reduce saturation velocity, perhaps reducing the drain voltage at saturation. The proposed biosensor's sensitivity was multiplied by 108 when vertical and lateral tunnelling were used in tandem. We apply a variety of optimisation strategies to deal with this problem, despite the fact that quantum confinement reduces the effect of mobility variations on device performance. When biomolecules were positively charged, the drain current increased, and when they were negatively charged, the drain current decreased.

APA, Harvard, Vancouver, ISO, and other styles

27

Das, Samadrita, Trupti Ranjan Lenka, Fazal Ahmed Talukdar, Hieu Pham Trung Nguyen, and Giovanni Crupi. "Polarization Engineered p-Type Electron Blocking Layer Free AlGaN Based UV-LED Using Quantum Barriers with Heart-Shaped Graded Al Composition for Enhanced Luminescence." Micromachines 14, no. 10 (2023): 1926. http://dx.doi.org/10.3390/mi14101926.

Full text

Abstract:

In this paper, in order to address the problem of electron leakage in AlGaN ultra-violet light-emitting diodes, we have proposed an electron-blocking free layer AlGaN ultra-violet (UV) light-emitting diode (LED) using polarization-engineered heart-shaped AlGaN quantum barriers (QB) instead of conventional barriers. This novel structure has decreased the downward band bending at the interconnection between the consecutive quantum barriers and also flattened the electrostatic field. The parameters used during simulation are extracted from the referred experimental data of conventional UV LED. Using the Silvaco Atlas TCAD tool; version 8.18.1.R, we have compared and optimized the optical as well as electrical characteristics of three varying LED structures. Enhancements in electroluminescence at 275 nm (52.7%), optical output power (50.4%), and efficiency (61.3%) are recorded for an EBL-free AlGaN UV LED with heart-shaped Al composition in the barriers. These improvements are attributed to the minimized non-radiative recombination on the surfaces, due to the progressively increasing effective conduction band barrier height, which subsequently enhances the carrier confinement. Hence, the proposed EBL-free AlGaN LED is the potential solution to enhance optical power and produce highly efficient UV emitters.

APA, Harvard, Vancouver, ISO, and other styles

28

Jihane, Ouchrif, Baghdad Abdennaceur, Sahel Aicha, Badri Abdelmajid, and Ballouk Abdelhakim. "How does technological parameters impact the static current gain of InP-based single heterojunction bipolar transistor?" International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3432–40. https://doi.org/10.11591/ijece.v9i5.pp3432-3440.

Full text

Abstract:

In telecommunication systems, Heterojunction Bipolar Transistors (HBTs) are used extensively due to their good electrical characteristics. The work presented in this paper aims to enhance the electrical performance of the InP / InGaAs Single Heterojunction Bipolar Transistor (SHBT) in terms of the static current gain β. Silvaco’s TCAD tools were used for the simulation of the output characteristics of the studied electronic device. Initially, we used the interactive tool Deckbuild to define the simulation program and the device editor DevEdit to design the device structure, and we also used the simulator Atlas which allows the prediction of the electrical characteristics of most semiconductor devices. Because of several phenomena occuring within the electronic device SHBT, we added some physical models included in the simulator such as SRH, BBT.STD. Afterwards, we investigated the influence of doping concentrations of the base and the collector Nb and Nc on the electrical performance of the InP/InGaAs SHBT, and particularly in terms of the static current gain β. Finally, based on optimal values of the selected parameters, we have defined an optimized device that has a highest current gain β.

APA, Harvard, Vancouver, ISO, and other styles

29

Djedoui, L., A. Aissat, A. Djemouai, and J. Vilcot. "Improving the efficiency of a GaInP solar cell using an AlGaAs buffer layer by optimizing the thicknesses of the PN junction." Digest Journal of Nanomaterials and Biostructures 17, no. 4 (2022): 1191–202. http://dx.doi.org/10.15251/djnb.2022.174.1191.

Full text

Abstract:

In this work, the design and simulation of an GaInP single junction solar cell are presented. The work focuses mainly on the optimization of the PN junction thicknesses of n-base and pemitter cell layers in order to improve the cell conversion efficiency. Besides this optimization, the layers of the cell window AlGaInP and an added buffer AlGaAs were also optimized in term of doping and thicknesses using Atlas tool of SILVACO TCAD. The cell is simulated under the conditions of 1 sun and AM1.5G solar spectrum at 25°C. The simulated GaInP solar cell demonstrates an efficiency (𝜂𝜂) of 22.42%. The cell shows different electrical behaviors in terms of short circuit current density (Jsc), open circuit voltage (Voc), fill factor (FF), and external quantum efficiency (EQE). The obtained results are compared with those reported in the literature. Simulation results of the cell are: a Jsc of 18.35 mA/cm2 , Voc of 1.41 V and FF of 86.81% with the corresponding n-base layer and pemitter layer thickness of 0.410 µm and 0.174 µm respectively and the total device thickness of 0.65 µm. According to these results, the proposed cell demonstrates an improvement in the efficiency and a reduction of the used GaInP material.

APA, Harvard, Vancouver, ISO, and other styles

30

Ameer, F. Roslan, Salehuddin F., S. M. Zain A., E. Kaharudin K., and Ahmad I. "Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 18, no. 2 (2020): 724–30. https://doi.org/10.11591/ijeecs.v18.i2.pp724-730.

Full text

Abstract:

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology.

APA, Harvard, Vancouver, ISO, and other styles

31

F. Roslan, Ameer, F. Salehuddin, A. S. M. Zain, K. E. Kaharudin, and I. Ahmad. "Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (2020): 724. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp724-730.

Full text

Abstract:

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology.

APA, Harvard, Vancouver, ISO, and other styles

32

Rashid, Muhammad Haroon, Ants Koel, and Toomas Rang. "Nano- and Micro-Scale Simulations of Ge/3C-SiC and Ge/4H-SiC NN-Heterojunction Diodes." Materials Science Forum 1004 (July 2020): 490–96. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.490.

Full text

Abstract:

During the last decade, silicon carbide (SiC) and its heterostructures with other semiconductors have gained a significant importance for wide range of electronics applications. These structures are highly suitable for high frequency and high power applications in extremely high temperature environments. SiC exists in more than 200 different polycrystalline forms, called polytypes. Among these 200 types, the most prominent polytypes with exceptional physical and electrical attributes are 3C-SiC, 4H-SiC and 6H-SiC. Heterostructures of these SiC polytypes with other conventional semiconductors (like Si, Ge) can give rise to interesting electronic characteristics. In this article, Germanium (Ge) has been used to make heterostructures with 3C-SiC and 4H-SiC using a novel technique called diffusion welding. Microscale and nanoscale simulations of nn-heterojunction of Ge/3C-SiC and Ge/4H-SiC have been done. Microscale devices have been simulated with a commercially available semiconductor device simulator tool called Silvaco TCAD. Whereas nanoscale devices have been simulated with QuantumWise Atomistix Toolkit (ATK) software package. Current-voltage (IV) curves of all simulated devices have been calculated and compared. In nanoscale device, the effects of defects on IV-characteristics due to non-ideal bonding (lattice misplacement) at heterojunction interface have been analyzed. Our simulation results reveal that the proposed heterostructure devices with diffusion welding of wafers are theoretically possible. These simulations are the preparations of our near future physical experiments targeted to fabricate SiC based heterostructure devices using diffusion bonding technique.

APA, Harvard, Vancouver, ISO, and other styles

33

Singh, Sarabdeep, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, and Amandeep Singh. "Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier." Micromachines 14, no. 7 (2023): 1357. http://dx.doi.org/10.3390/mi14071357.

Full text

Abstract:

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

APA, Harvard, Vancouver, ISO, and other styles

34

Gowthami, Y., B.Balaji, and K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.

Full text

Abstract:

The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.

APA, Harvard, Vancouver, ISO, and other styles

35

Barzdenas, Vaidotas, Gediminas Grazulevicius, and Aleksandr Vasjanov. "TCAD tools in undergraduate studies: A laboratory work for learning deep submicron CMOS processes." International Journal of Electrical Engineering & Education 57, no. 2 (2019): 133–63. http://dx.doi.org/10.1177/0020720919846811.

Full text

Abstract:

This article discusses one exemplary and one original laboratory work from the micro- and nano-electronics manufacturing process laboratory works cycle. These laboratory works have been successfully introduced into the undergraduate programme and have been attended by students for several years at Vilnius Gediminas Technical University, Faculty of Electronics. This laboratory work is unique in that it consistently displays and graphically depicts practically all CMOS transistor manufacturing processes: from the preparation of the silicon wafer to the final passivation. Silvaco TCAD tools are used in order to simulate these technological processes. This type of laboratory works provides students with the necessary knowledge of chip manufacturing processes and TCAD tools without the use of costly manufacturing equipment specific to each technological process in the fabrication chain, long-term experiments and a large amount of human resources. This article also presents and discusses student feedback statistics over several years of studies, the advantages of this laboratory work, recommendations for further improvement and formulates conclusions.

APA, Harvard, Vancouver, ISO, and other styles

36

Sanjay, Sooraj, Fahimul Islam Sakib, Mainul Hossain, and Navakanta Bhat. "(Invited, Digital Presentation) Super-Nernstian Isfet Combining Two-Dimensional WSe₂/MoS₂ Heterostructure with Negative Capacitance." ECS Meeting Abstracts MA2022-02, no. 15 (2022): 823. http://dx.doi.org/10.1149/ma2022-0215823mtgabs.

Full text

Abstract:

Ion-sensitive field-effect transistors (ISFETs) are quite popular as compact, low-cost biosensors with fast response time and label-free detection1. They can be used as pH sensors or functionalized for complex biomolecule detection. The voltage sensitivity (Sv) in classical ISFETs is fundamentally limited to 59 mV/pH (Nernst limit). Surpassing the Nernst limit requires complex device architectures or novel transport phenomena. Sensitivity beyond the Nernst limit can be achieved using specific device architectures such as dual gate ISFETs2, negative capacitance ISFETs (NC-ISFET)3, tunnel ISFETs4, etc. Compatible architectures can be combined for further enhancements in sensitivity. First, we experimentally demonstrate a super-Nernstian hetero-ISFET that uses 2-D WSe2/MoS2 heterostructure in a double-gated configuration5. The schematic of the device structure is shown in Fig. 1(a) along with its dimensions. The fluid gate to the pH solution is biased at VFG = 0 V and the voltage sensitivity (SV) is extracted by applying bias to the back-gate (VBG). Fig. 1(b) shows the variation of drain current for change in VBG at different pH. The voltage sensitivity is also included in the same graph. The device uses charge screening due to the interface traps and inversion charges at the hetero-interface to modulate the back-gate transconductance (gmb), thereby allowing super sensitivity. Further enhancement in sensitivity is explored using technology computer-aided (TCAD) device simulator tool (Silvaco ATLAS) by integrating with different device architectures. First we model the baseline hetero-ISFET. The 2-D materials were modeled using their material parameters and 3-D equivalents of their density of states. Amorphous hafnium oxide (HfO2) was used as the dielectric. The mobile ions in the electrolyte were modeled as charge carriers in an intrinsic semiconductor, with its effective density of states varying as a function of pH. The simulation model was calibrated with the experimental device (at pH = 7), as shown in Fig. 2(a). The transfer characteristics of the back-gate at different pH and fixed VFG (= 0 V) for the simulated device is shown in Fig. 2(b). We note that the sensitivity from simulations is lower than the experimental device. This is likely due to non-ideal and 2-D material specific factors which are not accounted in simulations. Nevertheless, the simulated device also shows super-Nernstian sensitivity (Fig. 2(b), right axis), validating the model. Hence, the calibrated TCAD model is used as the baseline for further studies. Next, an NC-FE layer (aluminum-doped HfO2) was added to the top fluid-gate stack6. We have used a ferroelectric-metal-insulator-semiconductor (FMIS) stack for the proposed NC-hetero-ISFET. Fig. 3(a) shows the new top-gate stack with the FMI layer, which replaces the top-gate stack in the earlier schematic. The fluid-gate charge (QFG), and drain current (ID) as a function of VFG (VBG = 0 V), were obtained from the TCAD simulations. The 1-D Landau–Khalatnikov (L-K) equations were used to model the voltage across the FE layer (VFE = 2αQFG+4βQ3 FG = V' FG - Vint; where V' FG is the newly computed fluid-gate bias and Vint is the internal node voltage)7. The calculated Vint (for fixed V' FG) is coupled back into the ATLAS simulator to extract voltage sensitivity (SV) by sweeping VBG at different pH values. The fluid-gate transfer curve of the proposed NC-hetero-ISFET, in Fig. 3(b), clearly shows a steeper sub-threshold slope and higher ON current than the baseline device. The corresponding FE layer parameters are shown in Table 1. These improved fluid-gate characteristics contribute to an increased voltage-sensitivity (SV) when VBG is applied. The transfer characteristic (ID v/s VBG, at fixed V' FG) of the NC-hetero-ISFET at different pH values is shown in Fig. 3(c), along with the voltage sensitivity. Further, in Fig. 3(d), we compare the peak SV obtained at different V' FG. There is an improvement in voltage sensitivity (as much as ~ 100 mV/pH) over the baseline device when NC is introduced. The results pave the way for highly sensitive super-Nernstian ISFETs by combining 2-D heterostructure with NC effect. References: P. Bergveld, Sensors Actuators, B Chem., 88, 1–20 (2003). M. Spijkman et al., Appl. Phys. Lett., 98, 2011–2014 (2011). F. Bellando et al., Appl. Phys. Lett., 116, 173503 (2020) P. Dwivedi, R. Singh, and Y. S. Chauhan, IEEE Sens. J., 21, 3233–3240 (2021). S. Sanjay, M. Hossain, A. Rao, and N. Bhat, npj 2D Mater. Appl. 2021 51, 5, 1–8 (2021) S. Salahuddin and S. Datta, Nano Lett, 8, 405–410 (2008) F. I. Sakib, M. A. Hasan, and M. Hossain, IEEE Trans. Electron Devices, 69, 311–317 (2022). Figure 1

APA, Harvard, Vancouver, ISO, and other styles

37

Anil Kumar, Anil Kumar. "Optimization of Threshold Voltage for 65nm PMOS Transistor using Silvaco TCAD Tools." IOSR Journal of Electrical and Electronics Engineering 6, no. 1 (2013): 62–67. http://dx.doi.org/10.9790/1676-0616267.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Barzdenas, Vaidotas, Gediminas Grazulevicius, John Liobe, Aleksandr Vasjanov, and Leonid Kladovscikov. "Verification of a Fabless Device Model Using TCAD Tools: from Bipolar Transistor Formation to I-V Characteristics Extraction." Ingeniería e Investigación 41, no. 3 (2021): e88685. http://dx.doi.org/10.15446/ing.investig.v41n3.88685.

Full text

Abstract:

This paper describes the analysis of processes used in microand nanoelectronic device manufacturing. It also presents an exemplary and novel laboratory exercise in which an epitaxial planar n + pn bipolar transistor with junction isolation is illustrated and analyzed stepbystep. Only seven photolithography steps are used to obtain this bipolar transistor structure: for buried layer formation, for junction transistor isolation and collectors regions formation, for base region formation, for emitter and collector n+ region formation, for contact windows, for first aluminum metallization, and, finally, for passivation. Silvaco TCAD software tools are used to implement all of these manufacturing processes and to simulate the resulting IV characteristics of all presented semiconductor structures. This type of laboratory work provides students with basic knowledge and a consistent understanding of bipolar transistor manufacturing, as well as facilitating theoretical understanding, analysis, and simulation of various semiconductor manufacturing processes without the need for costly and lengthy technological manufacturing experiments. This article also presents the conclusions and other benefits of such laboratory work, as well as possible recommendations for further improvement or expansion.

APA, Harvard, Vancouver, ISO, and other styles

39

Anizam, Fatin Antasha, Lyly Nyl Ismail, Norsabrina Sihab, and Nur Sa’adah Mohd Sauki. "Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools." Journal of Electrical & Electronic Systems Research 19, OCT2021 (2021): 143–48. http://dx.doi.org/10.24191/jeesr.v19i1.019.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Boukortt, Nour El I., Amal M. AlAmri, Feriel Bouhjar, and Kheira Bouhadiba. "Investigation and optimization of ultrathin Cu(In,Ga)Se2 solar cells by using silvaco-TCAD tools." Journal of Materials Science: Materials in Electronics 32, no. 16 (2021): 21525–38. http://dx.doi.org/10.1007/s10854-021-06661-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Ouchrif, Jihane, Abdennaceur Baghdad, Aicha Sahel, Abdelmajid Badri, and Abdelhakim Ballouk. "How does technological parameters impact the static current gain of InP-based Single Heterojunction Bipolar Transistor?" International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3432. http://dx.doi.org/10.11591/ijece.v9i5.pp3432-3440.

Full text

Abstract:

In telecommunication systems, Heterojunction Bipolar Transistors (HBTs) are used extensively due to their good electrical characteristics. The work presented in this paper aims to enhance the electrical performance of the InP / InGaAs Single Heterojunction Bipolar Transistor (SHBT) in terms of the static current gain β. Silvaco’s TCAD tools were used for the simulation of the output characteristics of the studied electronic device. Initially, we used the interactive tool Deckbuild to define the simulation program and the device editor DevEdit to design the device structure, and we also used the simulator Atlas which allows the prediction of the electrical characteristics of most semiconductor devices. Because of several phenomena occuring within the electronic device SHBT, we added some physical models included in the simulator such as SRH, BBT.STD. Afterwards, we investigated the influence of doping concentrations of the base and the collector Nb and Nc on the electrical performance of the InP/InGaAs SHBT, and particularly in terms of the static current gain β. Finally, based on optimal values of the selected parameters, we have defined an optimized device that has a highest current gain β.

APA, Harvard, Vancouver, ISO, and other styles

42

Ramesh, L., S. Moparthi, P. K. Tiwari, V. R. Samoju, and G. K. Saramekala. "Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO-=SUB=-2-=/SUB=-/La-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=-/HfO-=SUB=-2-=/SUB=- (HLH) Sandwich Gate Dielectrics." Физика и техника полупроводников 54, no. 10 (2020): 1098. http://dx.doi.org/10.21883/ftp.2020.10.49949.9395.

Full text

Abstract:

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) is investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide HfO2/lanthanum oxide La2O3/hafnium dioxide HfO2 (HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85&#183;10-3 A/&mu;m, very low OFF-current of 2.53&#183;10-17 A/&mu;m, very high ION/IOFF ratio of 1.51&#183;1014, the threshold voltage of 0.642 V, high mobility of 35 cm2&#183;v-1&#183;s-1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures. Keywords: single active layer (SAL), dual active layer (DAL), double-gate dual active layer (DG-DAL), InGaZnO (IGZO), InSnO (ITO), thin-film transistor (TFT), HfO2/La2O3/HfO2 (HLH).

APA, Harvard, Vancouver, ISO, and other styles

43

"Modelling and Efficiency Analysis of InGaP/GaAs Single Junction PV cells with BSF." International Journal of Engineering and Advanced Technology 8, no. 6 (2019): 623–27. http://dx.doi.org/10.35940/ijeat.f8081.088619.

Full text

Abstract:

The purposes of PV cells are to transfer light energy into electrical energy. A compelling BSF is a key basic component for a productive PV cell.. In this paper, two significant materials GaAs and InGaP with top BSF and base BSF cells are researched utilizing the computational numerical modelling TCAD tool based Silvaco ATLAS. Past research observed that on the current coordinating condition with top BSF layer and base BSF layer, the cell show a general upgrade of density in Isc (short circuit current ) and Voc (open circuit voltage ) subsequently improving the overall efficiency of the cell. In this paper, structure of various thin film PV cells based on III-V materials e.g. GaN, InGaN have been used to design the multi junction PV cells. Extraction of figures of merits (efficiency, open circuit OC voltage, short circuit SC current and fill factor), simulation of electrical and optical characteristics of these devices have been carried out in this work. Our focus is to improve the optical characteristics, refractive index and absorption coefficient of InGaP with BSF and tunnelling features. In this paper complete Simulation and experimental results are shown and compared. The objective of this paper is to examine the productivity of InGaP/GaAs PV cells utilizing the Silvaco Atlas TCAD simulation software.

APA, Harvard, Vancouver, ISO, and other styles

44

"Self-Heating Effects in SiGe Heterojunction Bipolar Transistor with Different Ge Grading Profile." International Journal of Innovative Technology and Exploring Engineering 8, no. 12 (2019): 3993–99. http://dx.doi.org/10.35940/ijitee.l3486.1081219.

Full text

Abstract:

A comparative account of self heating effect of four SiGe HBTs with different Ge grading profiles, designated as Hybrid Trapezoidal (HT), Symmetrically Triangular (ST), Linear Increasing (LI), and Conventional Trapezoidal (CT) with maximum Ge contents of 20%, is presented. Based on an experimentally validated model of the Silvaco TCAD tool, the properties of the four HBTs are simulated. It is observed that both self heating and local temperature increase due to higher device power dissipation. The effect of energy balance and non iso thermal energy balance effect is observed in SiGe HBT with different Ge base profile have been studied in terms of DC, AC, and RF performances and compared .

APA, Harvard, Vancouver, ISO, and other styles

45

Amin, S. Intekhab, and Dr M. S. Alam. "Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET Using TCAD TOOL." International Journal of Computer Science and Informatics, July 2011, 41–46. http://dx.doi.org/10.47893/ijcsi.2011.1008.

Full text

Abstract:

Virtual Fabrication of sub-40nm Bulk MOSFET is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in terms of gm, gds ,Av ,fT and fmax .The simulation result predict that gm is 3.75ms for engineered MOSFET as compared to nonengineered MOSFET with gm of 2.9ms for similar gate length, similarly Av for engineered device is 17.5db and for non-engineered device is 6.96db,fT is 146GHz and for non-engineered fT is 65GHz,fmax is 299GHz for engineered device and for nonengineered device fmaxis 170GHz and a comparison of an engineered device is done with a non engineered device to investigate the improved performance of an engineered device as compared to a non engineered device. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.

APA, Harvard, Vancouver, ISO, and other styles

46

Verma, Akshay, and Nitesh Kashyap. "Impact of insulating layer thickness variation on Igzo-based thin-film transistor performance." Engineering Research Express, November 25, 2024. http://dx.doi.org/10.1088/2631-8695/ad970c.

Full text

Abstract:

Abstract This paper highlights the thin film transistors used in the latest applications and devices. The working principle of thin film transistors with various device structures can be used to fabricate thin film transistors. Progress in the latest materials that are being used in applications like LCDs, sensors, RFID tags, Displays, etc. The remarkable characteristics of Indium-Gallium-Zinc Oxide (IGZO) thin films, for instance, their transparency and high mobility, have generated significant interest in the application part of Thin-Film Transistors (TFTs). Simulating the functioning of a-IGZO TFTs over Silvaco [Atlas] TCAD Tool, four distinct insulators [SiO2, Si3N4, HfO2, and Al2O3] are taken into consideration by adjusting insulator thicknesses and measuring the overall current density.&#xD;

APA, Harvard, Vancouver, ISO, and other styles

47

"An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor." International Journal of Recent Technology and Engineering 8, no. 3 (2019): 603–8. http://dx.doi.org/10.35940/ijrte.b2253.098319.

Full text

Abstract:

The given paper proposes the 2D analytical modeling of surface potential and electric field for a Dual Source Vertical Tunnel Field Effect Transistor (DSV-TFET). The 2-D Poisson equations are solved by parabolic approximation method, with the help of suitable boundary conditions and analytical expressions for surface potential and electric field distribution in DSV-TFET. The analytical results of proposed model are compared with simulation results drive using SILVACO TCAD tool, whereas in our proposed device DSV-TFET provides the high on current (ION=1.74×10-4 A/µm), low OFF current (IOFF= 6.92 ×10-13 A/µm), ION/IOFF current ratio in order of 108 to 109 with the minimum point of average subthreshold slope of 3.47 mV/decade which can be used for low power application.

APA, Harvard, Vancouver, ISO, and other styles

48

Salim, Bindu. "Modeling of Ion Sensitive Field Effect Transistor for Sensing Application using TCAD." Frontiers in Advanced Materials Research, December 29, 2024, 46–53. https://doi.org/10.34256/famr2425.

Full text

Abstract:

Hydrogen ion concentration (pH) of a solution can be measured using FET type sensor called Ion sensitive field effect transistor, ISFET. Chemical reactions occur at the electrolyte – insulator interface making the FET sensitive to pH. The objective of this work is to model the electrolyte-insulator structure of a transistor using Silvaco TCAD tool. Sensitivity is measured based on the shift in the threshold voltage which is caused by the effect of pH on the charge and the potential distributions in the gate insulator. Based on the analytical calculation of parameters of the electrolyte region, semiconductor materials are used to model the reference electrode and electrolyte. In this study, Silicon Nitride and Aluminum Oxide are used as gate insulators for ISFET and their performance comparison is made for sensing applications. The transfer and output characteristics of the transistor are obtained by simulation for both the films for various thicknesses. A comparison of the effect of thickness of films on device performance is analyzed since the dielectric constant of Aluminum oxide is higher than Silicon nitride.

APA, Harvard, Vancouver, ISO, and other styles

49

Chamola, Paritosh, and Poornima Mittal. "Parametric extraction and internal analysis of fullerene-based polymer bulk heterojunction solar cell." Main Group Chemistry, November 22, 2022, 1–12. http://dx.doi.org/10.3233/mgc-220038.

Full text

Abstract:

This paper present device model simulation describing the current-voltage characteristics of polymer/fullerene bulk heterojunction solar cell. In the research paper an organic photovoltaic device with PPV/PCBM [poly (2-methoxy-5-{3’,7’-dimethyloctyloxy}-p-phenylene vinylene) and {6,6}- phenyl C61-butyric acid methyl ester] was simulated via Silvaco TCAD 2-D simulation tool. PCBM acts as acceptor and PPV is donor. The models used to simulate the device were Langevin for recombination, s.binding and a.singlet. Simulation of these type of devices is an vital approach to project and predict the cell performance. Under the illumination of one sun (AM 1.5) the simulated organic cell showed a short circuit current density (J SC ) of 28 A/m2, open circuit voltage (V OC ) of 0.84 Volt and a fill factor (FF) of 52.51%, the resulting maximum efficiency of the PPV/PCBM organic solar cell is 1.22%.

APA, Harvard, Vancouver, ISO, and other styles

50

Yirak, Mekonnen Getnet, and Rishu Chaujar. "Comparative Assessment of Trap Charges Effect on Triple Hybrid Metal Gate Dielectric Modulated Junctionless Gate All Around Nanowire FET‐Based Biosensor." Advances in Condensed Matter Physics 2025, no. 1 (2025). https://doi.org/10.1155/acmp/3744806.

Full text

Abstract:

This work investigates how interface trap charges (ITCs) affect the performance of biosensors made from junctionless nanowire field‐effect transistors (NWFETs) with triple hybrid metal gate dielectric modulated gates. The subthreshold sensitivity of double and triple metal gate silicon NWFET biosensors was investigated using the SILVACO ATLAS‐TCAD simulation tool, emphasizing the impacts of positive and negative ITCs. Simulations examined the impact of uniformly immobilized biomolecules within the nanogap cavity region and evaluated key electrical characteristics, such as transconductance, switching ratio, drain current, and threshold voltage, under trap charges of ±5 × 1012 cm−2 at the SiO2–silicon interface. Results showed that the triple hybrid metal gate device achieved an 184% improvement in threshold voltage shift compared to the double gate device when negative trap charges were present. The findings imply that integrating negative ITCs enhances the biosensor’s performance and accuracy, emphasizing its importance in device modeling and design optimization.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Silvaco TCAD tool'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles