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Journal articles on the topic 'Silvaco'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 May 2024

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1

Tobbeche, S., and M. N. Kateb. "Two-Dimensional Modelling and Simulation of Crystalline Silicon n⁺pp⁺ Solar Cell." Applied Mechanics and Materials 260-261 (December 2012): 154–62. http://dx.doi.org/10.4028/www.scientific.net/amm.260-261.154.

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In this work, we present the simulation results of the technological parameters and the electrical characteristics of a crystalline silicon n+pp+ solar cell, using two-dimension (2D) software, namely TCAD Silvaco (Technology Computer Aided Design). TCAD Silvaco Athena is used to simulate various stages of the technology manufacturing, while TCAD Silvaco Atlas is used for the simulation of the electrical characteristics and the spectral response of the solar cell. The J-V characteristics and the external quantum efficiency (EQE) are simulated under AM 1.5 illumination. The conversion efficiency(η)of 16.06% is reached and the other characteristic parameters are simulated: the open circuit voltage (Voc) is of 0.63 V, the short circuit current density (Jsc) equals 30.54 mA/cm² and the form factor (FF) is of 0.83 for the n+pp+ solar cell with a silicon nitride antireflection layer (Si3N4). In order to highlight the importance of the back surface field (BSF), a comparison between two cells, one without BSF (structure n+p), the other with one BSF (structure n+pp+), was made. By creating a BSF on the rear face of the cell the short circuit current density increases from 28.55 to 30.54 mA/cm2, the open circuit voltage from 0.6 to 0.63 V and the conversion efficiency from 14.19 to 16.06%. A clear improvement of the spectral response is obtained in wavelengths ranging from 0.65 to 1.1 µm for the solar cell with BSF.

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2

Stęszewski, Jędrzej, Andrzej Jakubowski, and Michael L. Korwin-Pawlowski. "Comparison of 4H-SiC and 6H-SiC MOSFET I-V characteristics simulated with Silvaco Atlas and Crosslight Apsys." Journal of Telecommunications and Information Technology, no. 3 (June 25, 2023): 93–95. http://dx.doi.org/10.26636/jtit.2007.3.837.

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A set of physical models describing silicon carbide with fitting parameters is proposed. The theoretical I-V output and transfer characteristics and parameters of MOS transistors were calculated using Silvaco Atlas and Crosslight Apsys semiconductor device simulation environments

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3

Taouririt, Taki Eddine, Afak Meftah, Nouredine Sengouga, Marwa Adaika, Slimane Chala, and Amjad Meftah. "Effects of high-k gate dielectrics on the electrical performance and reliability of an amorphous indium–tin–zinc–oxide thin film transistor (a-ITZO TFT): an analytical survey." Nanoscale 11, no. 48 (2019): 23459–74. http://dx.doi.org/10.1039/c9nr03395e.

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This study is a numerical simulation obtained by using Silvaco Atlas software to investigate the effect of different types of dielectric layers, inserted between the channel and the gate, on the performance and reliability of an a-ITZO TFT.

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4

Parajuli, D., Deb Kumar Shah, Devendra KC, Subhash Kumar, Mira Park, and Bishweshwar Pant. "Influence of Doping Concentration and Thickness of Regions on the Performance of InGaN Single Junction-Based Solar Cells: A Simulation Approach." Electrochem 3, no. 3 (July 28, 2022): 407–15. http://dx.doi.org/10.3390/electrochem3030028.

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The impact of doping concentration and thickness of n-InGaN and p-InGaN regions on the power conversion efficiency of single junction-based InGaN solar cells was studied by the Silvaco ATLAS simulation software. The doping concentration 5 × 1019 cm−3 and 1 × 1015 cm−3 were optimized for n-InGaN and p-InGaN regions, respectively. The thickness of 300 nm was optimized for both n-InGaN and p-InGaN regions. The highest efficiency of 22.17% with Jsc = 37.68 mA/cm2, Voc = 0.729 V, and FF = 80.61% was achieved at optimized values of doping concentration and thickness of n-InGaN and p-InGaN regions of InGaN solar cells. The simulation study shows the relevance of the Silvaco ATLAS simulation tool, as well as the optimization of doping concentration and thickness of n- and p-InGaN regions for solar cells, which would make the development of high-performance InGaN solar cells low-cost and efficient.

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5

Islam, Md Rabiul, Md Kamrul Hasan, Md Abdul Mannan, M. Tanseer Ali, and Md Rokib Hasan. "Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor." AIUB Journal of Science and Engineering (AJSE) 18, no. 2 (August 31, 2019): 73–80. http://dx.doi.org/10.53799/ajse.v18i2.43.

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We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-based DG MOSFETs shows better performance than Si-based Single gate MOSFETs. The proposed device has drawn the attention over conventional SG-MOSFET due to fas switching performance. The device turn on and turn off voltage is respectively VGS=1V(On state) and VGS-0V(OFF State). To validate our simulation tool and model results, previous research model has been investigated using Silvaco Atlas and the results obtained are compared to the previous results.

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6

Vatyuk, A. A. "Modeling of GaAs pHEMT parameters in Silvaco TCAD." Proceedings of Tomsk State University of Control Systems and Radioelectronics 19, no. 1 (2016): 69–72. http://dx.doi.org/10.21293/1818-0442-2016-19-1-69-72.

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7

Gupta, Vaibhav. "Performance Analysis of TFET and VDSTFET for Low Power Application using the Work Function Engineering." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 25, 2021): 2722–27. http://dx.doi.org/10.22214/ijraset.2021.35534.

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We report a design of TFET which is quite different from conventional TFET. The structure of VTFET is similar to MOSFET but the conducting mechanism is completely different. Vertical TFET is designed perpendicular to the horizontal plane. The switching and carrier transportation mechanism of VTFET is based on the mechanism of the band to band tunneling through a potential barrier and vertical TFET is based on tunneling perpendicular to the device rather than a mechanism like thermionic emission unlike in MOSFET. We have designed a model for the two-dimension structure of V-TFET which consists of the dual-source and single drain. The channel among the drain and gate region is extraordinarily thin. We have plotted the transfer characteristics of V-TFET according to device parameters using TCAD. The comparison of VTFET with DSVTFET is done by using Silvaco TCAD and the effect of source doping, and work function on transfer characteristics of the device is examined by using silvaco TCAD simulations. The proposed device produces a low-off current.

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8

PICOS, R., E. GARCIA, M. ESTRADA, A. CERDEIRA, and B. IÑIGUEZ. "EFFECT OF PROCESS VARIATIONS ON AN OTFT COMPACT MODEL PARAMETERS." International Journal of High Speed Electronics and Systems 20, no. 04 (December 2011): 815–28. http://dx.doi.org/10.1142/s0129156411007070.

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We have studied the effect of some of the possible deviations on the values of the extracted parameters of a specific OTFT model, considering OTFTs designed using P 3 HT as semiconductor layer, PMMA as insulator, bottom gate, and top gold contacts. Specifically, we have studied the influence of misposition or misalignment of the masks, the effect of imperfections of etching, and the effect of variations on the layer deposition process. These effects have been simulated using the Silvaco Athena software, and they have been modeled as horizontal shifts of the etching windows and variations of the layers thickness. Once the devices were defined, they were simulated using Silvaco Atlas, and parameter extraction was performed using a specifically developed algorithm. We have found a strong correlation among some of the physical parameters and the model parameters that may offer useful insight for process optimization. Moreover, strong correlations have been found also among the model parameters. We have used these results to develop a Monte Carlo model, suitable for statistical circuit simulation.

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9

Kløw, Frode, Erik S. Marstein, and Sean Erik Foss. "Tunneling Contact Passivation Simulations using Silvaco Atlas." Energy Procedia 77 (August 2015): 99–105. http://dx.doi.org/10.1016/j.egypro.2015.07.015.

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10

Nabil, Amira, Ahmed Shaker, Mohamed Abouelatta, Hani Ragai, and Christian Gontrand. "Tunneling FET Calibration Issues: Sentaurus vs. Silvaco TCAD." Journal of Physics: Conference Series 1710 (November 2020): 012003. http://dx.doi.org/10.1088/1742-6596/1710/1/012003.

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11

Ellakany, Abdelhady, Abdelhalim Zekry, Mohamed Abouelatta, Ahmed Shaker, Gihan T. Sayah, and Mohamed M. El-Banna. "Analytical and Numerical Investigation of Nanowire Transistor X-ray Detector." Materials 16, no. 7 (March 27, 2023): 2637. http://dx.doi.org/10.3390/ma16072637.

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Recently, nanowire detectors have been attracting increasing interest thanks to their advantages of high resolution and gain. The potential of using nanowire detectors is investigated in this work by developing a physically based model for Indium Phosphide (InP) phototransistor as well as by performing TCAD simulations. The model is based on solving the basic semiconductor equations for bipolar transistors and considering the effects of charge distribution on the bulk and on the surface. The developed model also takes into consideration the impact of surface traps, which are induced by photogenerated carriers situated at the surface of the nanowire. Further, photogating phenomena and photodoping are also included. Moreover, displacement damage (DD) is also investigated; an issue arises when the detector is exposed to repeated doses. The presented analytical model can predict the current produced from the incident X-ray beam at various energies. The calculation of the gain of the presented nanowire carefully considers the different governing effects at several values of energies as well as biasing voltage and doping. The proposed model is built in MATLAB, and the validity check of the model results is achieved using SILVACO TCAD device simulation. Comparisons between the proposed model results and SILVACO TCAD device simulation are provided and show good agreement.

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12

Rolland, Gwen, Christophe Rodriguez, Guillaume Gommé, Abderrahim Boucherif, Ahmed Chakroun, Meriem Bouchilaoun, Marie Clara Pepin, et al. "High Power Normally-OFF GaN/AlGaN HEMT with Regrown p Type GaN." Energies 14, no. 19 (September 24, 2021): 6098. http://dx.doi.org/10.3390/en14196098.

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In this paper is presented a Normally-OFF GaN HEMT (High Electron Mobility Transistor) device using p-doped GaN barrier layer regrown by CBE (Chemical Beam Epitaxy). The impact of the p doping on the device performance is investigated using TCAD simulator (Silvaco/Atlas). With 4E17 cm−3 p doping, a Vth of 1.5 V is achieved. Four terminal breakdowns of the fabricated device are investigated, and the origin of the device failure is identified.

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13

KUMARI, RITI, MANISH GOSWAMI, and B. R. SINGH. "THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs." International Journal of Nanoscience 11, no. 02 (April 2012): 1250021. http://dx.doi.org/10.1142/s0219581x12500214.

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This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.

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14

Chan, C. W., Fan Li, Philip A. Mawby, and Peter M. Gammon. "Numerical Study of Energy Capability of Si/SiC LDMOSFETs." Materials Science Forum 897 (May 2017): 751–54. http://dx.doi.org/10.4028/www.scientific.net/msf.897.751.

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A comparable study is made on the energy capability of 190 V LDMOSFETs in Si/SiC, SOI, PSOI and PSOSiC technology, using capacitive and inductive switching circuits established in SILVACO Mixed-mode simulators. The results show that the PSOSiC has a thermal advantage compared with other SOI structures under a 48-μs-power-pulse condition, but the Si/SiC device offers superior cooling and energy handling ability in all switching cases despite having a larger chip area.

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15

Zhuang, Xiao Feng, Qing Kai Zeng, Bing Ren, Zhen Hua Wang, Yue Lu Zhang, Li Ya Shen, Mei Bi, et al. "A Threshold Voltage Simulation of Hydrogen-Terminated Diamond MESFETs." Advanced Materials Research 482-484 (February 2012): 1093–96. http://dx.doi.org/10.4028/www.scientific.net/amr.482-484.1093.

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In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.

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16

DWIVEDI, A. D. D., and POOJA KUMARI. "TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs." Surface Review and Letters 27, no. 05 (August 23, 2019): 1950145. http://dx.doi.org/10.1142/s0218625x19501452.

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This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

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17

Islam, Muhammad Johirul, Sanjina Mostafa, and Md Iqbal Bahar Chowdhury. "Thickness Optimization of Single Junction Quantum well Solar Cell Using TCAD." International Journal of Engineering and Technologies 18 (April 2020): 1–7. http://dx.doi.org/10.18052/www.scipress.com/ijet.18.1.

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The efficiency increase by inserting quantum wells in a p-i-n solar cell has already been studied practically and theoretically over the years. Here we present a Multi-Quantum-well Single-Junction GaAs/GaSb solar cell which is simulated using Silvaco TCAD, where thicknesses of different layers have been varied to obtain the optimum thickness for maximum efficiency. Comparison is also presented for the same between the solar cells with and without the inclusion of quantum wells.

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18

Islam, Muhammad Johirul, Sanjina Mostafa, and Md Iqbal Bahar Chowdhury. "Thickness Optimization of Single Junction Quantum well Solar Cell Using TCAD." International Journal of Engineering and Technologies 18 (April 9, 2020): 1–7. http://dx.doi.org/10.56431/p-rq2260.

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The efficiency increase by inserting quantum wells in a p-i-n solar cell has already been studied practically and theoretically over the years. Here we present a Multi-Quantum-well Single-Junction GaAs/GaSb solar cell which is simulated using Silvaco TCAD, where thicknesses of different layers have been varied to obtain the optimum thickness for maximum efficiency. Comparison is also presented for the same between the solar cells with and without the inclusion of quantum wells.

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19

Xiong, Yan, and Lai Yu Shu. "A New TIGBT Device with Hole Bypass Emitter and Simulationuse." Applied Mechanics and Materials 427-429 (September 2013): 1105–8. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1105.

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In this paper, a new TIGBT device with Hole Bypass Emitter was proposed. Compared with traditional TIGBT, the new structure introduce a P+ hole bypass region under trench metal emitter. Simulation results by SILVACO show that the new structure suppress latch-up effectively and allow wider Safe Operation Area (SOA) as well as higher security current without latch-up and have better temperature stability. In addition, all the impurity implantations in this structure need no extra mask, it is very convenient for fabrication.

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20

Dubey, Sarvesh, and Rahul Mishra. "Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 9, no. 01 (June 25, 2017): 67–72. http://dx.doi.org/10.18090/samriddhi.v9i01.8340.

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The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

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21

Smaani, Billel, Samir Labiod, Fares Nafa, Mohamed Salah Benlatreche, and Saida Latreche. "Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs." International Journal of Circuits, Systems and Signal Processing 15 (October 25, 2021): 1585–90. http://dx.doi.org/10.46300/9106.2021.15.170.

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In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

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22

Smaani, Billel, Samir Labiod, Fares Nafa, Mohamed Salah Benlatreche, and Saida Latreche. "Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs." International Journal of Circuits, Systems and Signal Processing 15 (September 10, 2021): 1394–99. http://dx.doi.org/10.46300/9106.2021.15.149.

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In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

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23

Zainal, N., Abu Hassan Haslan, Hassan Zainuriah, M. Roslan Hashim, and Naser Mahmoud Ahmed. "Optimization of InGaN Based Light Emitting Diodes." Materials Science Forum 517 (June 2006): 195–201. http://dx.doi.org/10.4028/www.scientific.net/msf.517.195.

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The performance of InGaN quantum well based Light Emitting Diodes; (LEDs) had been numerically investigated by using standard industrial software, Silvaco. In this work, we found that InGaN single quantum well (SQW) LEDs gives better performance than InGaN triple quantum wells LEDs. The simulation results suggest that the inhomogeneity of electron and hole distributions in quantum wells active region plays an important role in the LEDs performance. The threshold current per μm also increases as the number of quantum well is increased.

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24

Pandey, Kamal Prakash. "Device Simulation of Si-Ge HBT Using SILVACO TCAD." International Journal of Computer Sciences and Engineering 6, no. 5 (May 31, 2018): 331–35. http://dx.doi.org/10.26438/ijcse/v6i5.331335.

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25

Cazarre, A., N. Nolhier, F. Morancho, P. Austin, and P. Calmon. "Initiation à la simulation bidimensionnelle Environnement SILVACO ( ATHENA - ATLAS)." J3eA 4 (2005): 003. http://dx.doi.org/10.1051/j3ea:200515.

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26

Ali, Farida A., Abhipsha Sahoo, Tara P. Dash, and Gouranga Bose. "Study of 65 nm n-MOSFET Using SILVACO TCAD." Advanced Science Letters 22, no. 2 (February 1, 2016): 381–83. http://dx.doi.org/10.1166/asl.2016.6850.

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27

Seabroke, G. M., T. Prod’homme, G. Hopkinson, D. Burt, M. Robbins, and A. Holland. "Modelling Gaia CCD pixels with Silvaco 3D engineering software." EAS Publications Series 45 (2010): 433–36. http://dx.doi.org/10.1051/eas/1045077.

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28

Sharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj, and Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET." Journal of Nanoelectronics and Optoelectronics 13, no. 10 (October 1, 2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.

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In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

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29

Rais, A. R. M., S. Sepeai, M. K. M. Desa, M. A. Ibrahim, P. J. Ker, S. H. Zaidi, and K. Sopian. "Photo-generation profiles in deeply-etched, two-dimensional patterns in interdigitated back contact solar cells." Journal of Ovonic Research 17, no. 3 (May 2021): 283–89. http://dx.doi.org/10.15251/jor.2021.173.283.

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Interdigitated back contact (IBC) crystalline silicon solar cell model has been developed by using SILVACO in order to achieve design optimization in non-conventional device configurations. The SILVACO software was employed to evaluate performance of IBC solar cell as a function of texture while keeping identical semiconductor process parameters including doping of emitter, BSF and FSF. Based on the period of the pyramidal texturing, the textured surface can be distributed uniformly throughout the solar cell as exhibited by the 40-μm period pattern for which the incident is uniformly and deeply penetrated inside the IBC solar cell. Therefore, efficiency of the IBC solar cell is boosted to 23.31% in comparison with 22.36% from planar IBC solar cell. The photo-generation profile for planar surface is not uniformly and deeply distributed throughout the IBC solar cell but for P40D20 the distribution of incident photons well distributed and penetrates deeper into IBC solar cell which leads to improved IBC solar cell performance. For IBC solar cells with periods larger than 40 μm, performance is degraded due to formation of shadows within the solar cell located at grooves of pyramid. These shadows effectively reduce number of photons and therefore degrade solar cell performance. Hence, the texturization process can boost solar cell performance only if appropriate parameters are chosen otherwise reduced performance can result due to enhanced shadow effects inside the solar cell even though the front surface has no metallic contacts to physically block light.

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30

Surdi, Harshad, Trevor Thornton, Robert J. Nemanich, and Stephen M. Goodnick. "Space charge limited corrections to the power figure of merit for diamond." Applied Physics Letters 120, no. 22 (May 30, 2022): 223503. http://dx.doi.org/10.1063/5.0087059.

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An interpretation of the unipolar figure of merit is formulated for wide bandgap (WBG) semiconductors based on the on-state specific resistance ([Formula: see text]) derived from the space charge limited current–voltage relationship (Mott–Gurney square law). The limitations of the traditional Ohmic [Formula: see text] for WBG semiconductors are discussed, particularly at low doping, while the accuracy of the Mott–Gurney based [Formula: see text] is confirmed by Silvaco ATLAS drift–diffusion simulations of diamond Schottky pin diodes. The effects of incomplete ionization are considered as well.

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31

Abdul Razak, Hanim, Hazura Haroon, Mardiana Bidin, P. Susthitha Menon, and Sahbudin Shaari. "Free Carrier Absorption Loss of Optical Phase Modulator." Advanced Materials Research 545 (July 2012): 355–58. http://dx.doi.org/10.4028/www.scientific.net/amr.545.355.

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The effect of the free carrier absorption loss on the split-ridge waveguide based phase modulator is analyzed at 1.3 and 1.55 µm. The electrical device performance is predicted using the 2-D semiconductor package SILVACO software under DC operation. Based on the simulation results, it is shown that there is a penalty of increased free carrier absorption as the injected electrons and holes are getting higher. Meanwhile, the loss of the device at 1.3 µm is smaller than that of 1.55 µm at an equal applied voltage.

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32

Maati, Wafa, and Abdelkader Hamdoune. "Aluminium Gallium Nitride (AlGaN)/Gallium Nitride (GaN)/Boron Gallium Nitride (BGaN) High Electron Mobility Transistors (HEMT): From Normally-On to Normally-Off Transistor." Sensor Letters 18, no. 5 (May 1, 2020): 366–70. http://dx.doi.org/10.1166/sl.2020.4226.

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In this paper, using the simulator TCAD SILVACO, the physical parameters to pass from a normallyon to a normally-off AlGaN/GaN HEMT with a BGaN back-barrier, was studied. With n-doped donor layer at 1 × 1016 cm–3, as a results we obtain a threshold voltage of 0.509 V normally-off AlGaN/GaN HEMT. The first transistor is able to operate in high power in better way; the second one is efficient for weak signals up to the X-band, and it has the advantage of being normally-off.

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33

Kuang, Yawei, Yushen Liu, Yulong Ma, Jing Xu, Xifeng Yang, Xuekun Hong, and Jinfu Feng. "Modeling and Design of Graphene GaAs Junction Solar Cell." Advances in Condensed Matter Physics 2015 (2015): 1–7. http://dx.doi.org/10.1155/2015/326384.

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Graphene based GaAs junction solar cell is modeled and investigated by Silvaco TCAD tools. The photovoltaic behaviors have been investigated considering structure and process parameters such as substrate thickness, dependence between graphene work function and transmittance, and n-type doping concentration in GaAs. The results show that the most effective region for photo photogenerated carriers locates very close to the interface under light illumination. Comprehensive technological design for junction yields a significant improvement of power conversion efficiency from 0.772% to 2.218%. These results are in good agreement with the reported experimental work.

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34

Liu, Yue Wei, Rui Xia Yang, and Xiao Chuan Deng. "Design, Fabrication and Characterization of a 4.5kV / 50A 4H-SiC PiN Rectifiers." Materials Science Forum 954 (May 2019): 85–89. http://dx.doi.org/10.4028/www.scientific.net/msf.954.85.

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In this work, a 4.5kV/50A 4H-SiC PiN rectifiers with mesa combined with double-JTE structures is successfully developed for high power applications. Two-dimension numerical device simulator Silvaco-TCAD is applied to optimizing the electrical performance of fabricated rectifiers. Mesa-combined double-JTE structure is utilized to achieve a high blocking voltage with a wider optimum process latitude. A forward current is 50 A at room temperature when SiC PiN device bias 4.1 V, while the maximum blocking voltage achieved is 4.7 kV, reaching up to 86% of parallel-plane junction bulk breakdown.

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Sharma, Manvinder, Anuj Kumar Gupta, Dishant Khosla, Jagbir Singh Gill, and Hauwa Amshi. "Design, Modeling of Ga-As based MESFET for SRAM Cell." CGC International Journal of Contemporary Technology and Research 2, no. 2 (June 26, 2020): 86–89. http://dx.doi.org/10.46860/cgcijctr.2020.06.26.86.

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The main attention in the area of technology is given to the low power SRAM (Static random Access Memory).GaAs SRAM have been developed with great efforts which include its many advantages such as reduced power consumption and temperature tolerance. There are many limitations of conventional cell which are overcome by the design of new cell which is used to simulate SRAM. The structure of MESFET and the limitations are discussed in the paper. Further, a code in silvaco is run and simulated and the result analysis is done using tony plots.

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Elmir, H., B. Dennai, and M. Fillali. "Effect of proton radiation on the performance ofInGaP/GaAs solar cell." Journal of Ovonic Research 17, no. 3 (May 2021): 307–11. http://dx.doi.org/10.15251/jor.2021.173.307.

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To understand the effect of radiation on the performance of tandem solar cells based on III-V materials in space and AM0 ; we exposed our solar cell InGaP/GaAs to proton ions radiation with different energy using SRIM simulation software( Stopping and Range of Ions in Matter ) [1], and we investigate the effect of proton energy. The I-V characteristics and degradation of the electrical parameters (efficiency EFF; current schourt-circuit Jsc, voltage open-cicuit Vco and FF) are simulated by SILVACO TCAD [2] simulation software before and after irradiation.

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Boukortt, N., S. Patanè, and B. Hadri. "Development of High-Efficiency PERC Solar Cells Using Atlas Silvaco." Silicon 11, no. 1 (May 21, 2018): 145–52. http://dx.doi.org/10.1007/s12633-018-9838-8.

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Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

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In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

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Ogorodnikov, D. A., S. B. Lastovskii, and Yu V. Bogatyrev. "Simulating of charge build-up in irradiated MOS/SOI transistors." Proceedings of the National Academy of Sciences of Belarus. Physics and Mathematics Series 55, no. 4 (January 7, 2020): 498–504. http://dx.doi.org/10.29235/1561-2430-2019-55-4-498-504.

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The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.

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Petrauskas, Romas. "RESEARCH OF SELF-FORMATION NANOSTRUCTURES / NANODARINIŲ FORMAVIMOSI PROCESŲ TYRIMAS." Mokslas - Lietuvos ateitis 3, no. 1 (August 22, 2011): 59–62. http://dx.doi.org/10.3846/mla.2011.012.

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Lateral etching processes for the modeling of the geometry of self-formation nanostructures with Silvaco TCAD Athena program are analyzed. Self-formation nanostructures is modeled with different mask selectivity values equal to 2, 10, 40 and 100 with respect to the etching layer, with the etching duration of 0–180 s. The etching rates are constant – 1.33 nm/s. The analysis of the dependence of the etching systematic error on its thickness has been carried out. The computer modeled results are close to the ones produced by means of the application of the analytical calculation models by other authors.

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Jaafar, Hind, Abdellah Aouaj, Ahmed Bouziane, and Benjamin Iñiguez. "An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET." Nanoscience &Nanotechnology-Asia 9, no. 2 (June 25, 2019): 291–97. http://dx.doi.org/10.2174/2210681208666180813122145.

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Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

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Sadoun, Ali. "Extraction of the electrical parameters of the Au/InSb/InP Schottky diode in the temperature range (300 K- 425 K)." International Journal of Energetica 5, no. 1 (July 6, 2020): 30. http://dx.doi.org/10.47238/ijeca.v5i1.120.

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In this work, we have presented a theoretical study of Au/InSb/InP Schottky diode based on current-voltage (I-V) measurement in the temperature range ( 300 K- 425 K). Electrical parameters of Au/InSb/InP such as barrier height (Φb), ideality factor and series resistance have been calculated by employing the conventional (I-V), Norde, Cheung and Chattopadhyay methods. Measurements show that the Schottky barrier height (SBH), ideality factor and series resistance, RS for Au/InSb/InP Schottky diode in the temperature range (300 K–425 K) are 0.602-0.69eV, 1.683-1.234 and 84.54-18.95 (Ω), respectively. These parameters were extracted using Atlas-Silvaco-Tcad logical.

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Hadri, B., and F. Djaafar. "Parametric Requirements for Optimum Performance of InGaP/GaAs Heterojonction Solar Cell." Advanced Materials Research 1105 (May 2015): 131–35. http://dx.doi.org/10.4028/www.scientific.net/amr.1105.131.

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In this paper, we analyze the temperature effect on the performance of photovoltaic cells using a virtual wafer fabrication TCAD Silvaco. As is often done, the previous work on this solar cell involved optimizing it at 300 K, even though operating temperatures are typically higher. Therefore, for this article, we model the InGaP/GaAs heterojunction solar cell from 275 °K to 375° K in 25°K increments while varying their thicknesses and doping levels, as well as varying the molar fraction of InAlAsP, AlGaAs and InGaP. We chose to vary these design parameters to observe their effect on performance and suggest a better design for operating at higher temperatures.

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Abd Rahim, Alhan Farhanah, N. M. Sah, I. H. Hamzah, Siti Noraini Sulaiman, and Musa Mohamed Zahidi. "Study on the Effect of Porous Silicon Sizes for Potential Visible Photodetector." Applied Mechanics and Materials 815 (November 2015): 121–30. http://dx.doi.org/10.4028/www.scientific.net/amm.815.121.

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In this work, the characterization of porous silicon (PS) for potential visible light emission was investigated by simulation. SILVACO TCAD simulator was used to simulate PS by using process simulator, ATHENA and device simulator, ATLAS. Different pore diameter sizes of the PS structures were constructed. The structural, optical and electrical characteristics of the structures PS were investigated by current-voltage (I-V), current gain, spectral response and the energy band gap. It was observed that PS enhances the current gain compare to bulk Si and exhibited photo emission in the visible spectrum which constitutes to the quantum confinement effect of the Si in the PS structures.

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Munir, Tarriq, Azlan Abdul Aziz, Mat Johar Abdullah, and Mohd Fadzil Ain. "Temperature Dependent DC and RF Performance of n-GaN Schottky Diode: A Numerical Approach." Advanced Materials Research 895 (February 2014): 439–43. http://dx.doi.org/10.4028/www.scientific.net/amr.895.439.

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This paper reports the temperature dependent DC and RF characteristics of n-GaN Schottky diode simulated using Atlas/Blaze developed by Silvaco. It was found that as the temperature increases from 300K to 900K the forward current decreases due to lowering of the Schottky barrier with an increase in series-resistance and ideality factor. These observations indicates that tunneling behavior dominates the current flow rather than thermionic emission. Furthermore, the breakdown voltage decreases in reverse bias and insertion loss for RF behavior increases with respect to temperature due to the increase in capacitance near diode junction.Keywords: Atlas/Blaze, Schottky barrier, series resistance, ideality factor, insertion loss.

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Mohd Said, Muzalifah, Zul Atfyi Fauzan, and Nur Fatihah Azmi. "NMOS Low Boron Activation in Pre-Amorphise Silicon." Advanced Materials Research 875-877 (February 2014): 734–38. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.734.

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The high demand of smaller and compact size of MOSFETs has leads to desirable for ultra shallow junction formation with low sheet resistance and good electrical performances. These two characteristics are required to suppress short channel effects and to increase the efficiency of device. In this paper, Pre-amorphise implantation (PAI) PMOS with different doses of Boron and the basic PMOS structure are done by using ATHENA and the performance of devices is compared by using ATLAS software package from Silvaco TCAD. Comparison done in electrical characteristic, I-V curve Ion and Ioff has showed PMOS with PAI technology with low boron doses resulted in increasing electrical performance characteristic.

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Rogdakis, Konstantinos, Edwige Bano, Laurent Montes, M. Bechelany, David Cornu, and Konstantinos Zekentes. "Field Effect Transistors Based on Catalyst-Free Grown 3C-SiC Nanowires." Materials Science Forum 645-648 (April 2010): 1235–38. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1235.

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Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and electrical characterization is presented. Silvaco simulation was used to fit the I-V characteristics and to extract information about the carrier (electrons) concentration and the oxide/NW interface quality. The high trap density and fixed charges at the nanowire/oxide interface, Dit~5x1011 cm-2eV-1 and Qf ~3x1013cm-2, and the high electron concentration (~3x1019 cm-3) originating from unintentional doping severely affect the electrical conduction through the nanowires which has as a result low values of mobility and transconductance, 0.11 cm2/Vs and 7x10-10 A/V, respectively.

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Ranganathan, N., A. Malar, D. Y. Lee, K. Prasad, and K. L. Pey. "Development and Characterization of Tapered Silicon Etch Process by Topography Modeling for TSV Application." Journal of Microelectronics and Electronic Packaging 7, no. 1 (January 1, 2010): 58–66. http://dx.doi.org/10.4071/1551-4897-7.1.58.

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A dual-etch via tapering technology has been presented which combines Bosch process and isotropic etch process. It has been shown that the dual-etch process technology provides a high degree of process flexibility to the user by independently controlling and optimizing the etch rate and profile tapering process. Based on experimental work, RIE process models have been set up using ELITE simulation software from Silvaco. Detailed DOE has been done to optimize the RIE models so that the experimental and simulation results match over a wide range of via geometries and aspect ratios. The optimized models have been further used to predict the aspect ratio induced RIE lag effects.

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Иванов, П. А., А. С. Потапов, and Т. П. Самсонова. "Моделирование переходных процессов в полупроводниковых приборах на основе 4H-SiC (учет неполной ионизации легирующих примесей в модуле ATLAS программного пакета SILVACO TCAD)." Физика и техника полупроводников 53, no. 3 (2019): 407. http://dx.doi.org/10.21883/ftp.2019.03.47295.9014.

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AbstractTransient process in a resistor–capacitor (RC) circuit with a reverse-biased 4 H -SiC p – n diode as the capacitive element is simulated. Simulation is performed with the ATLAS software module from the SILVACO TCAD system for technology computer-aided design (TCAD). An alternative way, to that in ATLAS, to set the parameters of doping impurities partly ionized in 4 H -SiC at room temperature is suggested. (The INCOMPLETE physical model available in the ATLAS module, which describes the incomplete ionization of doping impurities in semiconductors, is unsuitable for simulating the dynamic characteristics of devices.) The simulation results are discussed in relation to previously obtained experimental results.

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Abdul-Kadir, Firas Natheer, Yasir Hashim, Muhammad Nazmus Shakib, and Faris Hassan Taha. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 780. http://dx.doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.

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