Relevant bibliographies by topics / SIMD architecture

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'SIMD architecture'

Author: Grafiati
Published: 4 June 2021
Last updated: 27 April 2022

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Journal articles on the topic "SIMD architecture"

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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.
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Wang, Guang, and Yin Sheng Gao. "An Implementation of Configurable SIMD Core on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1925–29. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1925.

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In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.
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Liu, Song Ping. "Optimization Method of Coherent Accumulation Operation Based on SIMD Architecture." Applied Mechanics and Materials 644-650 (September 2014): 4330–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.4330.

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With SIMD functional unit as part of a wide range of application acceleration, how to effectively use this architecture to optimize the application to become a hot spot compiler optimization. This paper discusses the SIMD instructions and pipeline optimization methods. After using MMX instructions and pipeline optimization, real-time to achieve a strong guarantee pure software receiver.
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FUJITA, YOSHIHIRO, NOBUYUKI YAMASHITA, and SHIN-ICHIRO OKAZAKI. "IMAP: INTEGRATED MEMORY ARRAY PROCESSOR." Journal of Circuits, Systems and Computers 02, no. 03 (1992): 227–45. http://dx.doi.org/10.1142/s0218126692000155.

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This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.
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Suaib, Mohammad, Abel Palaty, and Kumar Sambhav Pandey. "Architecture of SIMD Type Vector Processor." International Journal of Computer Applications 20, no. 4 (2011): 42–45. http://dx.doi.org/10.5120/2418-3233.

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Jiang, Li, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, and Xiaoyao Liang. "CNFET-Based High Throughput SIMD Architecture." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 7 (2018): 1331–44. http://dx.doi.org/10.1109/tcad.2017.2695899.

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Bruno, Alessandro, Fabrizio Pisacane, and Vittorio Rosato. "Simulation of a Two-Dimensional Dipolar System on a APE100/Quadrics Simd Architecture." International Journal of Modern Physics C 08, no. 03 (1997): 459–72. http://dx.doi.org/10.1142/s0129183197000382.

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The temperature behavior of a system of dipoles with long-range interactions has been simulated via a two-dimensional lattice Monte Carlo on a massively SIMD platform (Quadrics/APE100). Thermodynamic quantities have been evaluated in order to locate and to characterize the phase transition in absence of applied field. Emphasis is given to the code implementation on the SIMD architecture and to the relevant features which have been used to improve code capabilities and performances.
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ZIPPEL, RICHARD. "THE DATA STRUCTURE ACCELERATOR ARCHITECTURE." International Journal of High Speed Electronics and Systems 07, no. 04 (1996): 533–71. http://dx.doi.org/10.1142/s012915649600030x.

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We present a heterogeneous architecture that contains a fine grained, massively parallel SIMD component called the data structure accelerator and demonstrate its use in a number of problems in computational geometry including polygon filling and convex hull. The data structure accelerator is extremely dense and highly scalable. Systems of 106 processing elements can be embedded in workstations and personal computers, without dramatically changing their cost. These components are intended for use in tandem with conventional single sequence machines and with small scale, shared memory multiprocessors. A language for programming these heterogeneous systems is presented that smoothly incorporates the SIMD instructions of the data structure accelerator with conventional single sequence code. We then demonstrate how to construct a number of higher level primitives such as maximum and minimum, and apply these tools to problems in logic and computational geometry. For computational geometry problems, we demonstrate that simple algorithms that take advantage of the parallelism available on a data structure accelerator perform as well or better than the far more complex algorithms which are needed for comparable efficiency on single sequence computers.
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BHANDARKAR, SUCHENDRA M., HAMID R. ARABNIA, and JEFFREY W. SMITH. "A RECONFIGURABLE ARCHITECTURE FOR IMAGE PROCESSING AND COMPUTER VISION." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 201–29. http://dx.doi.org/10.1142/s0218001495000110.

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In this paper we describe a reconfigurable architecture for image processing and computer vision based on a multi-ring network which we call a Reconfigurable Multi-Ring System (RMRS). We describe the reconfiguration switch for the RMRS and also describe its VLSI implementation. The RMRS topology is shown to be regular and scalable and hence well-suited for VLSI implementation. We prove some important properties of the RMRS topology and show that a broad class of algorithms for the n-cube can be mapped to the RMRS in a simple and elegant manner. We design and analyze a class of procedural primitives for the SIMD RMRS and show how these primitives can be used as building blocks for more complex parallel operations. We demonstrate the usefulness of the RMRS for problems in image processing and computer vision by considering two important operations—the Fast Fourier Transform (FFT) and the Hough transform for detection of linear features in an image. Parallel algorithms for the FFT and the Hough transform on the SIMD RMRS are designed using the aforementioned procedural primitives. The analysis of the complexity of these algorithms shows that the SIMD RMRS is a viable architecture for problems in computer vision and image processing.
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Moudgill, Mayan, Andrei Iancu, and Daniel Iancu. "Galois Field Instructions in the Sandblaster 2.0 Architectrue." International Journal of Digital Multimedia Broadcasting 2009 (2009): 1–5. http://dx.doi.org/10.1155/2009/129698.

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This paper presents a novel approach to implementing multiplication of Galois Fields with . Elements of GF() can be represented as polynomials of degree less than N over GF(2). Operations are performed modulo an irreducible polynomial of degree n over GF(2). Our approach splits a Galois Field multiply into two operations, polynomial-multiply and polynomial-remainder over GF(2). We show how these two operations can be implemented using the same hardware. Further, we show that in many cases several polynomial-multiply operations can be combined before needing to a polynomial-remainder. The Sandblaster 2.0 is a SIMD architecture. It has SIMD variants of the poly-multiply and poly-remainder instructions. We use a Reed-Solomon encoder and decoder to demonstrate the performance of our approach. Our new approach achieves speedup of 11.5x compared to the standard SIMD processor of 8x.
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Dissertations / Theses on the topic "SIMD architecture"

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Chung, Kee Shik. "ILP-SIMD : an instruction parallel SIMD architecture with short-wire interconnects." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15455.

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Andersson, Johan, Mikael Mohlin, and Artur Nilsson. "A reconfigurable SIMD architecture on-chip." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-291.

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<p>This project targets the problems with design and implementation of Single Instruction </p><p>Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct </p><p>a reconfigurable framework in VHDL to ease this process. The resulting framework should </p><p>be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- </p><p>tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and </p><p>the Interconnection Network (ICN), and a framework was constructed with these parts </p><p>as the main building blocks. The constructed framework is reconfigurable in data width, </p><p>memory size, number of PEs, topology and instruction set. To test ease of use and per- </p><p>formance of the system a FIR-filter application was implemented. The scalability of the </p><p>system and its different parts has been measured and comparisons are illustrated.</p>
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Bergach, Mohamed Amine. "Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée." Thesis, Nice, 2015. http://www.theses.fr/2015NICE4060/document.

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Les architectures multi-cœurs Intel Core (IvyBridge, Haswell,...) contiennent à la fois des cœurs CPU généralistes (4), mais aussi des cœurs dédiés GPU embarqués sur cette même puce (16 et 40 respectivement). Dans le cadre de l'activité de la société Kontron (qui participe à ce financement de nature CIFRE) un objectif important est de calculer efficacement sur cette architecture des tableaux et séquences de transformées de Fourier rapides (FFT), comme par exemple on en trouve dans des applications radar. Alors que des bibliothèques natives (mais propriétaires) existent chez Intel pour les CPU, rien de tel n'est actuellement disponible pour la partie GPU. L'objectif de la thèse était donc de définir le placement efficace de modules FFT, en étudiant au niveau théorique la forme optimale permettant de regrouper des étages de calcul d'une telle FFT en fonction de la localité des données sur un cœur de calcul unique. Ce choix a priori permet d'espérer une efficacité des traitements, en ajustant la taille de la mémoire disponible à celles des données nécessaires. Ensuite la multiplicité des cœurs reste exploitable pour disposer plusieurs FFT calculées en parallèle, sans interférence (sauf contention du bus entre CPU et GPU). Nous avons obtenu des résultats significatifs, tant au niveau de l'implantation d'une FFT (1024 points) sur un cœur CPU SIMD, exprimée en langage C, que pour l'implantation d'une FFT de même taille sur un cœur GPU SIMT, exprimée alors en OpenCL. De plus nos résultats permettent de définir des règles pour synthétiser automatiquement de telles solutions, en fonction uniquement de la taille de la FFT son nombre d'étages plus précisément), et de la taille de la mémoire locale pour un coeur de calcul donné. Les performances obtenues sont supérieures à celles de la bibliothèque native Intel pour CPU), et démontrent un gain important de consommation sur GPU. Tous ces points sont détaillés dans le document de thèse. Ces résultats devraient donner lieu à exploitation au sein de la société Kontron<br>Multicore architectures Intel Core (IvyBridge, Haswell…) contain both general purpose CPU cores (4) and dedicated GPU cores embedded on the same chip (16 and 40 respectively). As part of the activity of Kontron (the company partially funding this CIFRE scholarship), an important objective is to efficiently compute arrays and sequences of fast Fourier transforms (FFT) such as one finds in radar applications, on this architecture. While native (but proprietary) libraries exist for Intel CPU, nothing is currently available for the GPU part.The aim of the thesis was to define the efficient placement of FFT modules, and to study theoretically the optimal form for grouping computing stages of such FFT according to data locality on a single computing core. This choice should allow processing efficiency, by adjusting the memory size available to the required application data size. Then the multiplicity of cores is exploitable to compute several FFT in parallel, without interference (except for possible bus contention between the CPU and the GPU). We have achieved significant results, both in the implementation of an FFT (1024 points) on a SIMD CPU core, expressed in C, and in the implementation of a FFT of the same size on a GPU SIMT core, then expressed in OpenCL. In addition, our results allow to define rules to automatically synthesize such solutions, based solely on the size of the FFT (more specifically its number of stages), and the size of the local memory for a given computing core. The performances obtained are better than the native Intel library for CPU, and demonstrate a significant gain in consumption on GPU. All these points are detailed in the thesis document
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Choi, Jee W. "Reducing Communication Through Buffers on a SIMD Architecture." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4970.

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Advances in wireless technology and the growing popularity of multimedia applications have brought about a need for energy efficient and cost effective portable supercomputers capable of delivering performance beyond the capabilities of current microprocessors and DSP chips. The SIMPil architecture currently being developed at Georgia Institute of Technology is a promising candidate for this task. In order to develop applications for SIMPil, a high level language and an optimizing compiler for the language are essential. However, with the recent trend of interconnect latency becoming a major bottleneck on computer systems, optimizations focusing on reducing latency are becoming more important, especially with SIMPil, as it is highly scalable. The compiler tracks the path of data through the network and buffers data in each processor to eliminate redundant communication. With a buffer size of 5, the compiler was able to eliminate 96 percent of the redundant communication for a 9x9 convolution and 8x8 DCT algorithms. With 5x5 convolution, only 89 percent elimination was observed. In terms of performance, 106 percent speedup was observed with 9x9 convolution at buffer size of 5 while 5x5 convolution and 8x8 DCT which have a much lower number of communication showed only 101 percent speedup.
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Kerbyson, Darren James. "A multiple-SIMD architecture for image and tracking analysis." Thesis, University of Warwick, 1992. http://wrap.warwick.ac.uk/80185/.

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The computational requirements for real-time image based applications are such as to warrant the use of a parallel architecture. Commonly used parallel architectures conform to the classifications of Single Instruction Multiple Data (SIMD), or Multiple Instruction Multiple Data (MIMD). Each class of architecture has its advantages and dis-advantages. For example, SIMD architectures can be used on data-parallel problems, such as the processing of an image. Whereas MIMD architectures are more flexible and better suited to general purpose computing. Both types of processing are typically required for the analysis of the contents of an image. This thesis describes a novel massively parallel heterogeneous architecture, implemented as the Warwick Pyramid Machine. Both SIMD and MIMD processor types are combined within this architecture. Furthermore, the SIMD array is partitioned, into smaller SIMD sub-arrays, forming a Multiple-SIMD array. Thus, local data parallel, global data parallel, and control parallel processing are supported. After describing the present options available in the design of massively parallel machines and the nature of the image analysis problem, the architecture of the Warwick Pyramid Machine is described in some detail. The performance of this architecture is then analysed, both in terms of peak available computational power and in terms of representative applications in image analysis and numerical computation. Two tracking applications are also analysed to show the performance of this architecture. In addition, they illustrate the possible partitioning of applications between the SIMD and MIMD processor arrays. Load-balancing techniques are then described which have the potential to increase the utilisation of the Warwick Pyramid Machine at run-time. These include mapping techniques for image regions across the Multiple-SIMD arrays, and for the compression of sparse data. It is envisaged that these techniques may be found useful in other parallel systems.
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Allen, James D. "System level design issues for high performance SIMD architectures." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15406.

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Robert, Yves Robert François. "Algorithmique parallèle réseaux d'automates, architectures systoliques, machines SIMD et MIMD /." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00319876.

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Robert, Yves. "Algorithmique parallèle : réseaux d'automates, architectures systoliques, machines SIMD et MIMD." Habilitation à diriger des recherches, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00319876.

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Kalathingal, Sajith. "Transforming TLP into DLP with the dynamic inter-thread vectorization architecture." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S133/document.

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De nombreux microprocesseurs modernes mettent en œuvre le multi-threading simultané (SMT) pour améliorer l'efficacité globale des processeurs superscalaires. SMT masque les opérations à longue latence en exécutant les instructions de plusieurs threads simultanément. Lorsque les threads exécutent le même programme (cas des applications SPMD), les mêmes instructions sont souvent exécutées avec des entrées différentes. Les architectures SMT traditionnelles exploitent le parallélisme entre threads, ainsi que du parallélisme de données explicite au travers d'unités d'exécution SIMD. L'exécution SIMD est efficace en énergie car le nombre total d'instructions nécessaire pour exécuter un programme est significativement réduit. Cette réduction du nombre d'instructions est fonction de la largeur des unités SIMD et de l'efficacité de la vectorisation. L'efficacité de la vectorisation est cependant souvent limitée en pratique. Dans cette thèse, nous proposons l'architecture de vectorisation dynamique inter-thread (DITVA) pour tirer parti du parallélisme de données implicite des applications SPMD en assemblant dynamiquement des instructions vectorielles à l'exécution. DITVA augmente un processeur à exécution dans l'ordre doté d'unités SIMD en lui ajoutant un mode d'exécution vectorisant entre threads. Lorsque les threads exécutent les mêmes instructions simultanément, DITVA vectorise dynamiquement ces instructions pour assembler des instructions SIMD entre threads. Les threads synchronisés sur le même chemin d'exécution partagent le même flot d'instructions. Pour conserver du parallélisme de threads, DITVA groupe de manière statique les threads en warps ordonnancés indépendamment. DITVA tire parti des unités SIMD existantes et maintient la compatibilité binaire avec les architectures CPU existantes<br>Many modern microprocessors implement Simultaneous Multi-Threading (SMT) to improve the overall efficiency of superscalar CPU. SMT hides long latency operations by executing instructions from multiple threads simultaneously. SMT may execute threads of different processes, threads of the same processes or any combination of them. When the threads are from the same process, they often execute the same instructions with different data most of the time, especially in the case of Single-Program Multiple Data (SPMD) applications.Traditional SMT architecture exploit thread-level parallelism and with the use of SIMD execution units, they also support explicit data-level parallelism. SIMD execution is power efficient as the total number of instructions required to execute a complete program is significantly reduced. This instruction reduction is a factor of the width of SIMD execution units and the vectorization efficiency. Static vectorization efficiency depends on the programmer skill and the compiler. Often, the programs are not optimized for vectorization and hence it results in inefficient static vectorization by the compiler.In this thesis, we propose the Dynamic Inter-Thread vectorization Architecture (DITVA) to leverage the implicit data-level parallelism in SPMD applications by assembling dynamic vector instructions at runtime. DITVA optimizes an SIMD-enabled in-order SMT processor with inter-thread vectorization execution mode. When the threads are running in lockstep, similar instructions across threads are dynamically vectorized to form a SIMD instruction. The threads in the convergent paths share an instruction stream. When all the threads are in the convergent path, there is only a single stream of instructions. To optimize the performance in such cases, DITVA statically groups threads into fixed-size independently scheduled warps. DITVA leverages existing SIMD units and maintains binary compatibility with existing CPU architectures
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Duclos, Pierre. "Etude du parallélisme en traitement des images réalisations sur une architecture mixte SIMD/SPMD /." Grenoble 2 : ANRT, 1988. http://catalogue.bnf.fr/ark:/12148/cb37613253f.

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Books on the topic "SIMD architecture"

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Hord, R. Michael. Parallel supercomputing in SIMD architectures. CRC Press, 1990.

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Cypher, Robert. The SIMD model of parallel computation. Springer-Verlag, 1994.

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Kerbyson, Darren James. A multiple-SIMD architecture for image and tracking analysis. typescript, 1992.

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Tomboulian, Sherryl. Indirect addressing and load balancing for faster solution to Mandelbrot Set on SIMD architectures. ICASE, 1989.

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Rigoutsos, Isidore. Scalable parallel geometric hashing for hypercube SIMD architectures. Courant Institute of Mathematical Sciences, New York University, 1991.

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Society for Information Management (U.S.), ed. The SIM guide to enterprise architecture. Taylor & Francis, 2010.

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Tomboulian, Sherryl. A system for routing arbitrary directed graphs on SIMD architectures. ICASE, 1987.

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Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, 1994.

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Hennessy, John L. Computer organization and design: The hardware/software interface. Morgan Kaufmann, 1994.

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Hennessy, John L. Computer organization and design: The hardware/software interface. Morgan Kaufmann Publishers, 1994.

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Book chapters on the topic "SIMD architecture"

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Kusswurm, Daniel. "X86-64 SIMD Architecture." In Modern X86 Assembly Language Programming. Apress, 2014. http://dx.doi.org/10.1007/978-1-4842-0064-3_19.

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Kusswurm, Daniel. "Armv8-32 SIMD Architecture." In Modern Arm Assembly Language Programming. Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-6267-2_7.

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Nowinski, Wieslaw L. "A SIMD architecture for medical imaging." In Parallel Processing: CONPAR 92—VAPP V. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55895-0_412.

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Vitabile, Salvatore, Antonio Gentile, G. B. Dammone, and Filippo Sorbello. "MLP Neural Network Implementation on a SIMD Architecture." In Neural Nets. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45808-5_10.

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Payá-Vayá, Guillermo, Javier Martín-Langerwerf, Sören Moch, and Peter Pirsch. "An Enhanced DMA Controller in SIMD Processors for Video Applications." In Architecture of Computing Systems – ARCS 2009. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00454-4_17.

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Neschen, Martin, and Martin Gumm. "A scalable bit-sequential SIMD architecture for pattern recognition." In PARLE'94 Parallel Architectures and Languages Europe. Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/3-540-58184-7_154.

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Vervisch, L., J. Réveillon, S. Melen, and D. Vandromme. "Turbulent combustion modeling using complex chemistry on SIMD architecture." In Computational Fluid Dynamics on Parallel Systems. Vieweg+Teubner Verlag, 1995. http://dx.doi.org/10.1007/978-3-322-89454-0_18.

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Kim, Jongmyon, D. Scott Wills, and Linda M. Wills. "Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_45.

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Abu-Ghazaleh, Nael B., and Philip A. Wilsey. "Shared control — Supporting control parallelism using a SIMD-like architecture." In Euro-Par’98 Parallel Processing. Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0057970.

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Nicastro, S., and F. Valentinotti. "Parallel implementation of a meteorological model on a SIMD architecture." In High-Performance Computing and Networking. Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0037142.

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Conference papers on the topic "SIMD architecture"

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Clark, Nathan, Amir Hormati, Sami Yehia, Scott Mahlke, and Krisztian Flautner. "Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping." In 2007 IEEE 13th International Symposium on High Performance Computer Architecture. IEEE, 2007. http://dx.doi.org/10.1109/hpca.2007.346199.

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Yaohua Wang, Shuming Chen, Jianghua Wan, et al. "A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments." In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013. http://dx.doi.org/10.1109/hpca.2013.6522353.

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Liu, Yingying, Dake Liu, and Wei Wang. "IIR parallelization on multi-datapath SIMD architecture." In 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016. http://dx.doi.org/10.1109/icam.2016.7813619.

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Pandya, Abhijit S., Ravi T. Sankar, and Lynn Freytag. "SIMD architecture for the Alopex neural network." In SC - DL tentative, edited by Joydeep Ghosh and Colin G. Harrison. SPIE, 1990. http://dx.doi.org/10.1117/12.19587.

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Khorasani, Farzad, Rajiv Gupta, and Laxmi N. Bhuyan. "Scalable SIMD-Efficient Graph Processing on GPUs." In 2015 International Conference on Parallel Architecture and Compilation (PACT). IEEE, 2015. http://dx.doi.org/10.1109/pact.2015.15.

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Wu, Chen, Hamid Aghajan, and Richard Kleihorst. "Mapping Vision Algorithms on SIMD Architecture Smart Cameras." In 2007 First ACM/IEEE International Conference on Distributed Smart Cameras. IEEE, 2007. http://dx.doi.org/10.1109/icdsc.2007.4357502.

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Zhang, Weihua, Xinglong Qian, Ye Wang, Binyu Zang, and Chuanqi Zhu. "Optimizing compiler for shared-memory multiple SIMD architecture." In the 2006 ACM SIGPLAN/SIGBED conference. ACM Press, 2006. http://dx.doi.org/10.1145/1134650.1134679.

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Chiu, Jih-Ching, Yu-Liang Chou, and Hua-Yi Tzeng. "A multi-streaming SIMD architecture for multimedia applications." In the 6th ACM conference. ACM Press, 2009. http://dx.doi.org/10.1145/1531743.1531753.

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Azeemi, Naeem Z., A. Sultan, and A. Arshad Muhammad. "Parameterized Characterization of Bioinfomatics Workload on SIMD Architecture." In 2006 International Conference on Information and Automation. IEEE, 2006. http://dx.doi.org/10.1109/icinfa.2006.374110.

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Patwardhan, Jaidev P., Vijeta Johri, Chris Dwyer, and Alvin R. Lebeck. "A defect tolerant self-organizing nanoscale SIMD architecture." In the 12th international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1168857.1168888.

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Reports on the topic "SIMD architecture"

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Barkmeyer, Edward J., Neil Christopher, Shaw C. Feng, et al. SIMA reference architecture, part 1:. National Institute of Standards and Technology, 1996. http://dx.doi.org/10.6028/nist.ir.5939.

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