Relevant bibliographies by topics / SIMD array architectures

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'SIMD array architectures'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "SIMD array architectures"

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NARAYANAN, P. J., and LARRY S. DAVIS. "REPLICATED IMAGE ALGORITHMS AND THEIR ANALYSES ON SIMD MACHINES." International Journal of Pattern Recognition and Artificial Intelligence 06, no. 02n03 (1992): 335–52. http://dx.doi.org/10.1142/s0218001492000217.

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Data parallel processing on processor array architectures has gained popularity in data intensive applications, such as image processing and scientific computing, as massively parallel processor array machines became feasible commercially. The data parallel paradigm of assigning one processing element to each data element results in an inefficient utilization of a large processor array when a relatively small data structure is processed on it. The large degree of parallelism of a massively parallel processor array machine does not result in a faster solution to a problem involving relatively s
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SZYMANSKI, BOLESLAW K., WILLIAM MANIATTY, and BALARAM SINHAROY. "SIMULTANEOUS PARALLEL REDUCTION ON SIMD MACHINES." Parallel Processing Letters 05, no. 03 (1995): 437–49. http://dx.doi.org/10.1142/s0129626495000400.

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Proper distribution of operations among parallel processors in a large scientific computation executed on a distributed-memory machine can significantly reduce the total computation time. In this paper, we propose an operation called simultaneous parallel reduction(SPR), that is amenable to such optimization. SPR performs reduction operations in parallel, each operation reducing a one-dimensional consecutive section of a distributed array. Each element of the distributed array is used as an operand to many reductions executed concurrently over the overlapping array's sections. SPR is distinct
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AL-RABADI, ANAS N. "REVERSIBLE SYSTOLIC ARRAYS: m-ARY BIJECTIVE SINGLE-INSTRUCTION MULTIPLE-DATA (SIMD) ARCHITECTURES AND THEIR QUANTUM CIRCUITS." Journal of Circuits, Systems and Computers 17, no. 04 (2008): 729–71. http://dx.doi.org/10.1142/s0218126608004472.

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New type of m-ary systolic arrays called reversible systolic arrays is introduced in this paper. The m-ary quantum systolic architectures' realizations and computations of the new type of systolic arrays are also introduced. A systolic array is an example of a single-instruction multiple-data (SIMD) machine in which each processing element (PE) performs a single simple operation. Systolic devices provide inexpensive but massive computation power, and are cost-effective, high-performance, and special-purpose systems that have wide range of applications such as in solving several regular and com
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Philipov, Ph, and V. Lazarov. "Investigation of the Indirect Hypercube as Natural Architecture for Parallel Algorithms of a Transpose Type for FFT and Other Fourier-Related Transforms." Information Technologies and Control 11, no. 2 (2014): 29–44. http://dx.doi.org/10.2478/itc-2013-0010.

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Abstract The natural architectures are architectures, derived from the signal graph of the corresponding algorithm. That is why they are considered to be the most appropriate architectures for parallel realization of this algorithm. For Fast Fourier Transform algorithm (FFT) two types of natural architectures are known – the direct and the indirect hypercube. The direct hypercube has been investigated and analyzed a long time ago. The development of the concept of Indirect Hypercube, although quite old, is too difficult, controversal and still unfinished. Fast Hartley transform (FHT)/Real-valu
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Drabik, Timothy J., and Sing H. Lee. "Shift-connected SIMD array architectures for digital optical computing systems, with algorithms for numerical transforms and partial differential equations." Applied Optics 25, no. 22 (1986): 4053. http://dx.doi.org/10.1364/ao.25.004053.

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FUJITA, YOSHIHIRO, NOBUYUKI YAMASHITA, and SHIN-ICHIRO OKAZAKI. "IMAP: INTEGRATED MEMORY ARRAY PROCESSOR." Journal of Circuits, Systems and Computers 02, no. 03 (1992): 227–45. http://dx.doi.org/10.1142/s0218126692000155.

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This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this pa
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Miller, P. R., M. Zwolinski, and C. R. Jesshope. "Using Ella as a Design Tool." International Journal of Electrical Engineering & Education 26, no. 1-2 (1989): 134–45. http://dx.doi.org/10.1177/002072098902600120.

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An overview of the ELLA system is given, followed by a description of how it has been used as an architectural tool to develop packet-switching networks for SIMD processor arrays. Finally, the merits and drawbacks of ELLA are discussed, with a summary on current trends in automated design.
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FEIL, MANFRED, ANDREAS UHL, and MARIAN VAJTERŠIC. "COMPUTATION OF THE CONTINUOUS WAVELET TRANSFORM ON MASSIVELY PARALLEL SIMD ARRAYS." Parallel Processing Letters 09, no. 04 (1999): 453–66. http://dx.doi.org/10.1142/s0129626499000426.

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Strategies for computing the continuous wavelet transform on massively parallel SIMD arrays are introduced and discussed. The different approaches are theoretically assessed and the results of implementations on a MasPar MP-2 are compared.
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R, Maheswari, Pattabiraman V, and Sharmila P. "RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 180. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19632.

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Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF
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Herbordt, Martin C., Jade Cravy, and Honghai Zhang. "Array control for high-performance SIMD systems." Journal of Parallel and Distributed Computing 64, no. 3 (2004): 400–413. http://dx.doi.org/10.1016/j.jpdc.2003.09.007.

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Dissertations / Theses on the topic "SIMD array architectures"

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Ekström, Mikael, and Martin Westerberg. "Implementation study of radar signal processing Using SIMD architectures." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-284.

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<p>The aim of this pro ject was to evaluate the use of SIMD array architectures in radar </p><p>signal processing. This has been done by implementing one of the most demanding parts </p><p>of the radar signal processing chain for airborne radar on the CSX600 architecture devel- </p><p>oped by Clearspeed Technologies. The CSX600 architecture is a SIMD processor with 96 </p><p>processing elements which can be arranged either as a linera array or as a ring. The QR- </p><p>decomposition, which was the part chosen for implementation, is the most performance </p><p>demanding part of the STAP stage.
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Goshi, Darren S. "Advanced retrodirective array and phased array architectures for wireless communication systems." Diss., Restricted to subscribing institutions, 2007. http://proquest.umi.com/pqdweb?did=1414125501&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Boubekeur, Ahmed. "Conception d'architectures intégrées de traitement d'image de bas niveau." Phd thesis, Grenoble INPG, 1992. http://tel.archives-ouvertes.fr/tel-00341394.

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Poonnen, Thomas. "Efficient VLSI divide and conquer array architectures for multiplication." 2007. http://proquest.umi.com/pqdweb?did=1397913401&sid=2&Fmt=2&clientId=39334&RQT=309&VName=PQD.

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Thesis (Ph.D.)--State University of New York at Buffalo, 2007.<br>Title from PDF title page (viewed on Feb. 28, 2008) Available through UMI ProQuest Digital Dissertations. Thesis adviser: Fam, Adly T. Includes bibliographical references.
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Book chapters on the topic "SIMD array architectures"

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Duff, M. J. B. "Architectures of SIMD Cellular Logic Image Processing Arrays." In Computer Architectures for Spatially Distributed Data. Springer Berlin Heidelberg, 1985. http://dx.doi.org/10.1007/978-3-642-82150-9_2.

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Chu, Xuezheng, John McAllister, and Roger Woods. "A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19475-7_16.

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Conference papers on the topic "SIMD array architectures"

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Lopich, Alexey, and Piotr Dudek. "Global operations in SIMD cellular processor arrays employing functional asynchronism." In CAMPS 2006. International Workshop on Computer Architecture for Machine Perception and Sensing. IEEE, 2006. http://dx.doi.org/10.1109/camp.2007.4350343.

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Tsai, Alex, David Tucker, and Craig Groves. "Improved Controller Performance of Selected Hybrid SOFC-GT Plant Signals Based on Practical Control Schemes." In ASME Turbo Expo 2010: Power for Land, Sea, and Air. ASMEDC, 2010. http://dx.doi.org/10.1115/gt2010-22470.

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This paper compares and demonstrates the efficacy of implementing two practical Single Input Single Output (SISO) multi-loop control schemes on the dynamic performance of selected signals of a Solid Oxide Fuel Cell Gas Turbine (SOFC-GT) hybrid simulation facility. The hybrid plant, located at the U.S. Department of Energy National Energy Technology Laboratory (NETL) in Morgantown WV, is capable of simulating the interaction between a 350kW SOFC and a 120kW GT using a Hardware-in-the-Loop (HIL) configuration. Previous studies have shown that the thermal management of coal based SOFC-GT hybrid s
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