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Journal articles on the topic 'SIMD array architectures'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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1

NARAYANAN, P. J., and LARRY S. DAVIS. "REPLICATED IMAGE ALGORITHMS AND THEIR ANALYSES ON SIMD MACHINES." International Journal of Pattern Recognition and Artificial Intelligence 06, no. 02n03 (1992): 335–52. http://dx.doi.org/10.1142/s0218001492000217.

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Data parallel processing on processor array architectures has gained popularity in data intensive applications, such as image processing and scientific computing, as massively parallel processor array machines became feasible commercially. The data parallel paradigm of assigning one processing element to each data element results in an inefficient utilization of a large processor array when a relatively small data structure is processed on it. The large degree of parallelism of a massively parallel processor array machine does not result in a faster solution to a problem involving relatively s
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2

SZYMANSKI, BOLESLAW K., WILLIAM MANIATTY, and BALARAM SINHAROY. "SIMULTANEOUS PARALLEL REDUCTION ON SIMD MACHINES." Parallel Processing Letters 05, no. 03 (1995): 437–49. http://dx.doi.org/10.1142/s0129626495000400.

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Proper distribution of operations among parallel processors in a large scientific computation executed on a distributed-memory machine can significantly reduce the total computation time. In this paper, we propose an operation called simultaneous parallel reduction(SPR), that is amenable to such optimization. SPR performs reduction operations in parallel, each operation reducing a one-dimensional consecutive section of a distributed array. Each element of the distributed array is used as an operand to many reductions executed concurrently over the overlapping array's sections. SPR is distinct
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3

AL-RABADI, ANAS N. "REVERSIBLE SYSTOLIC ARRAYS: m-ARY BIJECTIVE SINGLE-INSTRUCTION MULTIPLE-DATA (SIMD) ARCHITECTURES AND THEIR QUANTUM CIRCUITS." Journal of Circuits, Systems and Computers 17, no. 04 (2008): 729–71. http://dx.doi.org/10.1142/s0218126608004472.

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New type of m-ary systolic arrays called reversible systolic arrays is introduced in this paper. The m-ary quantum systolic architectures' realizations and computations of the new type of systolic arrays are also introduced. A systolic array is an example of a single-instruction multiple-data (SIMD) machine in which each processing element (PE) performs a single simple operation. Systolic devices provide inexpensive but massive computation power, and are cost-effective, high-performance, and special-purpose systems that have wide range of applications such as in solving several regular and com
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4

Philipov, Ph, and V. Lazarov. "Investigation of the Indirect Hypercube as Natural Architecture for Parallel Algorithms of a Transpose Type for FFT and Other Fourier-Related Transforms." Information Technologies and Control 11, no. 2 (2014): 29–44. http://dx.doi.org/10.2478/itc-2013-0010.

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Abstract The natural architectures are architectures, derived from the signal graph of the corresponding algorithm. That is why they are considered to be the most appropriate architectures for parallel realization of this algorithm. For Fast Fourier Transform algorithm (FFT) two types of natural architectures are known – the direct and the indirect hypercube. The direct hypercube has been investigated and analyzed a long time ago. The development of the concept of Indirect Hypercube, although quite old, is too difficult, controversal and still unfinished. Fast Hartley transform (FHT)/Real-valu
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5

Drabik, Timothy J., and Sing H. Lee. "Shift-connected SIMD array architectures for digital optical computing systems, with algorithms for numerical transforms and partial differential equations." Applied Optics 25, no. 22 (1986): 4053. http://dx.doi.org/10.1364/ao.25.004053.

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6

FUJITA, YOSHIHIRO, NOBUYUKI YAMASHITA, and SHIN-ICHIRO OKAZAKI. "IMAP: INTEGRATED MEMORY ARRAY PROCESSOR." Journal of Circuits, Systems and Computers 02, no. 03 (1992): 227–45. http://dx.doi.org/10.1142/s0218126692000155.

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This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this pa
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7

Miller, P. R., M. Zwolinski, and C. R. Jesshope. "Using Ella as a Design Tool." International Journal of Electrical Engineering & Education 26, no. 1-2 (1989): 134–45. http://dx.doi.org/10.1177/002072098902600120.

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An overview of the ELLA system is given, followed by a description of how it has been used as an architectural tool to develop packet-switching networks for SIMD processor arrays. Finally, the merits and drawbacks of ELLA are discussed, with a summary on current trends in automated design.
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8

FEIL, MANFRED, ANDREAS UHL, and MARIAN VAJTERŠIC. "COMPUTATION OF THE CONTINUOUS WAVELET TRANSFORM ON MASSIVELY PARALLEL SIMD ARRAYS." Parallel Processing Letters 09, no. 04 (1999): 453–66. http://dx.doi.org/10.1142/s0129626499000426.

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Strategies for computing the continuous wavelet transform on massively parallel SIMD arrays are introduced and discussed. The different approaches are theoretically assessed and the results of implementations on a MasPar MP-2 are compared.
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9

R, Maheswari, Pattabiraman V, and Sharmila P. "RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 180. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19632.

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Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF
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10

Herbordt, Martin C., Jade Cravy, and Honghai Zhang. "Array control for high-performance SIMD systems." Journal of Parallel and Distributed Computing 64, no. 3 (2004): 400–413. http://dx.doi.org/10.1016/j.jpdc.2003.09.007.

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11

Carey, Stephen J., David R. W. Barr, Bin Wang, Alexey Lopich, and Piotr Dudek. "Mixed signal SIMD processor array vision chip for real-time image processing." Analog Integrated Circuits and Signal Processing 77, no. 3 (2013): 385–99. http://dx.doi.org/10.1007/s10470-013-0192-x.

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12

Herbordt, Martin C., Jade Cravy, Renoy Sam, Owais Kidwai, and Calvin Lin. "A System for Evaluating Performance and Cost of SIMD Array Designs." Journal of Parallel and Distributed Computing 60, no. 2 (2000): 217–46. http://dx.doi.org/10.1006/jpdc.1999.1602.

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13

Umeo, Hiroshi. "A class of SIMD machines simulated by systolic arrays." Journal of Parallel and Distributed Computing 2, no. 4 (1985): 391–403. http://dx.doi.org/10.1016/0743-7315(85)90022-x.

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14

Pieper, Andreas, Georg Hager, and Holger Fehske. "A domain-specific language and matrix-free stencil code for investigating electronic properties of Dirac and topological materials." International Journal of High Performance Computing Applications 35, no. 1 (2020): 60–77. http://dx.doi.org/10.1177/1094342020959423.

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We introduce PVSC-DTM (Parallel Vectorized Stencil Code for Dirac and Topological Materials), a library and code generator based on a domain-specific language tailored to implement the specific stencil-like algorithms that can describe Dirac and topological materials such as graphene and topological insulators in a matrix-free way. The generated hybrid-parallel (MPI+OpenMP) code is fully vectorized using Single Instruction Multiple Data (SIMD) extensions. It is significantly faster than matrix-based approaches on the node level and performs in accordance with the roofline model. We demonstrate
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15

MIYAKOSHI, J., Y. MURACHI, T. MATSUNO, et al. "A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (2006): 3623–33. http://dx.doi.org/10.1093/ietfec/e89-a.12.3623.

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16

Burmester, C. P., L. T. Wille, and R. Gronsky. "Monte Carlo Simulations on SIMD Computer Architectures." MRS Proceedings 278 (1992). http://dx.doi.org/10.1557/proc-278-3.

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AbstractAlgorithmic considerations regarding the implementation of various materials science applications of the Monte Carlo technique to single instruction multiple data (SIMD) computer architectures are presented. In particular, implementation of the Ising model with nearest, next nearest. and long range screened Coulomb interactions on the SIMD architecture MasPar MP-1 (DEC mpp-12000) series of massively parallel computers is demonstrated. Methods of code development which optimize processor array use and minimize inter-processor communication are presented including lattice partitioning an
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17

"Scientific computation on SIMD and MIMD machines." Philosophical Transactions of the Royal Society of London. Series A, Mathematical and Physical Sciences 326, no. 1591 (1988): 481–98. http://dx.doi.org/10.1098/rsta.1988.0099.

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The ICL Distributed Array Processor and the Meiko Computing Surface have been successfully applied to a wide range of scientific problems. I give an overview of selected applications from experimental data analysis, molecular dynamics and Monte Carlo simulation, cellular automata for fluid flow, neural network models, protein sequencing and NMR imaging. I expose the problems and advantages of implementations on the two architectures, and discuss the general conclusions which one can draw from experience so far.
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