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Journal articles on the topic 'Simulation de spectre'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

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1

Peikert, T., J. K. Bremer, and W. Mathis. "Modellierungskonzept für MOS Varaktoren zur Minimierung der AM-FM Konversion in VCOs." Advances in Radio Science 8 (October 1, 2010): 143–49. http://dx.doi.org/10.5194/ars-8-143-2010.

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Abstract. In dieser Arbeit wird ein analytisches Simulationsmodell für MOS Varaktoren zur Entwurfsunterstützung von integrierten CMOS LC-Tank VCO-Schaltungen präsentiert. Das analytische Simulationsmodell wurde auf Basis des EKV-Transistormodells implementiert und beinhaltet ausschließlich Design- und Prozessparameter für die Berechnung der Varaktorkapazität. Dieses Simulationsmodell ermöglicht es, die verwendeten Varaktoren im Vorfeld des VCO-Entwurfs zu dimensionieren, die effektive Großsignalkapazität in Abhängigkeit des Ausgangssignals zu berechnen und einzelne Eigenschaften der Varaktoren

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2

Hussey, Andrew. "Spectacle, Simulation and Spectre: Debord, Baudrillard and the ghost of Marx." Parallax 7, no. 3 (2001): 63–72. http://dx.doi.org/10.1080/13534640110064039.

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Teffahi, H., and S. Kherouf. "Effets du couplage source–conduit vocal sur le modèle à deux masses." Canadian Journal of Physics 88, no. 9 (2010): 657–62. http://dx.doi.org/10.1139/p10-047.

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Nous présentons une simulation de la source vocale, connue comme modèle à deux masses. Ce modèle simule le fonctionnement des cordes vocales humaines. Une étude qualitative des effets du couplage source–conduit sur la forme et le spectre de l’onde de débit de la glotte est entreprise. Cette simulation va permettre de mieux cerner le processus acoustique de production de la parole.

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ISLAM, SYED S., and A. F. M. ANWAR. "SPICE MODEL OF AlGaN/GaN HEMTs AND SIMULATION OF VCO AND POWER AMPLIFIER." International Journal of High Speed Electronics and Systems 14, no. 03 (2004): 853–59. http://dx.doi.org/10.1142/s0129156404002946.

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SPICE model parameters are extracted from reported experimental data. The model is implemented in the Cadence Affirma Analog Circuit Design Environment and Spectre simulator is used to simulate class-E power amplifier and ring voltage controlled oscillator (VCO) circuits. The availability of the SPICE model for GaN HEMTs ensures optimization of analog/RF circuits before an expensive cut-and-try method is employed.

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KANUNGO, JITENDRA, and S. DASGUPTA. "ENERGY ESTIMATION FOR n-INPUT ADIABATIC LOGIC GATE: A PROPOSED ANALYTICAL MODEL." Journal of Circuits, Systems and Computers 22, no. 05 (2013): 1350037. http://dx.doi.org/10.1142/s0218126613500370.

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In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic mor

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Mr. Nikhil Surkar, Ms. Shriya Timande. "Analysis of Analog to Digital Converter for Biomedical Applications." International Journal of New Practices in Management and Engineering 1, no. 03 (2012): 01–07. http://dx.doi.org/10.17762/ijnpme.v1i03.6.

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This paper presents an ADC which can be used for biomedical application like pacemaker. For the low-power operation, monotonic switching scheme and operating voltage reduction have been implemented in the design. The 10bit 1.8V rail-to-rail (SAR) ADC is realized using UMC 0.18µm CMOS process. Simulations are performed by spectre simulation. From static performance, offset error and full scale error are noticed. This performance issue can be corrected by reducing discharge in capacitor by implementing sampling switch as bootstrapped switch and proper selection of common-mode voltage where 20fF

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Descrettes, Victoria, Laure Boissel, Ingrid Vasselin, et al. "Troubles du spectre de l’autisme et simulation : un outil au service du soin." Enfances & Psy 80, no. 4 (2018): 152. http://dx.doi.org/10.3917/ep.080.0152.

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8

Kabouchi, B., C. Kenfack Assongo, and C. Cazeau-Dubroca. "Simulation théorique du spectre d'absorption UV du carbazole et de quelques molécules analogues." Spectrochimica Acta Part A: Molecular and Biomolecular Spectroscopy 57, no. 5 (2001): 1111–17. http://dx.doi.org/10.1016/s1386-1425(00)00430-3.

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9

Dumitru, Ion, and Anghel Cernescu. "Fatigue Crack Growth under Variable Amplitude Loadings: A Theoretical Study." Key Engineering Materials 399 (October 2008): 21–26. http://dx.doi.org/10.4028/www.scientific.net/kem.399.21.

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The purpose of this study was making evident the overload effect in a spectre with constant amplitude cycles. The crack growth simulation was made on cracked specimen and was studied for four loading cases. Fatigue crack growth rate was calculated applying NASGRO equation and the crack growth retardation analyzed.

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10

Takai, Nobukazu, Takashi Okada, Kenji Takahashi, et al. "Single Inductor Bipolar Outputs DC-DC Converter with Current Mode Control Circuit." Key Engineering Materials 534 (January 2013): 220–26. http://dx.doi.org/10.4028/www.scientific.net/kem.534.220.

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Mobile equipment such as organic-EL display, digital still camera and so on re-quire both positive and negative power supply voltage to obtain high quality. Single InductorMultiple-Output (SIMO) DC-DC converter can provide a pair of positive and negative outputvoltages with only one external inductor. This paper describes SIMO DC-DC Converter usingproposed current-mode control (CMC) circuit. The proposed CMC circuit realizes high responsespeed for the change of load current. Spectre simulations with 0.18m CMOS process parameterare performed to verify the validity of the proposed converter. The

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11

Cavalcanti, Hercílio M., and Leandro Manera. "A Simulation Methodology for Wirebonds Interconnects of Radiofrequency Integrated Circuits." Journal of Integrated Circuits and Systems 10, no. 3 (2015): 181–86. http://dx.doi.org/10.29292/jics.v10i3.421.

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This work presents a methodology for the simulation of bonding wires under the circumstance when signals with RF frequencies are employed and thus, the impedances of the parasitic resistances, capacitances and inductances of these interconnections are no longer negligible. A s-parameters extraction strategy for each of the wirebonds will be shown with the help of Agilent’s EM simulator ADS resulting in a netlist in spectre which will be used in the test-bench of the designed IC to emulate the behavior of the bondwires and thus making possible a proper dimensioning and tuning of the RF chip to

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12

Yang, Jian, Liang Liu, Qiu Ye Lv, Xiao Wei Liu, and Liang Yin. "A High-Order Sigma-Delta Modulator Applied in Micro-Accelerometer." Key Engineering Materials 609-610 (April 2014): 1266–70. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1266.

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In this paper a high-order sigma-delta modulator applied in micro-accelerometer is designed. The modulator chooses the distributed feedback structure. And the signal bandwidth is 500Hz, the oversampling ratio is 250 and sampling frequency is 250KHz. By the MATLAB Simulink simulation, when the input signal is 1g, and the signal frequency is 250Hz, the simulation result is that the noise level is-160dBV at the signal frequency in the ideal situation. And when considering the non-ideal factors, the simulation result shows that the noise level at the input accelerated signal is 20dBV higher than t

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13

Barboni, Leonardo. "Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors." Journal of Low Power Electronics and Applications 10, no. 2 (2020): 17. http://dx.doi.org/10.3390/jlpea10020017.

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The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no pre

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14

Guo, Min, Hong Hui Deng, Bo Wen Ding, and Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator." Applied Mechanics and Materials 644-650 (September 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of

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15

Kamal, A., and S. Bennis. "Effet d'échelle sur la simulation du ruissellement en milieu urbain." Revue des sciences de l'eau 18, no. 2 (2005): 225–46. http://dx.doi.org/10.7202/705558ar.

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Ce travail consiste en l’élaboration d’une méthodologie systématique qui permet de substituer une modélisation hydraulique simplifiée à une modélisation détaillée d’un réseau d’assainissement. L’approche préconisée est basée sur une analyse multi-paramètre du processus du drainage en milieu urbain. Les paramètres adimensionnels retenus dans cette analyse font intervenir les caractéristiques du bassin versant, les caractéristiques du réseau et celles de la pluie. Pour donner à cette approche un cadre plus général, les auteurs ont mené cette analyse sur des réseaux et des pluies synthétiques cou

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16

HEN-NGAM, NIKORN, and JIRAYUTH MAHATTANAKUL. "DERIVATION OF TRADE-OFF OF EQUATION FOR CMOS CROSS-COUPLED LC DIFFERENTIAL OSCILLATOR." Journal of Circuits, Systems and Computers 22, no. 09 (2013): 1340002. http://dx.doi.org/10.1142/s0218126613400021.

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This paper aims at presenting an equation describing a relation between power consumption and phase noise of the widely used CMOS cross-coupled LC differential oscillator. This equation is derived by using periodic time-varying method and it relates oscillator's key performance parameters, e.g., oscillation frequency and amplitude, sideband spectrum and bias current, and CMOS process parameters. The validity of the proposed equation was confirmed by the periodic noise simulation available in the Cadence's Virtuoso Spectre Circuit Simulator.

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17

Roberts, Michael, and Jess Ponting. "Waves of simulation: Arguing authenticity in an era of surfing the hyperreal." International Review for the Sociology of Sport 55, no. 2 (2018): 229–45. http://dx.doi.org/10.1177/1012690218791997.

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This article is an examination of the impact of new, technologically sophisticated wave pools upon the culture of surfers. Appropriating the concepts of simulation from the work of postmodern theorist Jean Baudrillard, and mechanical reproduction from the critical theorist Walter Benjamin, we consider how the spectre of perfectly simulated waves in controlled environments has signaled a new era in the history of the social construction and contestation of authenticity within the surfing world. Through an examination of interview and survey data that reveals contrasting perspectives on wave poo

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18

MARANO, DAVIDE, GAETANO PALUMBO, and SALVATORE PENNISI. "IMPROVED POWER-EFFICIENT RNMC TECHNIQUE WITH VOLTAGE BUFFER AND NULLING RESISTORS FOR LOW-POWER HIGH-LOAD THREE-STAGE AMPLIFIERS." Journal of Circuits, Systems and Computers 18, no. 07 (2009): 1321–31. http://dx.doi.org/10.1142/s021812660900568x.

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This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be

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19

Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumpti

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20

Wang, Ye, Yong Sheng Yin, Lang Wang, and Hong Hui Deng. "Design of the High-Speed High-Resolution Latched Comparator." Advanced Materials Research 748 (August 2013): 853–58. http://dx.doi.org/10.4028/www.scientific.net/amr.748.853.

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Based on the latch and comparison theory, a high-speed high-resolution latched comparator is designed in this paper by using a standard 0.18μm/1.8V CMOS process. With the sampling frequency of 400MHz, the Cadence Spectre simulation results show that the regeneration time is around 230ps and only 11.83mV offset voltage, power consumption is 2.12mW, the minimum voltage resolution is 0.2mV without any input offset error. The circuit is applicable for the design of a high-speed high-resolution A/D converter.

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Alimisis, Vassilis, Christos Dimas, Georgios Pappas, and Paul P. Sotiriadis. "Analog Realization of Fractional-Order Skin-Electrode Model for Tetrapolar Bio-Impedance Measurements." Technologies 8, no. 4 (2020): 61. http://dx.doi.org/10.3390/technologies8040061.

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This work compares two design methodologies, emulating both AgCl electrode and skin tissue Cole models for testing and verification of electrical bio-impedance circuits and systems. The models are based on fractional-order elements, are implemented with active components, and capture bio-impedance behaviors up to 10 kHz. Contrary to passive-elements realizations, both architectures using analog filters coupled with adjustable transconductors offer tunability of the fractional capacitors’ parameters. The main objective is to build a tunable active integrated circuitry block that is able to appr

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Wang, Xiao Yan, and Jian Ping Liu. "Design of Oscillator for PWM Controller." Applied Mechanics and Materials 157-158 (February 2012): 1242–45. http://dx.doi.org/10.4028/www.scientific.net/amm.157-158.1242.

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An oscillator is designed for PWM controller chip. The resistance Rt and capacitance Ct for oscillator are located outside the chip to adjust the frequency expediently. The circuit is simulated by CADENCE Spectre, and the simulation results show that the frequency of the oscillator is 52.84KHz (at Vcc=15V), voltage stability is 0.4%. The layout is done based on the process flow and layout levels of bipolar 45V process provided by HUAYUE Microelectronics Company. The test results prove that the oscillator present in this paper meets the design requirements.

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Liu, Zi Yi, Xing Xing Jing, and Wen Xi. "Design of a Sawtooth Generator Applied for Class-D Audio Power Amplifier." Applied Mechanics and Materials 241-244 (December 2012): 693–97. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.693.

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A systematic introduction to principles and advantages of the class-D audio amplifier based on pulse width modulation (PWM) are presented in this paper. The traditional sawtooth generator needs voltage-regulator tube to server as a core component. Against to such a disadvantage a simple way based on the charging and discharging capacitance is proposed to achieve sawtooth generator. The circuit design is based on SIMC 0.18um process. Spectre simulation results show that the sawtooth generator's performance is good. And it suits for the design of class-D audio power amplifier chip.

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SHAKER, MOHAMED O., and MAGDY A. BAYOUMI. "A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450023. http://dx.doi.org/10.1142/s0218126614500236.

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A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

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Oki, Daiki, Satoru Kawauchi, Cong Bing Li, et al. "A Power-Efficient Noise Canceling Technique Using Signal-Suppression Feed-Forward for Wideband LNAs." Key Engineering Materials 643 (May 2015): 109–16. http://dx.doi.org/10.4028/www.scientific.net/kem.643.109.

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This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is

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Fu, Qiang, Wei Ping Chen, Song Chen, Peng Fei Wang, and Xiao Wei Liu. "A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope." Key Engineering Materials 562-565 (July 2013): 369–73. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.369.

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In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes

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Hu, Zhi Cheng, Zhi Hua Ning, and Le Nian He. "A Low Temperature Coefficient, High Voltage Detection Circuit Used in Power over Ethernet." Advanced Materials Research 588-589 (November 2012): 839–42. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.839.

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A low temperature coefficient, high voltage detection circuit used in Power over Ethernet is proposed. This circuit realizes the detection comparison without utilizing an extra voltage reference circuit and comparator while the temperature coefficient of the threshold voltage is as low as that of a regular bandgap reference. The proposed detection circuit is implemented in CSMC 0.5μm 60V BCD process, Cadence Spectre simulation results show that the temperature coefficient of the threshold voltage is 66.5 ppm/°C over the temperature range of -40°C to 125°C, and the maximum variation of the thre

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Patel, Rashmit, Yash Agarwal, and Rutu Parekh. "A New Tool for Simulation of Single Electron Transistor based Microprocessor Using Vector File." Nanoscience & Nanotechnology-Asia 10, no. 4 (2020): 493–500. http://dx.doi.org/10.2174/2210681209666191014122904.

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Background: A microprocessor is a general-purpose device, which works on the user defined instructions. The design of next generation microprocessors demands high speed, high density and low power requirements that can be attained by prominent device like Single Electron Transistor (SET). Methods: Based on realizable SET parameters at room temperature and 800 mV operating voltage; an 8-bit SET based microprocessor is designed and simulated using Cadence Virtuoso environment. The simulation of the microprocessor requires complex stimuli to verify the design for multiple instructions. Convention

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Kumar, Sunil, and Arun Kr Chatterjee. "Comparative study of different Sense Amplifiers in 0.18um technology." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (2013): 615–19. http://dx.doi.org/10.24297/ijct.v7i3.3440.

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A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiersÂ are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output

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Xu, Ming Yuan, Shui Qin Yao, Liang Li, Xing Fa Huang, Xiao Feng Shen, and Xi Chen. "A Low Power Reference Buffer Used in High-Speed High-Precision Pipelined ADC." Applied Mechanics and Materials 667 (October 2014): 379–82. http://dx.doi.org/10.4028/www.scientific.net/amm.667.379.

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An analysis of the output impedance of the reference buffer for pipelined ADC is presented is this paper. To achieve high performance of the reference buffer, damping network has added in. The output impedance of buffer amplifier is made equal to the resistance of the damping network. As a result, the effective impedance is made independent of frequency. Spectre simulation with 14-bit 250MSPS pipelined ADC loads, the results show the settling time can be achieved 1.2 ns with 0.0023% precision, and the noise floor per bin is-114dB with the power consumption is 42.3mW. The reference buffer can m

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Zhang, Shuo, Zong Min Wang, and Liang Zhou. "An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC." Applied Mechanics and Materials 598 (July 2014): 365–70. http://dx.doi.org/10.4028/www.scientific.net/amm.598.365.

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This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total curr

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Liu, Liang, Song Chen, Chong He, Liang Yin, and Xiao Wei Liu. "Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator." Key Engineering Materials 609-610 (April 2014): 1176–80. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1176.

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Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modul

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Mr. Kankan Sarkar. "Design and analysis of Low Power High Speed Pulse Triggered Flip Flop." International Journal of New Practices in Management and Engineering 5, no. 03 (2016): 01–06. http://dx.doi.org/10.17762/ijnpme.v5i03.45.

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The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is

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Dendouga, Abdelghani, and Slimane Oussalah. "Telescopic Op-Amp Optimization for MDAC Circuit Design." Electronics ETF 20, no. 2 (2017): 55. http://dx.doi.org/10.7251/els1620055d.

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An 8-bit 40-MS/s low power Multiplying Digital-to-Analog Converter (MDAC) for a pipelined-to-Analog to Digital converter (ADC) is presented. The conventional dedicated operational amplifier (Op-Amp) is performed by using telescopic architecture that features low power and less-area. Further reduction of power and area is achieved by using multifunction 1.5bit/stage MDAC arch itecture. The design of the Op-Amp is performed by the elaboration of a program based on multi objective genetic algorithms to allow automated optimization. The proposed program is used to find the optimal transistors size

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Kumar, Pankaj, and Rajender Kumar Sharma. "Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing." Journal of Circuits, Systems and Computers 26, no. 02 (2016): 1750030. http://dx.doi.org/10.1142/s021812661750030x.

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To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC

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Nosker, Zachary, Yasunori Kobori, Haruo Kobayashi, et al. "A High Efficiency, Extended Load Range Boost Regulator Optimized Forenergy Harvesting Applications." Key Engineering Materials 534 (January 2013): 206–19. http://dx.doi.org/10.4028/www.scientific.net/kem.534.206.

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A small, low power bootstrapped boost regulator is introduced that can start upwith an input voltage of 240mV and achieve a maximum efficiency of 96%. The proposed circuituses two separate control schemes for startup and steady-state operation. A xed-frequencyoscillator is used to initially start up the circuit and raise the output voltage. Once the outputvoltage has reached a level adequate to bias the internal circuitry, a constant-on-time stylehysteretic control scheme is used, which helps increase system efficiency compared to using aconventional Pulse-Width-Modulated control scheme. While

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Yousefi, Mousa, Ziaadin Daie Koozehkanani, Jafar Sobhi, Hamid Jangi, and Nasser Nasirezadeh. "Efficiency Analysis of Low Power Class-E Power Amplifier." Modern Applied Science 8, no. 5 (2014): 19. http://dx.doi.org/10.5539/mas.v8n5p19.

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This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated

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Pal, Shishu, and Ashutosh Nandi. "Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach." Sensor Letters 17, no. 10 (2019): 777–83. http://dx.doi.org/10.1166/sl.2019.4136.

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This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for s

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Kumar Beura, Srikant, Rekib Uddin Ahmed, Bishnulatpam Pushpa Devi, and Prabir Saha. "On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges." Electronics ETF 25, no. 1 (2021): 20–30. http://dx.doi.org/10.53314/els2125020b.

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Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined throu

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Muhamad, Maizan, Norhayati Soin, and Harikrishnan Ramiah. "Linearity improvement of differential CMOS low noise amplifier." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 407. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp407-412.

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<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<s

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Zainol Murad, Sohiful Anuar, Azizi Harun, Mohd Nazrin Md Isa, Saiful Nizam Mohyar, and Jamilah Karim. "A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM." Jurnal Teknologi 82, no. 6 (2020): 11–19. http://dx.doi.org/10.11113/jurnalteknologi.v82.15031.

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This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results

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Prof. Bhushan Thakre, Dr. R.M Thakre. "Analysis of Modified Current Controller and its Implementation in Automotive LED." International Journal of New Practices in Management and Engineering 6, no. 04 (2017): 01–06. http://dx.doi.org/10.17762/ijnpme.v6i04.60.

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A novel highly dimmable current controller which is a linear one is employed in the application of low power automotive is discussed here. Light Emitting Diode is the one which drives current that is linearly controlled to decrease the intensity of LED to limit the destruction of the LED and improve its reliability. Although many dimming techniques for LED lighting are available, our proposed method outperforms the existing methods in terms of power consumption and the no. of transistors used in the proposed design. This emits 100mA and decrease the LED current which is going linearly based on

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Bhargava, Bhanupriya, Pradeep Kumar Sharma, and Shyam Akashe. "High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime." International Journal of Nanoscience 13, no. 01 (2014): 1450003. http://dx.doi.org/10.1142/s0219581x14500033.

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In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requ

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A. Jyotsna, K., P. Satish Kumar, B. K. Madhavi, and Sana Bano. "Implementation of data path components of ARM7 microprocessor using sub threshold current mode logic with sleep transistor technique." International Journal of Engineering & Technology 7, no. 2.12 (2018): 253. http://dx.doi.org/10.14419/ijet.v7i2.12.11292.

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The latest Very Large Scale Integration (VLSI) technology trends have been moving towards making devices cheaper and more powerful for everyone to afford them. So the ultimate focus being reducing power consumption by the gadgets. With the added feature of transistors to be structured in 3D, the Moore’s law is to be continued. Hence, Leakage currents are a major concern with the increasing number of transistors per chip when the technology is scaled, static power dissipation needs to be monitored. Advanced RISC Machine (ARM) Processors have been giving a new definition to smart phones, tablets

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Dendouga, Abdelghani, Slimane Oussalah, Damien Thienpont, and Abdenour Lounis. "Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics." Advances in Electrical Engineering 2014 (August 13, 2014): 1–5. http://dx.doi.org/10.1155/2014/374741.

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The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) bas

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Jung, Seungmin. "Image Processor and RISC MCU Embedded Single Chip Fingerprint Sensor." Journal of Sensor and Actuator Networks 9, no. 4 (2020): 51. http://dx.doi.org/10.3390/jsan9040051.

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In this paper, we propose a single chip fingerprint sensor with the algorithm processor and 16-bit MCU. The algorithm processor is a logic circuit that implements the GABOR filter and the THINNING step, which occupies 80% of the fingerprint image processing time. The rest of the algorithm is processed by embedded 16-bit MCU with small circuit volume, so all steps of the algorithm can be processed on the single chip without an external CPU. The capacitive sensing circuit was designed by applying the parasitic-insensitive integrator with the variable clock generator. The function was verified by

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Pal, Satyabrata, and Arunava Ghosh. "Global annual average temperature – a precise modelling." Biometrical Letters 51, no. 1 (2014): 37–44. http://dx.doi.org/10.2478/bile-2014-0003.

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SUMMARY Global annual average temperature (GAAT) is regarded as a precise indicator of the warming of the globe over the centuries, and its spectre is looming large with the passage of time and with the advancement of civilization. Global warming, caused by the accumulation of greenhouse gases in the atmosphere, has become the worst environmental threat to mankind. The phase 1981 to 2012 was the most crucial phase, and the impact of global warming in that phase indeed points to a disaster if not controlled now. Work on the building of appropriate models to represent the GAAT data can be found

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INANLOU, REZA, and MOHAMMAD YAVARI. "A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450026. http://dx.doi.org/10.1142/s0218126614500261.

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In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digita

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Strohmaier, Paul. "Heilsfiktionen." Romanistisches Jahrbuch 71, no. 1 (2020): 169–203. http://dx.doi.org/10.1515/roja-2020-0005.

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AbstractEven in a century so commonly associated with the stage as the French siècle classique, the theatre’s social, political and religious acceptance as a cultural practice remains highly contested. Hence, the recourse to the seemingly obsolete dramatic genre of the martyr tragedy that both Corneille (Polyeucte, Théodore) and Rotrou (Le véritable Saint Genest) take in the 1640 s must be understood as an attempt to secure a possible alliance between Christian devotion and the stage. Rather than effecting a reconciliation between the two, however, all three plays in question, in their attempt

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Ritchie, Nicholas W. M. "Spectrum Simulation in DTSA-II." Microscopy and Microanalysis 15, no. 5 (2009): 454–68. http://dx.doi.org/10.1017/s1431927609990407.

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AbstractSpectrum simulation is a useful practical and pedagogical tool. Particularly with complex samples or trace constituents, a simulation can help to understand the limits of the technique and the instrument parameters for the optimal measurement. DTSA-II, software for electron probe microanalysis, provides both easy to use and flexible tools for simulating common and less common sample geometries and materials. Analytical models based on ϕ(ρz) curves provide quick simulations of simple samples. Monte Carlo models based on electron and X-ray transport provide more sophisticated models of a

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