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Relevant bibliographies by topics / Simulation HDL

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Academic literature on the topic 'Simulation HDL'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "Simulation HDL"

1

Skold, S., and R. Ayani. "Fast simulation of HDL models." IEEE Potentials 14, no. 5 (1996): 14–17. http://dx.doi.org/10.1109/45.481506.

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Mittal, Mayank. "Simulation of 16 bit ALU using Verilog-hdl." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (December 31, 2017): 114–15. http://dx.doi.org/10.31142/ijtsrd5876.

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Milik, Adam, and Adam Zytka. "HDL Simulation and mathematical modelling integration." IFAC Proceedings Volumes 39, no. 21 (February 2006): 144–49. http://dx.doi.org/10.1016/s1474-6670(17)30174-x.

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Yang, Seiyang, and Kyuho Shim. "A Practical Approach to Incremental Event-driven HDL Simulation." KIPS Transactions on Computer and Communication Systems 3, no. 3 (March 31, 2014): 73–80. http://dx.doi.org/10.3745/ktccs.2014.3.3.73.

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Memon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (July 1, 2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.

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In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.

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Cilpa-Karhu, Geraldine, Matti Jauhiainen, and Marja-Liisa Riekkola. "Atomistic MD simulation reveals the mechanism by which CETP penetrates into HDL enabling lipid transfer from HDL to CETP." Journal of Lipid Research 56, no. 1 (November 25, 2014): 98–108. http://dx.doi.org/10.1194/jlr.m054288.

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Kobayashi, Ryohei, Tomohiro Misono, and Kenji Kise. "A High-speed Verilog HDL Simulation Method using a Lightweight Translator." ACM SIGARCH Computer Architecture News 44, no. 4 (January 11, 2017): 26–31. http://dx.doi.org/10.1145/3039902.3039908.

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Adon, Nur Atiqah, Fahanahani Mahmud, Mohamad Hairol Jabbar, and Norliza Othman. "Optimization in MATLAB for Cardiac Excitation Modeling towards FPGA Standalone Simulation Tools." Applied Mechanics and Materials 773-774 (July 2015): 761–65. http://dx.doi.org/10.4028/www.scientific.net/amm.773-774.761.

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In past few decades, most of the modern electrophysiological concepts and methods were developed by the computational technique extensively to compute the cardiac action potential in nerve cells. Thus, tissue models consisting of a large number of single cell models cause a problem in the amount of computation required to obtain meaningful results from simulations. One of the solutions to this problem is by implementing the simulation through hardware modeling using a Field Programmable Gate Array (FPGA). Here, a research on developing a real-time simulation tool responsible for reentrant excitations in a ring of cardiac tissue based on the FitzHugh-Nagumo (FHN) model has been carried out by using a Xilinx Virtex-6 XC6VLX240T ML605 development board FPGA. In order to invest some of the time savings for creating the FPGA prototype, rapid prototyping method introduced by MathWorks which are MATLAB Simulink and its HDL Coder toolbox have been used to automate the algorithm design process by converting Simulink blocks into Hardware Description Language (HDL) code for the FPGA using a fixed-point data type in discrete-time framework. In this paper, the method and the optimization of the HDL design through the MATLAB Simulink have been discussed and the FPGA hardware performance in terms of speed, area and power consumption has also been analyzed.

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Litovski, Vančo, Dejan Maksimović, and Željko Mrčarica. "Mixed-signal modeling with AleC++: Specific features of the HDL." Simulation Practice and Theory 8, no. 6-7 (March 2001): 433–49. http://dx.doi.org/10.1016/s0928-4869(01)00027-1.

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Wei Chun, Quek, Pang Wai Leong, Chan Kah Yoong, Lee It Ee, and Chung Gwo Chin. "HDL Modelling of Low-CostMemory Fault Detection Tester." Journal of Engineering Technology and Applied Physics 2, no. 2 (December 15, 2020): 17–23. http://dx.doi.org/10.33093/jetap.2020.2.2.3.

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

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Dissertations / Theses on the topic "Simulation HDL"

1

Tong, C. O. (Chung On) 1945. "A schedule-based transit network model." Monash University, Dept. of Civil Engineering, 1986. http://arrow.monash.edu.au/hdl/1959.1/7935.

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McBean, Ivan William 1974. "Simulation of 3-dimensional aeroelastic effects in turbomachinery cascades." Monash University, Dept. of Mechanical Engineering, 2002. http://arrow.monash.edu.au/hdl/1959.1/7690.

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Alharbi, Badr Hadhidh A. "Airborne dust in Saudi Arabia: source areas, entrainment, simulation and composition." Monash University. Faculty of Arts. School of Geography and Environmental Science, 2009. http://arrow.monash.edu.au/hdl/1959.1/74116.

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Spatial and temporal characteristics of dust storm activity in Saudi Arabia has been established using coarse-particle (PM10) dust concentrations recorded by the KACST monitoring network during the 2000-2003 period, backward trajectory analysis and satellite imagery. Thirty three major dust episodes impacted Riyadh city during the 2000-2003 period. The majority of these intense dust episodes are experienced during the March-August period with interannual and monthly variability in both intensity and frequency. Using TOMS images in conjunction with the backward trajectories corresponding to these 33 major episodes, the dust source regions have been identified. The most vulnerable dust source areas within these identified source regions have also been determined by compiling satellite images of dusty days from the true color SeaWiFs and high resolution MODIS archives over a six-year period (2000-2005). In total 45 dust-source areas have been identified in 9 local source regions and 4 external ones. Furthermore, 38 episodes of high fine-particle (PM2.5) and PM10 dust concentrations were observed at Riyadh city and 16 and 6 episodes of elevated PM10 dust concentrations were observed at Dammam and Jeddah cities, respectively, during March-September 2006, corresponding to the dust season in Saudi Arabia. During these episodes, Riyadh city was significantly impacted by dust from the southern Iraqi source areas and the eastern source areas located to the north and to the northeast of the city, respectively. Moreover, Dammam city was also significantly impacted by dust from the southern Iraqi source areas whereas Jeddah city was evenly impacted by dust from northeastern-northwestern sources to the city, with somewhat higher PM10 concentrations from African dust source areas, located to the northwest of the city. Analysis of meteorological maps of surface pressure as well as upper air data associated with high airborne dust concentrations in Saudi Arabia was successfully performed. This analysis revealed seven common types of dust storms, triggered by a clear seasonal distribution of meteorological conditions: (1) frontal, (2) Haboob, (3) jets convergence, (4) jet streak, (5) Shamal, (6) cyclonic, and (7) gap. The majority of dust episodes that impacted Riyadh city during the study period were triggered by Haboob (~ 42 %) and Shamal (~ 37 %). Additional analyses, including elemental, ionic and biological analyses as well as model analyses were used to further characterize the airborne dust in Saudi Arabia.

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Chang, Ken Kai-fu 1973. "Simulation of nonlinear optic-fibre communication systems using Volterra series transfer function techniques." Monash University, Dept. of Electrical and Computer Systems Engineering, 2002. http://arrow.monash.edu.au/hdl/1959.1/7758.

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Blampey, Alexandre. "Interopérabilité en émulation et prototypage matériel." Grenoble INPG, 2006. http://www.theses.fr/2006INPG0168.

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Cette thèse introduit un nouveau concept dans la vérification des circuits au niveau RTL : l'interopérabilité entre simulateurs HDL, émulateurs matériel et plateformes de prototypage. Cela permet de bénéficier, à la fois de l'excellente vitesse d'exécution des plateformes de prototypage et des capacités de déboguage, d'observabilité et contrôlabilité offertes par les émulateurs matériel et simulateurs HDL. L'idée principale consiste en la réalisation des tests sur une plateforme de prototypage rapide tout en réalisant périodiquement des sauvegardes de l'état du circuit. Lorsqu'une erreur apparait, le déboguage est réalisé, soit un émulateur rapide, soit un simulateur HDL économique: le test est alors rejoué à partir de la dernière sauvegarde d'état réalisée avant l'instant d'apparition du problème. Enfin, cette thèse présente un flot de prototypage, validé sur un circuit industriel «STM HLS25», permettant d'intégrer l'interopérabilité comme une fonctionnalité du circuit
This thesis defines a new concept in RTL verification: interoperability between HDL simulators, hardware emulators and hardware prototyping platforms. The main purpose is to benefit from both good speed of hardware prototyping platforms and de bug capabilities of hardware emulators and HDL simulators. To achieve this purpose, this thesis introduces the notion of design state. Then, a interoperability dedicated tool is presented. This tool add interoperability to design functionnalities. Thus, ail machines working at RTL level are interoperables with each others. The main idea of interoperability is to lunch tests on fast prototyping platforms while periodically saving design state. When a bug will be faced, debug will be performed using a fast emulator or a low cost HDL simulator. The test will restart from the last database saved just before bug time. Finally, this thesis introduce a new prototyping flow which was validated on an industrial design «STM HLS25»

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Choy, Vivian K. Y. 1971. "Estimating the inevitability of fast oscillations in model systems with two timescales." Monash University, Dept. of Mathematics and Statistics, 2001. http://arrow.monash.edu.au/hdl/1959.1/9068.

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Privat, Anne-Gisèle. "L'avenir des retraites en France : évaluation de l'impact des réformes de 1993 à 2003 à l'aide du modèle de microsimulation ARTEMIS." Paris, Institut d'études politiques, 2005. http://spire.sciences-po.fr/hdl:/2441/f4rshpf3v1umfa09lat214kj4.

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L'objectif de la thèse est de donner une mesure des conséquences à moyen et long terme de la réforme des retraites du secteur privé, à législation inchangée, et d'effectuer une analyse comparative des effets des réformes de 1993 et de 2003 sur le niveau et les distributions des retraites futures à l'horizon 2030. A cette fin, nous construisons et utilisons un modèle de microsimulation, le modèle ARTEMIS (analyse des retraites du secteur privé par microsimulation), basé sur le fichier des assurés au régime général d'assurance vieillesse de la sécurité sociale géré par la Caisse nationale d'assurance vieillesse des travailleurs salariés (CNAV). Ce régime couvre les salariés du secteur privé, soit près des deux tiers de la population active française. Cette thèse est organisée en deux grandes parties. Dans la première partie intitulée "Microsimulation et retraites du régime général", nous présentons l'intérêt de la microsimulation pour l'étude des retraites du régime général sur le long terme, ainsi que les grandes caractéristiques de ce régime. La seconde partie sur "Le modèle de microsimulation ARTEMIS et ses résultats" décrit le modèle, puis présente les simulations des retraites de droit propre à l'horizon 2030 et leur comparaison aux autres sources d'évaluation disponibles. Nous nous intéressons au parcours des générations 1935 à 1970. Nous analysons les effets de ces réformes sur les dépenses totales, ainsi que leurs conséquences redistributives, en tenant compte des évolutions individuelles de carrière. En effet, la politique des retraites, comme toute politique sociale, repose sur des principes combinant efficacité économique et redistribution.

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Wilson, Simon J. "Thermal profiles in oxygen vacuum swing adsorption (VSA) : modelling, observations and optimisation." Monash University, Dept. of Chemical Engineering, 2001. http://arrow.monash.edu.au/hdl/1959.1/7766.

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Twining, Erika. "Voltage compensation in weak distribution networks using shunt connected voltage source converters." Monash University, Dept. of Electrical and Computer Systems Engineering, 2004. http://arrow.monash.edu.au/hdl/1959.1/9701.

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Kora, Venugopal Rishvanth. "FPGA BASED PARALLEL IMPLEMENTATION OF STACKED ERROR DIFFUSION ALGORITHM." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/40.

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Digital halftoning is a crucial technique used in digital printers to convert a continuoustone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This thesis focuses on the development and design of a parallel scalable hardware architecture for high performance implementation of a high quality Stacked Error Diffusion algorithm. The algorithm is described in ‘C’ and requires a significant processing time when implemented on a conventional CPU. Thus, a new hardware processor architecture is developed to implement the algorithm and is implemented to and tested on a Xilinx Virtex 5 FPGA chip. There is an extraordinary decrease in the run time of the algorithm when run on the newly proposed parallel architecture implemented to FPGA technology compared to execution on a single CPU. The new parallel architecture is described using the Verilog Hardware Description Language. Post-synthesis and post-implementation, performance based Hardware Description Language (HDL), simulation validation of the new parallel architecture is achieved via use of the ModelSim CAD simulation tool.

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Books on the topic "Simulation HDL"

1

Chuang, Chao-Kuei. An investigation into mixed-mode simulation using HDL behavioural models. Manchester: University of Manchester, 1994.

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HDL chip design: A practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog. Madison, AL: Doone Publications, 1996.

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Mirfendreski, Aras. Entwicklung eines echtzeitfähigen Motorströmungs- und Stickoxidmodells zur Kopplung an einen HiL-Simulator. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-19329-4.

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Practical HDL: Real World Synthesis and Simulation (MXP). Technically Speaking, Inc., 2004.

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Mechatronic Systems: Modelling and Simulation with HDLs. Wiley, 2003.

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Perelroyzen, Evgeni. Computer Arithmetic: Systems Simulation Using Simulink, Stateflow, and HDLs. CRC, 2009.

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Joshi, Adit. Automotive Applications of Hardware-in-the-Loop (HIL) Simulation. SAE International, 2019. http://dx.doi.org/10.4271/9781468600070.

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Smith, Douglas J. Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog. Doone Pubns, 1998.

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National Institute of Standards and Technology (U.S.), ed. Comparison of CFAST and FDS for fire simulation with the HDR T51 and T52 tests. Gaithersburg, MD: U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, 2002.

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Mirfendreski, Aras. Entwicklung eines echtzeitfähigen Motorströmungs- und Stickoxidmodells zur Kopplung an einen HiL-Simulator. Springer Vieweg, 2017.

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Book chapters on the topic "Simulation HDL"

1

Stanculescu, Alec. "HDL-Driven Digital Simulation." In Fundamentals and Standards in Hardware Description Languages, 263–80. Dordrecht: Springer Netherlands, 1993. http://dx.doi.org/10.1007/978-94-011-1914-6_8.

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Bergeron, Janick. "Simulation Management." In Writing Testbenches: Functional Verification of HDL Models, 375–428. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0302-6_7.

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Gadelrab, Serag M., and James A. Barby. "Creative Methods of Leveraging VHDL-AMS-like Analog-HDL Environments. Case Study: Simulation of Circuit Reliability." In Analog VHDL, 69–84. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5753-1_7.

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Schaffnit, Jochen. "HIL Simulation von Dieselmotoren mit Antriebstrang." In Modellgestützte Steuerung, Regelung und Diagnose von Verbrennungsmotoren, 307–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-642-55698-2_18.

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Pabiszczak, Mateusz, Krzysztof Górny, Przemysław Raczyński, and Zygmunt Gburski. "Impact of Carbon Nanotubes on HDL-Like Structures: Computer Simulations." In Springer Proceedings in Physics, 481–87. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-17759-1_32.

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Matheis, I., T. Dörsam, and W. Hoffmann. "Integrating a SiL into a HiL Test Platform." In Simulation and Testing for Vehicle Technology, 15–19. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-32345-9_2.

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Brötz, Nicolas, Manuel Rexer, and Peter F. Pelz. "Mastering Model Uncertainty by Transfer from Virtual to Real System." In Lecture Notes in Mechanical Engineering, 35–44. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-77256-7_4.

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AbstractTwo chassis components were developed at the Technische Universität Darmstadt that are used to isolate the body and to reduce wheel load fluctuation.The frequency responses of the components were identified with a stochastic foot point excitation in a hardware-in-the-loop (HiL) simulation environment at the hydropulser. The modelling of the transmission behaviour influence of the testing machine on the frequency response was approximately represented with a time delay of $$10\,\mathrm {ms}$$ 10 ms in the frequency range up to $$25\,\mathrm {Hz}$$ 25 Hz . This is considered by a Padé approximation. It can be seen that the dynamics of the testing machine have an influence on the wheel load fluctuation and the body acceleration, especially in the natural frequency of the unsprung mass. Therefor, the HiL stability is analysed by mapping the poles of the system in the complex plane, influenced by the time delay and virtual damping.This paper presents the transfer from virtual to real quarter car to quantify the model uncertainty of the component, since the time delay impact does not occur in the real quarter car test rig. The base point excitation directly is provided by the testing machine and not like in the case of the HiL test rig, the compression of the spring damper calculated in the real-time simulation.

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Kiffe, A., S. Geng, and T. Schulte. "Herausforderung der HIL–Simulation für Hybrid‐ und Elektrofahrzeuge." In Schritte in die künftige Mobilität, 111–20. Wiesbaden: Springer Fachmedien Wiesbaden, 2013. http://dx.doi.org/10.1007/978-3-8349-4308-8_8.

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Mirfendreski, Aras. "Hardware-in-the-Loop (HiL)-Kopplung." In Entwicklung eines echtzeitfähigen Motorströmungs- und Stickoxidmodells zur Kopplung an einen HiL-Simulator, 115–37. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-19329-4_4.

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Stolpe, Ralf, and Oliver Oberschelp. "Distributed HIL Simulation for the Design of Decentralized Control Structures." In Distributed and Parallel Embedded Systems, 97–106. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-0-387-35570-2_8.

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Conference papers on the topic "Simulation HDL"

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Qi Jianling and Deng Zhenjie. "Models simulation based on HDL-Simulink platform." In 2011 2nd International Conference on Control, Instrumentation, and Automation (ICCIA). IEEE, 2011. http://dx.doi.org/10.1109/icciautom.2011.6183939.

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Buck, Joseph, Dong Wang, and Yunshan Zhu. "Formal model construction using HDL simulation semantics." In 2007 IEEE International High Level Design Validation and Test Workshop. IEEE, 2007. http://dx.doi.org/10.1109/hldvt.2007.4392797.

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Qi, Jianling, and Zhenjie Deng. "Models Simulation based on HDL-Simulink Platform." In 2013 2nd International Conference on Intelligent System and Applied Material. Ottawa: EDUGAIT Press, 2013. http://dx.doi.org/10.12696/gsam.2013.0868.

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Crespo, Juan-Jose, German Maglione-Mathey, Jose L. Sanchez, Francisco J. Alfaro-Cortes, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, and Francisco J. Quiles. "Methodology for Decoupled Simulation of SystemVerilog HDL Designs." In 2019 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2019. http://dx.doi.org/10.1109/hpcs48598.2019.9188056.

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Macko, Dominik, and Katarina Jelemenska. "VHDLVisualizer: HDL model visualization with simulation-based verification." In 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2012. http://dx.doi.org/10.1109/ddecs.2012.6219056.

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Wang, Lingfeng, Hong Chen, and Yangdong Steve Deng. "Robust conservative parallel HDL simulation on multi-core CPUs." In 2013 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2013. http://dx.doi.org/10.1109/hpcsim.2013.6641448.

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Ahmad, Tariq B., and Maciej Ciesielski. "Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning." In 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2014. http://dx.doi.org/10.1109/isvlsi.2014.47.

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Ahmad, Tariq Bashir, Namdo Kim, Byeong Min, Apurva Kalia, Maciej Ciesielski, and Seiyang Yang. "Scalable parallel event-driven HDL simulation for multi-cores." In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2012. http://dx.doi.org/10.1109/smacd.2012.6339456.

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Milik, Adam, and Andrzej Pulka. "Complex mathematical models simulation on mixed HDL-simulink platform." In 2008 Conference on Human System Interactions (HSI). IEEE, 2008. http://dx.doi.org/10.1109/hsi.2008.4581468.

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Dusung Kim, M. Ciesielski, Kyuho Shim, and Seiyang Yang. "Temporal parallel simulation: A fast gate-level HDL simulation using higher level models." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763251.

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Reports on the topic "Simulation HDL"

1

DeLong, Suzanne O., Eric S. Tollefson, and Roger C. Burk. Modeling of HEL Weapons in Combat Simulations. Fort Belvoir, VA: Defense Technical Information Center, September 2003. http://dx.doi.org/10.21236/ada416997.

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Roozbahani, Bahareh. Simulation of CMS Phase 2 Pixel Tracker for HL-LHC. Office of Scientific and Technical Information (OSTI), June 2018. http://dx.doi.org/10.2172/1462095.

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Fitterer, M., G. Stancari, A. Valishev, and S. Redaelli. Simulation study of Hollow Electron Beam Collimation in HL-LHC. Office of Scientific and Technical Information (OSTI), October 2016. http://dx.doi.org/10.2172/1408322.

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Floyd, Jason E. Comparison of CFAST and FDS for fire simulation with the HDR T51 and T52 tests. Gaithersburg, MD: National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6866.

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Yudong Pan, S.C. Jardin, and C. Kes. The Discharge Design of HL-2M with the Tokamak Simulation Code (TSC). Office of Scientific and Technical Information (OSTI), October 2007. http://dx.doi.org/10.2172/961897.

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