Journal articles: 'Simulation HDL'

1

Skold, S., and R. Ayani. "Fast simulation of HDL models." IEEE Potentials 14, no. 5 (1996): 14–17. http://dx.doi.org/10.1109/45.481506.

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Mittal, Mayank. "Simulation of 16 bit ALU using Verilog-hdl." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (December 31, 2017): 114–15. http://dx.doi.org/10.31142/ijtsrd5876.

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Milik, Adam, and Adam Zytka. "HDL Simulation and mathematical modelling integration." IFAC Proceedings Volumes 39, no. 21 (February 2006): 144–49. http://dx.doi.org/10.1016/s1474-6670(17)30174-x.

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Yang, Seiyang, and Kyuho Shim. "A Practical Approach to Incremental Event-driven HDL Simulation." KIPS Transactions on Computer and Communication Systems 3, no. 3 (March 31, 2014): 73–80. http://dx.doi.org/10.3745/ktccs.2014.3.3.73.

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Memon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (July 1, 2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.

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In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.

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Cilpa-Karhu, Geraldine, Matti Jauhiainen, and Marja-Liisa Riekkola. "Atomistic MD simulation reveals the mechanism by which CETP penetrates into HDL enabling lipid transfer from HDL to CETP." Journal of Lipid Research 56, no. 1 (November 25, 2014): 98–108. http://dx.doi.org/10.1194/jlr.m054288.

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Kobayashi, Ryohei, Tomohiro Misono, and Kenji Kise. "A High-speed Verilog HDL Simulation Method using a Lightweight Translator." ACM SIGARCH Computer Architecture News 44, no. 4 (January 11, 2017): 26–31. http://dx.doi.org/10.1145/3039902.3039908.

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Adon, Nur Atiqah, Fahanahani Mahmud, Mohamad Hairol Jabbar, and Norliza Othman. "Optimization in MATLAB for Cardiac Excitation Modeling towards FPGA Standalone Simulation Tools." Applied Mechanics and Materials 773-774 (July 2015): 761–65. http://dx.doi.org/10.4028/www.scientific.net/amm.773-774.761.

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In past few decades, most of the modern electrophysiological concepts and methods were developed by the computational technique extensively to compute the cardiac action potential in nerve cells. Thus, tissue models consisting of a large number of single cell models cause a problem in the amount of computation required to obtain meaningful results from simulations. One of the solutions to this problem is by implementing the simulation through hardware modeling using a Field Programmable Gate Array (FPGA). Here, a research on developing a real-time simulation tool responsible for reentrant excitations in a ring of cardiac tissue based on the FitzHugh-Nagumo (FHN) model has been carried out by using a Xilinx Virtex-6 XC6VLX240T ML605 development board FPGA. In order to invest some of the time savings for creating the FPGA prototype, rapid prototyping method introduced by MathWorks which are MATLAB Simulink and its HDL Coder toolbox have been used to automate the algorithm design process by converting Simulink blocks into Hardware Description Language (HDL) code for the FPGA using a fixed-point data type in discrete-time framework. In this paper, the method and the optimization of the HDL design through the MATLAB Simulink have been discussed and the FPGA hardware performance in terms of speed, area and power consumption has also been analyzed.

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Litovski, Vančo, Dejan Maksimović, and Željko Mrčarica. "Mixed-signal modeling with AleC++: Specific features of the HDL." Simulation Practice and Theory 8, no. 6-7 (March 2001): 433–49. http://dx.doi.org/10.1016/s0928-4869(01)00027-1.

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Wei Chun, Quek, Pang Wai Leong, Chan Kah Yoong, Lee It Ee, and Chung Gwo Chin. "HDL Modelling of Low-CostMemory Fault Detection Tester." Journal of Engineering Technology and Applied Physics 2, no. 2 (December 15, 2020): 17–23. http://dx.doi.org/10.33093/jetap.2020.2.2.3.

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

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Tashev, Svetoslav, Todor Tashev, and Philip Philipov. "Emulation and Analytical Model of PIM Supplemental Computing Element via HDL." Information Technologies and Control 12, no. 2 (June 1, 2014): 19–22. http://dx.doi.org/10.1515/itc-2015-0012.

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Abstract This article presents and describes the simulation and emulation of single processing core, designed for new heterogeneous multiprocessor computer architectures with supplemental computing elements in the operating memory. We study the emulated results over the simulated model to confirm it’s usability in the overall simulation of complete system. The simulated models are developed based on existing data, comparing time markers, measuring the output performance against the results from the emulation. Using additional computing elements in the memory will allows us to improve the current limitations of the conventional architectures.

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Ananthan, T., and M. V. Vaidyan. "FPGA-based parallel architecture for PID control algorithm and HDL co-simulation." International Journal of Embedded Systems 5, no. 4 (2013): 239. http://dx.doi.org/10.1504/ijes.2013.057703.

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Xu, Qiuyun, Christopher L. Ayala, Naoki Takeuchi, Yuki Yamanashi, and Nobuyuki Yoshikawa. "HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic." IEEE Transactions on Applied Superconductivity 26, no. 8 (December 2016): 1–5. http://dx.doi.org/10.1109/tasc.2016.2615123.

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Meng, Wei, Fengxu Yu, Huaiqing Chen, Jianmin Zhang, Eryong Zhang, Ke Dian, and Yingkang Shi. "Concentration Polarization of High-Density Lipoprotein and Its Relation with Shear Stress in an In Vitro Model." Journal of Biomedicine and Biotechnology 2009 (2009): 1–8. http://dx.doi.org/10.1155/2009/695838.

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The purpose of this study was to determine the concentration polarization of high-density lipoprotein (HDL) at the surface of the carotid artery under conditions of steady flow and to establish its relationship with shear stress using an in vitro vascular simulation model of carotid bifurcation. Shear stress, HDL concentration at the surface, and the ratio of HDL concentration at the surface to concentration in bulk flow were measured at different locations within the model under high-speed (1.451 m/s) and low-speed (0.559 m/s) flow. HDL showed concentration polarization at the surface of the carotid artery model, particularly in the internal carotid artery sinus. With decreasing flow velocity, the shear stress at the surface also decreased, and HDL concentration polarization increased. The concentration polarization of HDL was negatively and strongly correlated with shear stress at both low- (r=−0.872,P<.001) and high-speed flow (r=−0.592,P=.0018).

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Hwang, Dong Hyun, Chang Yeop Han, Hyun Woo Oh, and Seung Eun Lee. "ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator." Micromachines 12, no. 7 (July 19, 2021): 838. http://dx.doi.org/10.3390/mi12070838.

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Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the performance space of k-NN algorithms and generate Verilog HDL code to demonstrate the k-NN accelerator in FPGA. Our contribution is to provide the artificial intelligence algorithm as an end-to-end pipeline and ensure that it is optimized to a specific dataset through simulation, and an artificial intelligence accelerator is generated in the end.

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Reddy Chirasani, Venkata, and Sanjib Senapati. "Lipid Transfer Mechanism of CETP between HDL and LDL: A Coarse-Grained Simulation Study." Biophysical Journal 112, no. 3 (February 2017): 386a—387a. http://dx.doi.org/10.1016/j.bpj.2016.11.2101.

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Gautam, Arvind K., and Avinash Chandra. "A computational study of Stillinger–Weber silicon at 0.75 GPa in supercooled region." International Journal of Modern Physics B 32, no. 30 (December 10, 2018): 1850330. http://dx.doi.org/10.1142/s0217979218503307.

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We studied the liquid-liquid transition in supercooled silicon modeled by the Stillinger–Weber potential. The Isothermal Isobaric Monte Carlo (NPT-MC) simulation techniques were performed here to compute the free energy difference between the two liquid phases of silicon by Bennett Acceptance Ratio (BAR) method along with a reversible path at 0.75 GPa pressure and 970 K temperature. The thermodynamic properties as energy ([Formula: see text]) and density ([Formula: see text]) of the high-density liquid (HDL) phase have been computed here at different temperatures from 970–990 K. We also computed the entropy difference between the high-density liquid (HDL) and low-density liquid (LDL) phases which indicates that the glass transition temperature for the LDL phase is lower compared to the HDL phase. Further, by using the BAR method, we have computed the excess Gibbs free energy (G[Formula: see text]) of HDL phase with respect to the crystalline phase at different temperatures in the supercooled region of SW-Silicon potential model. Based on the slope of excess Gibbs free energy with respect to temperature (T), we found that the excess entropy (Se) of the HDL with respect to crystalline phase shows a nonmonotonic dependence on temperature at the liquid-liquid transition temperature of T[Formula: see text] = 970 K. Our results are in good agreement with the previous observation of a nonmonotonic dependence of the enthalpy on temperature in MD simulations, starting with the HDL phase at a temperature just above T[Formula: see text]. All these properties are useful to understand the phase behavior of supercooled silicon and can be applicable to identify the better quality of silicon for industrial uses.

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Voigt Nesbo, Simon, Johan Alme, Matthias Bonora, Piero Giubilato, Håvard Helstrup, Matteo Lupi, Gianluca Aglieri Rinella, et al. "System simulations for the ALICE ITS detector upgrade." EPJ Web of Conferences 245 (2020): 02011. http://dx.doi.org/10.1051/epjconf/202024502011.

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The ALICE experiment at the CERN LHC will feature several upgrades for Run 3, one of which is a new Inner Tracking System (ITS). The ITS upgrade is currently under development and commissioning, and will be installed during the ongoing long shutdown 2. A number of factors will have an impact on the performance and readout efficiency of the ITS in run 3, and to that end, a simulation model of the readout logic in the ALPIDE pixel sensor chips for the ITS was developed, using the SystemC library for system level modeling in C++. This simulation model is three orders of magnitude faster than a normal HDL simulation of the chip and facilitates simulations of an increased number of events for a large portion of the detector. In this paper, we present simulation results, where we have been able to quantify detector performance under different running conditions. The results are used for system configuration as well as for the ongoing development of the readout electronics.

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Chirasani, Venkata Reddy, and Sanjib Senapati. "High Resolution Model of HDL Wrapped with Tetrafoil apoA-I: A Coarse-Grained Simulation Study." Biophysical Journal 108, no. 2 (January 2015): 248a. http://dx.doi.org/10.1016/j.bpj.2014.11.1372.

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Romanov, Aleksandr, and Alexander Ivannikov. "SystemC Language Usage as the Alternative to the HDL and High-level Modeling for NoC Simulation." International Journal of Embedded and Real-Time Communication Systems 9, no. 2 (July 2018): 18–31. http://dx.doi.org/10.4018/ijertcs.2018070102.

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This article describes how actual trends of networks-on-chip research and known approaches to their modeling are considered. The characteristics of analytic and high- / low- level simulation are given. The programming language SystemC as an alternative solution to create models of networks-on-chip is proposed, and SystemC models speed increase methodic is observed. The methods of improving SystemC models are formulated. There has been shown how SystemC language can reduce the disadvantages and maximize the advantages of high-level and low-level approaches. To achieve this, the comparison of results for high-level, low-level and SystemC NoC simulation is given on the example of “hot spots” and the geometric shape of regular NoC topologies effect on their productivity.

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Nguyen, Linh Thi Le, Nhan Chi Nguyen, Dong An Bui, and Hieu Van Nguyen. "Design and simulation of PCI Express physical layer." Science and Technology Development Journal 18, no. 3 (August 30, 2015): 101–13. http://dx.doi.org/10.32508/stdj.v18i3.826.

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This paper presents a detailed analysis, design and simulation of PCI Express Physical Layer. The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data interchange. The Physical Layer is divided into the logical and electrical subblocks. The paper designed Physical Layer in the system level with top-down design method and wrote the Verilog HDL codes to implement Physical Layer. Wrote testbench to verify the correctness of the design module for function simulation. The simulation results show that the designed Physical Layer meets the required of the function of PCI Express™ Physical layer Base Specification Revision 2.0.

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Kim, Choon Ok, Sangil Jeon, Seunghoon Han, Min Soo Park, and Dong-Seok Yim. "A Population Pharmacokinetic and Pharmacodynamic Model of CKD-519." Pharmaceutics 12, no. 6 (June 19, 2020): 573. http://dx.doi.org/10.3390/pharmaceutics12060573.

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CKD-519 is a selective and potent cholesteryl ester transfer protein (CETP) inhibitor that is being developed for dyslipidemia. Even though CKD-519 has shown potent CETP inhibition, the exposure of CKD-519 was highly varied, depending on food and dose. For highly variable exposure drugs, it is crucial to use modeling and simulation to plan proper dose selection. This study aimed to develop population pharmacokinetic (PK) and pharmacodynamics (PD) models of CKD-519 and to predict the proper dose of CKD-519 to achieve target levels for HDL-C and LDL-C using results from multiple dosing study of CKD-519 with a standard meal for two weeks in healthy subjects. The results showed that a 3-compartment with Erlang’s distribution, followed by the first-order absorption, adequately described CKD-519 PK, and the bioavailability, which decreased by dose and time was incorporated into the model (NONMEM version 7.3). After the PK model development, the CETP activity and cholesterol (HDL-C and LDL-C) levels were sequentially modeled using the turnover model, including the placebo effect. According to PK-PD simulation results, 200 to 400 mg of CKD-519 showing a 40% change in HDL-C and LDL-C from baselines was recommended for proof of concept studies in patients with dyslipidemia.

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Sady, S. P., R. C. Hanumara, and P. N. Herbert. "Mathematical models of the relationship between HDL-Cholesterol and Serum Triglyceride: an empirical evaluation." Mathematical and Computer Modelling 12, no. 9 (1989): 1103–12. http://dx.doi.org/10.1016/0895-7177(89)90231-8.

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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23810.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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Lai, Cheng-Tsung, Wangqiang Sun, Rohun U. Palekar, C. Shad Thaxton, and George C. Schatz. "Molecular Dynamics Simulation and Experimental Studies of Gold Nanoparticle Templated HDL-like Nanoparticles for Cholesterol Metabolism Therapeutics." ACS Applied Materials & Interfaces 9, no. 2 (January 5, 2017): 1247–54. http://dx.doi.org/10.1021/acsami.6b12249.

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Arshak, K., E. Jafer, D. McDonagh, and C. S. Ibala. "Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulink® mixed environment." IET Computers & Digital Techniques 1, no. 5 (2007): 508. http://dx.doi.org/10.1049/iet-cdt:20050206.

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Baszyński, Marcin. "Low cost, high accuracy real-time simulation used for rapid prototyping and testing control algorithms on example of BLDC motor." Archives of Electrical Engineering 65, no. 3 (September 1, 2016): 463–79. http://dx.doi.org/10.1515/aee-2016-0034.

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AbstractThis article presents the simulation of a BLDC motor and its closed control system in FPGA. The simulation is based on a mathematical model of the motor, including the electromagnetic torque, phase currents, back electromotive force, etc. In order to ensure calculation precision, the equations describing the motor were solved using a floating point representation of real numbers, and a small step of numerical calculations of 1 μs was assumed. The time step selection methodology has been discussed in detail. The motor model was executed with the use of Textual Programming Languages (with HDL codes).

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Zhang, Ming, Hao Ting Liu, and Yu Wang. "The Design of the Multifunctional Electronic Timing System Based on the Verilog HDL Language." Applied Mechanics and Materials 182-183 (June 2012): 763–67. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.763.

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Verilog is the most widely used hardware description language. It can be used in the modeling, synthesis, and simulation stages of the hardware system designing. This thesis is about applying Verilog HDL to design the multifunctional electronic timing system. This system has brought about the timing function, the Alarm clock function, the time checking module, the stop clock module, the exact hour alarming module, the alarm clock’s shielding and alarming function module and the stop clock Prompting function module. The modules which have applied this design can be transplanted to other kinds of electronic control systems conveniently. This system uses the Verilog HDL to design, so it has nothing to do with the craft. It allows us to attain the applicable actual circuit easily without considering much about the details of the gate level and the realization of the craft in the function designing stage and the logic verification stage. We just need to exert different conditions according to the demand of the design of the system.

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Abi Younes, G., and N. El Khatib. "Mathematical modeling of atherogenesis: Atheroprotective role of HDL." Journal of Theoretical Biology 529 (November 2021): 110855. http://dx.doi.org/10.1016/j.jtbi.2021.110855.

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31

Wang, Kaiyu, Zhenan Tang, Zhiming Song, and Yongrui Zhang. "Verilog HDL optimisation design and simulation for modified inversionless Berlerkamp-Massey algorithm and the multiplier over canonical field." International Journal of Mobile Network Design and Innovation 5, no. 1 (2013): 51. http://dx.doi.org/10.1504/ijmndi.2013.057148.

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Leela Rani, V., and M. Madhavi Latha. "Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits." International Journal of Electronics and Telecommunications 62, no. 2 (June 1, 2016): 179–86. http://dx.doi.org/10.1515/eletel-2016-0025.

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Abstract Leakage power is the dominant source of power dissipation in nanometer technology. As per the International Technology Roadmap for Semiconductors (ITRS) static power dominates dynamic power with the advancement in technology. One of the well-known techniques used for leakage reduction is Input Vector Control (IVC). Due to stacking effect in IVC, it gives less leakage for the Minimum Leakage Vector (MLV) applied at inputs of test circuit. This paper introduces Particle Swarm Optimization (PSO) algorithm to the field of VLSI to find minimum leakage vector. Another optimization algorithm called Genetic algorithm (GA) is also implemented to search MLV and compared with PSO in terms of number of iterations. The proposed approach is validated by simulating few test circuits. Both GA and PSO algorithms are implemented in Verilog HDL and the simulations are carried out using Xilinx 9.2i. From the simulation results it is found that PSO based approach is best in finding MLV compared to Genetic based implementation as PSO technique uses less runtime compared to GA. To the best of the author’s knowledge PSO algorithm is used in IVC technique to optimize power for the first time and it is quite successful in searching MLV.

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Zheng, Li Kun, Ya Li Chen, and Zhe Ying Li. "Design and Implementation of USB Transceiver with Verilog." Applied Mechanics and Materials 462-463 (November 2013): 604–8. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.604.

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The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.

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Yang, Yong Bin, Xue Hui Han, and Li Hong Lei. "Design of the Data Acquisition System Based on FPGA." Applied Mechanics and Materials 513-517 (February 2014): 4382–86. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4382.

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A data acquisition system is designed based on the datasheet of ICL7135 and EP2C5Q208C8. According to the characteristic of ICL7135, Verilog HDL language program and the software of QuartusII are used to simulate each function modules. The analysis of simulation results and experiment show that using the method of FPGA+A/D can simplify the complexity of the system design and possess a very high accuracy on the treatment effect.

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Gao, Li, Runmei Zhang, and Guangbin Zhang. "Development of Intelligent Building Energy-saving Temperature Control System Based on FPGA." E3S Web of Conferences 136 (2019): 02033. http://dx.doi.org/10.1051/e3sconf/201913602033.

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The ideal energy-saving building should meet the environmental quality of living space in different seasons with the least energy consumption. The indoor temperature of the building is an important consideration. However, most temperature control systems have certain problems. In order to improve the stability and accuracy of the temperature control system, a system based on FPGA+Verilog HDL for intelligent adjustment of indoor temperature is designed. The purpose of the system design is to achieve the dual effect of comfortable and energy-saving living environment. The system uses an integrated temperature sensor DS18B20 as a temperature sensing element. FPGA as the master control center to process data. The system is programmed with the hardware description language Verilog HDL. The temperature control system uses a digital PID control algorithm. The simulation results verify the correctness of the design.

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Xu, Fei, Hui Yu, Cai Lu, Jun Chen, and Wei Gu. "The Cholesterol-Lowering Effect of Alisol Acetates Based on HMG-CoA Reductase and Its Molecular Mechanism." Evidence-Based Complementary and Alternative Medicine 2016 (2016): 1–11. http://dx.doi.org/10.1155/2016/4753852.

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This study measured the impact of alisol B 23-acetate and alisol A 24-acetate, the main active ingredients of the traditional Chinese medicine Alismatis rhizoma, on total cholesterol (TC), triglyceride (TG), high density lipoprotein-cholesterol (HDL-C), and low density lipoprotein-cholesterol (LDL-C) levels of hyperlipidemic mice. The binding of alisol B 23-acetate and alisol A 24-acetate to the key enzyme involved in the metabolism of TC, 3-hydroxy-3-methylglutary-coenzyme A (HMG-CoA) reductase, was studied using the reagent kit method and the western blotting technique combined with a molecular simulation technique. According to the results, alisol acetates significantly lower the TC, TG, and LDL-C concentrations of hyperlipidemic mice, while raising HDL-C concentrations. Alisol acetates lower HMG-CoA reductase activity in a dose-dependent fashion, both in vivo and in vitro. Neither of these alisol acetates significantly lower the protein expression of HMG-CoA. This suggests that alisol acetates lower the TC level via inhibiting the activity of HMG-CoA reductase by its prototype drug, which may exhibit an inhibition effect via directly and competitively binding to HMG-CoA. The side chain of the alisol acetate was the steering group via molecular simulation.

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Das, SunilR, Dhruv Biswas, EmilM Petriu, MansourH Assaf, and SatyendraN Biswas. "System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL." IETE Journal of Research 58, no. 2 (2012): 107. http://dx.doi.org/10.4103/0377-2063.96177.

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Ruan, A. W., C. Q. Li, Z. J. Song, and W. C. Li. "SOC HW/SW co‐verification based debugging technique." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 32, no. 2 (March 1, 2013): 545–55. http://dx.doi.org/10.1108/03321641311296936.

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PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

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Yang, Yu, and Chao Zhang. "Research and Realization of Key Algorithm of ADS-B Overlapping Test." Advanced Materials Research 403-408 (November 2011): 1555–59. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1555.

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How to recognize the ADS-B messages is the key point of ADS-B receiver, and the preamble is the unique character of ADS-B messages. This paper describes a method for the overlapping test of the preamble detection. The FPGA implementation scheme is given in detail and the verilog HDL codes of this design is accomplished. The simulation result indicates that this method is viable and can detect the overlapping rapidly and accurately.

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Dash, Raju, Md Chayan Ali, Md Liton Rana, Yeasmin Akter Munni, Largess Barua, Israt Jahan, Mst Fatema Haque, Md Abdul Hannan, and Il Soo Moon. "Computational SNP Analysis and Molecular Simulation Revealed the Most Deleterious Missense Variants in the NBD1 Domain of Human ABCA1 Transporter." International Journal of Molecular Sciences 21, no. 20 (October 14, 2020): 7606. http://dx.doi.org/10.3390/ijms21207606.

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The ATP-binding cassette transporter A1 (ABCA1) is a membrane-bound exporter protein involved in regulating serum HDL level by exporting cholesterol and phospholipids to load up in lipid-poor ApoA-I and ApoE, which allows the formation of nascent HDL. Mutations in the ABCA1 gene, when presents in both alleles, disrupt the canonical function of ABCA1, which associates with many disorders related to lipid transport. Although many studies have reported the phenotypic effects of a large number of ABCA1 variants, the pathological effect of non-synonymous polymorphisms (nsSNPs) in ABCA1 remains elusive. Therefore, aiming at exploring the structural and functional consequences of nsSNPs in ABCA1, in this study, we employed an integrated computational approach consisting of nine well-known in silico tools to identify damaging SNPs and molecular dynamics (MD) simulation to get insights into the magnitudes of the damaging effects. In silico tools revealed four nsSNPs as being most deleterious, where the two SNPs (G1050V and S1067C) are identified as the highly conserved and functional disrupting mutations located in the NBD1 domain. MD simulation suggested that both SNPs, G1050V and S1067C, changed the overall structural flexibility and dynamics of NBD1, and induced substantial alteration in the structural organization of ATP binding site. Taken together, these findings direct future studies to get more insights into the role of these variants in the loss of the ABCA1 function.

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Yue, Ya Jie, Chen Ming Sha, and Xiao Jing Zhang. "Design of OLED Controlling Circuit Based on FPGA." Applied Mechanics and Materials 427-429 (September 2013): 1196–200. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1196.

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Organic light-emitting diode (OLED) has many advantages such as ultra light, ultra thin, high brightness, high definition, self-luminous, wide angle, quick response.It quickly attracts peoples attention to make one of today's hottest panel display subject. Based on the characteristics and working principle of OLED, the OLED display controlling circuit using the decoding module of DSP and controlling module of FPGA is designed.According to it,the use of each module in the circuit and the working process of the whole circuit are analysed.The simulations and tests are done.Verilog HDL is used to design the controlling circuit in the whole system and a top-down design method is used which is penetrated into each layer from top to bottom and devided carefully.The simulation results show that the gray scale display of OLED can be achieved and better display performance is obtained.

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Meng, Yang Yang, Xiao Dong Hu, and Dong Lai Yang. "Piecewise Linear Response Based on CMV4000 Image Sensor." Applied Mechanics and Materials 568-570 (June 2014): 568–72. http://dx.doi.org/10.4028/www.scientific.net/amm.568-570.568.

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With high speed CMOS image sensor CMV4000 produced by CMOSIS company as the object, after the thorough analysis of the piecewise linear response principle and how to extend the dynamic range, using piecewise linear response extends the dynamic range of CMV4000 image sensor. The ideas and methods of using the finite state machine designs piecewise linear response sequence are given, and the function simulation is done for the sequence in the Quartus II 9.0 environment using the Verilog HDL hardware description language. Through the analysis of simulation results, it can satisfy the demands of piecewise linear response sequence. The method is simple and feasible, and can improve the optical dynamic range of CMV4000 image sensor.

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Narendran, S., and J. Selvakumar. "Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling." Advances in Condensed Matter Physics 2018 (May 27, 2018): 1–5. http://dx.doi.org/10.1155/2018/2683723.

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We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Through our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to find which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the supply input in the range of 0-10 volts. Using HDL language, we made a memory logic design of RAM cells using Josephson Junction in FreeHDL software which is dedicated only for Josephson Junction based design. With use of XILINX, we have calculated the power consumption and equivalent Register Transfer Level (RTL) schematic is drawn.

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Li, Zhao, and Lei Xu. "Design of Driving Circuit of Area Array CCD with Interline Transfer Based on FPGA." Advanced Materials Research 860-863 (December 2013): 2365–68. http://dx.doi.org/10.4028/www.scientific.net/amr.860-863.2365.

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In this paper, FPGA is chosen as the hardware design platform, on the base of sufficient analysis of ICX204AL's working principle and driving timing, the driving timing of CCD is described with Verilog HDL in the development environment of QuartusII 9.0. Finally, Modelsim SE 6.4a is employed to carry on the simulation to verify the accuracy of the design. The result shows that the driving circuit design can meet the demands of ICX204AL, and the CCD can work stably.

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Yu, Qun Xiu, Shou Ming Zhang, Chao Wang, and Li Zhi Xie. "Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking." Applied Mechanics and Materials 734 (February 2015): 621–24. http://dx.doi.org/10.4028/www.scientific.net/amm.734.621.

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In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (April 1, 2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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PCI Express is a high-speed serial connection that operates more like a network than a bus. PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms. PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function of Transaction layer IP core in the System Level with top-down design method, wrote the codes to implement Transaction Layer using Very high speed hardware description language (VHDL) and provided the simulation results using Active HDL Simulation tool. The simulation result shows that the designed IP core meets the required protocol specifications for the proper functioning of PCI Express Transaction layer.

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Jie, Zhao, Fei Yu, Jing Xia Wang, and Liu Li. "Design and Implementation of RAM Operation Conflict Arbiter IC in LED/LCD Display Control System." Applied Mechanics and Materials 268-270 (December 2012): 1574–77. http://dx.doi.org/10.4028/www.scientific.net/amm.268-270.1574.

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To solve the writing and reading operation conflict to RAM in LED/LCD display control system, a new RAM operation conflict arbiter IC was proposed. Comparing the traditional dual ports RAM, the IC has the advantages of low-cost and high stability. By analyzing the working principle and structure design, the IC was designed in pure digital way with Verilog HDL, and passed the simulation verify. Finally the IC was realized by Alter FPGA chip and passed the actual test.

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Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.

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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

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R. Faezal, S. F., M. N. Isa, S. Taking, S. N. Mohyar, A. B. Jambek, and A. Harun. "Design of on-chip temperature-based digital signal processing for customized wireless microcontroller." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 653. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp653-660.

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Dramatic rises in power density and die sizes inside system-on-chip (SoC) design have led to the thermal issue. High temperatures or uneven temperature distributions may result not only in reliability issues, also has become the biggest issue that can limit the system performance. This paper presents the design and simulation of a temperature-based digital signal processing unit for modern system-on-chip design using the Verilog HDL. This design provides continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Synopsys Software. The result showed that temperature monitoring process is within the temperature range due to the incorporation of an interrupt-based system and with an advantage of minimum chip area required.

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Jin, Lin, and Qiang Liu. "Study on Mechanical and Electrical Automation with System Design of Frequency Meter Based on EDA Technology." Applied Mechanics and Materials 387 (August 2013): 356–59. http://dx.doi.org/10.4028/www.scientific.net/amm.387.356.

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Frequency meter as a kind of electronic measuring instruments, have been widely applied in the field of Mechanical and Electrical automation. The design of a frequency meter based on EDA technology, is implemented in EDA software platform of Quartus II, using hardware description language (HDL) editor can also be seasonal schematic, design, system hardware circuit compiler, simulation, system is divided into five modules: frequency module, control module, counting module, range switching module and display module, the hardware design requires a download chip EPM7128S and input and output circuit.

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Journal articles on the topic 'Simulation HDL'

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