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Journal articles on the topic 'Simulation SENTAURUS-TCAD'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

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<p>As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10<sup>7 &l

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Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents method

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Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

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This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge term

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Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design an

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Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results

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Phetchakul, Toempong, Wittaya Luanatikomkul, Chana Leepattarapongpan, E. Chaowicharat, Putapon Pengpad, and Amporn Poyai. "The Study of p-n and Schottky Junction for Magnetodiode." Advanced Materials Research 378-379 (October 2011): 663–67. http://dx.doi.org/10.4028/www.scientific.net/amr.378-379.663.

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This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.

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Palomo, F. R., P. Fernández-Martínez, J. M. Mogollón, et al. "Simulation of femtosecond pulsed laser effects on MOS electronics using TCAD Sentaurus customized models." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 23, no. 4-5 (2010): 379–99. http://dx.doi.org/10.1002/jnm.736.

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Salemi, Arash, Benedetto Buono, Anders Hallén, et al. "Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC." Materials Science Forum 778-780 (February 2014): 836–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.836.

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10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VFof 3.3 V at 100 A/cm2at 25°C, which was decreased to 3.0 V at 300°C.

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Zhu, Shunwei, Hujun Jia, Tao Li, et al. "Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer." Micromachines 10, no. 7 (2019): 444. http://dx.doi.org/10.3390/mi10070444.

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A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdo

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Jaikumar, M. G., and Shreepad Karmalkar. "Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs." Materials Science Forum 717-720 (May 2012): 1101–4. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1101.

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4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering

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Khalid, Muhammad, Waseem Raza, Saira Riaz, and Shahzad Naseem. "Simulation and Analysis of Static and Dynamic Performance of Normally-off TIVJFET Using Sentaurus TCAD." Materials Today: Proceedings 2, no. 10 (2015): 5720–25. http://dx.doi.org/10.1016/j.matpr.2015.11.117.

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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.

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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter

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Koptev, N. S., and A. A. Pugachev. "TCAD-ASSISTED TECHNIQUE FOR DETERMINING THE PARAMETERS OF MICROLENSES USED IN PHOTOSENSITIVE CCD VLSI." Electronic engineering Series 2 Semiconductor devices 257, no. 2 (2020): 28–36. http://dx.doi.org/10.36845/2073-8250-2020-257-2-28-36.

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In this paper we introduce the simulation technique for photosensitive cell with CCD VLSI microlens with interline transfer. A microlens enhances the photosensitivity of the cell and reduces image blur. The technique is based on the calculation and comparison of the volumetric photogeneration rate integrals of different areas of the photocell, where generated charge carriers are collected and transferred. This technique does not require simulation of the full frame accumulation cycle of the cell, significantly reducing the time of simulation and enabling the evaluation of many design options f

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Salemi, Arash, Hossein Elahipanah, Carl Mikael Zetterling, and Mikael Östling. "10+ kV Implantation-Free 4H-SiC PiN Diodes." Materials Science Forum 897 (May 2017): 423–26. http://dx.doi.org/10.4028/www.scientific.net/msf.897.423.

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Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The d

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Li, Han, Chen Wang, Lin Chen, Hao Zhu, and Qingqing Sun. "A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation." Electronics 8, no. 10 (2019): 1198. http://dx.doi.org/10.3390/electronics8101198.

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Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Compute

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Yang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu, and Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology." MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.

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High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also

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Patil, Kalawati, and B. K. Mishra. "Dielectric Dependent Absorption Characteristics in CNFET Infrared Phototransistor." International Journal of Engineering and Technologies 19 (December 2020): 11–21. http://dx.doi.org/10.18052/www.scipress.com/ijet.19.11.

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In future infrared photodetectors, single-walled carbon nanotubes (SWCNTs) are considered as potential candidates due to their band gap, high absorption coefficient (104 - 105 cm −1), high charge carrier mobility and ease of processability. The SWCNT based Field Effect Transistors (CNFETs) are being seriously considered for applications in optoelectronics. In the proposed work optically controlled back gated CNFET is modeled in Sentaurus TCAD to observe the impact of high dielectric oxides on its photoabsorption. The model is based on analytical approximations and parameters extracted from qua

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Wang, You, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang, and Hai Lin. "Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET." Electronics 10, no. 4 (2021): 454. http://dx.doi.org/10.3390/electronics10040454.

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure curre

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Adak, Sarosij, and Sanjit Kumar Swain. "Impact of High-K Dielectric Materials on Performance Analysis of Underlap In0.17Al0.83N/GaN DG-MOSHEMTs." Nano 14, no. 05 (2019): 1950060. http://dx.doi.org/10.1142/s1793292019500607.

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This work systematically investigated the effect of high-[Formula: see text] oxide materials on the performance of InAlN/GaN heterostructure underlap double gate (DG) MOS-HEMTs by considering 2D Sentaurus TCAD simulation. During the course of simulation, hydrodynamic mobility model was implemented and the obtained results were used for validating the model with the previously published experimental results. Different device performance parameters are thoroughly studied for different high-[Formula: see text] oxide materials by performing extensive simulations. It is verified that short channel

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Gan, Lu-Rong, Ya-Rong Wang, Lin Chen, Hao Zhu, and Qing-Qing Sun. "A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications." Micromachines 10, no. 9 (2019): 558. http://dx.doi.org/10.3390/mi10090558.

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We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO2 high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the b

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Dehzangi, Arash, Farhad Larki, Sawal Hamid Md Ali, et al. "Study of the side gate junctionless transistor in accumulation region." Microelectronics International 33, no. 2 (2016): 61–67. http://dx.doi.org/10.1108/mi-03-2015-0027.

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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transf

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Wang, Ying, Chan Shan, Wei Piao, et al. "3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance." Micromachines 9, no. 12 (2018): 659. http://dx.doi.org/10.3390/mi9120659.

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In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simul

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Choi, Yejoo, Jinwoong Lee, Jaehyuk Lim, Seungjun Moon, and Changhwan Shin. "Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET." Electronics 10, no. 16 (2021): 1899. http://dx.doi.org/10.3390/electronics10161899.

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In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS

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Palacios A., César, Noemi Guerra, Marco Guevara, and María José López. "TCAD 2D numerical simulations for increasing efficiency of AlGaAs – GaAs Solar Cells." I+D Tecnológico 14, no. 2 (2018): 96–107. http://dx.doi.org/10.33412/idt.v14.2.2078.

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The performance of solar cells has improved quickly in recent years, the latest research focuses on thin cells, multijunction cells, solar cells of the group III-V compounds, Tandem cells, etc. In the present work, numerical simulations are developed, using SENTAURUS TCAD as a tool, in order to obtain a solar cell model based on Galium Arsenide (GaAs). This solar cell corresponds to the so-called "Thin Films" due to the fact that can make layers thinner than we would have if we work with conventional semiconductors, such as; Silicon or Germanium; thus opening the possibility of placing the cel

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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, et al. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.

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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of

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Adak, Sarosij, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, and Chandan Kumar Sarkar. "Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs." Nano 12, no. 01 (2017): 1750009. http://dx.doi.org/10.1142/s1793292017500096.

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In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-o

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Zhu, Shunwei, Hujun Jia, Xingyu Wang, et al. "Improved MRD 4H-SiC MESFET with High Power Added Efficiency." Micromachines 10, no. 7 (2019): 479. http://dx.doi.org/10.3390/mi10070479.

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An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device i

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Chakraborty, Chaitali, and Chayanika Bose. "Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures." Journal of Advanced Dielectrics 06, no. 01 (2016): 1650001. http://dx.doi.org/10.1142/s2010135x16500016.

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The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due

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Rodríguez, Raúl, Benito González, Javier García, Gaetan Toulon, Frédéric Morancho, and Antonio Núñez. "DC Gate Leakage Current Model Accounting for Trapping Effects in AlGaN/GaN HEMTs." Electronics 7, no. 10 (2018): 210. http://dx.doi.org/10.3390/electronics7100210.

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A DC leakage current model accounting for trapping effects under the gate of AlGaN/GaN HEMTs on silicon has been developed. Based on TCAD numerical simulations (with Sentaurus Device), non-local tunneling under the Schottky gate is necessary to reproduce the measured transfer characteristics in a subthreshold regime. Once the trap concentration and distribution are determined in the device, the resulting gate leakage current is modeled making use of Verilog-A, for typical operation regimes.

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Nipoti, Roberta, Giovanna Sozzi, Maurizio Puzzanghera, and Roberto Menozzi. "Al+ implanted vertical 4H-SiC p-i-n diodes: experimental and simulated forward current-voltage characteristics." MRS Advances 1, no. 54 (2016): 3637–42. http://dx.doi.org/10.1557/adv.2016.315.

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ABSTRACT The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may jus

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Nguyen, Thi Thanh Huyen, Mihai Lazar, Jean Louis Augé, Hervé Morel, Luong Viet Phung, and Dominique Planson. "Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications." Materials Science Forum 858 (May 2016): 982–85. http://dx.doi.org/10.4028/www.scientific.net/msf.858.982.

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Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT2 technique increases the breakdown voltage (VBR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT2 used for a 3 kV 4H-SiC bipola

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Ke, Haotao, Yifan Jiang, Adam J. Morgan, and Douglas C. Hopkins. "Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors." International Symposium on Microelectronics 2017, no. 1 (2017): 000224–30. http://dx.doi.org/10.4071/isom-2017-wa32_092.

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Abstract The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-fi

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"Simulation photoelectric parameters of vertical junction solar cells." International Journal of Advanced Trends in Computer Science and Engineering 10, no. 2 (2021): 543–48. http://dx.doi.org/10.30534/ijatcse/2021/131022021.

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Many properties of the solar cells are being studied extensively. In this study, the basic photoelectric parameters of vertical junction solar cell were modeled. Attempts were made to approach the scientific work both physically and programmatically. In terms of programming, a perfect algorithm has been developed for modeling vertical junction solar cell in the Sentaurus TCAD software package. Using this algorithm, a vertical junction solar cell was modeled. The main focus was on the comparison of the photoelectric parameters of a vertical junction solar cell consisting of 3 elements with the

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Lee, Mankoo, Dipankar Pramanik, Haifan Liang, Ed Korczynski, and Jeroen van Duren. "Optimization of Graded CIGS Solar Cells Using TCAD Simulations." MRS Proceedings 1447 (2012). http://dx.doi.org/10.1557/opl.2012.1167.

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ABSTRACTTo understand paths towards higher efficiency (η) for copper-indium-gallium-(sulfur)-selenide [CIG(S)Se] solar cells, we investigated a variety of absorber composition grading schemes for various back-side gallium (Ga), front-side sulfur (S), and double-graded Ga composition depth profiles in TCAD 1D/2D simulations. We fitted experimental results of a Back-Side Graded (BSG) solar cell with our TCAD models, prior to investigating other grading and interface schemes. The BSG solar cell was fabricated on a High Productivity Combinatorial (HPC™) platform based on sputtering Cu(In,Ga) follo

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"Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator." International Journal of Innovative Technology and Exploring Engineering 8, no. 12S2 (2019): 61–66. http://dx.doi.org/10.35940/ijitee.l1012.10812s219.

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This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at ch

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Geißendörfer, Stefan, Karsten von Maydell, and Carsten Agert. "Numerical 3D-Simulation of Micromorph Silicon Thin Film Solar Cells." MRS Proceedings 1321 (2011). http://dx.doi.org/10.1557/opl.2011.934.

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ABSTRACTIn this contribution 1, 2 and 3-dimensional simulations of micromorph silicon solar cells are presented. In order to simulate solar cells with rough interfaces, the surface topographies were measured via atomic force microscopy (AFM) and transferred into the commercial software Sentaurus TCAD (Synopsys). The model of the structure includes layer thicknesses and optoelectronic parameters like complex refractive index and defect structure. Results of the space resolved optical generation rates by using of the optical solver Raytracer are presented. The space resolved optical generation r

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Yahya, Erman Azwan, Ramani Kannan, and Lini Lee. "Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation." Bulletin of Electrical Engineering and Informatics 8, no. 4 (2019). http://dx.doi.org/10.11591/eei.v8i4.1611.

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High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of thi

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Li, Joel B., and Bruce M. Clemens. "Modeling the Performance of Biaxially-Textured Silicon Solar Cells." MRS Proceedings 1670 (2014). http://dx.doi.org/10.1557/opl.2014.590.

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ABSTRACTGrain boundaries (GBs) in polycrystalline silicon (poly-Si) thin film solar cells are frequently found to be detrimental for device performance. Biaxiallytextured silicon with grains that are well-aligned in-plane and out-of-plane can possess fewer GB defects. In this work, we use TCAD Sentaurus device simulator and known experimental work to investigate and quantify the potential performance gains of biaxially-textured silicon. Simulation shows there can be performance gain from well-aligned grains when GB defects dominate carrier recombination or when grains are small. On the other h

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Lee, Mankoo, Xuena Zhang, and Dipankar Pramanik. "Analysis of Cu-Line EM Failure Kinetics Using Mass Transport TCAD Simulations." MRS Proceedings 1559 (2013). http://dx.doi.org/10.1557/opl.2013.870.

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ABSTRACTWe describe a mass transport TCAD simulation by using a Sentaurus S-Interconnect tool [1] that models reported electro-migration (EM) behaviors: EM induced resistance (R) change, line length (L) effect, and temperature (T) dependency on L and current density (j) products. We performed trend and sensitivity analyses for key physical EM model parameters: Cu-void formation, a sudden jump in line R associated with void growth, and Cu-vacancy (Cv) and void (Cvoid) profiles. In this manner, we develop a new methodology for accurately determining the EM lifetime by identifying an “EM-aware” r

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Morozzi, Arianna, Francesco Moscatelli, Tommaso Croci, and Daniele Passeri. "TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review." Frontiers in Physics 9 (February 2, 2021). http://dx.doi.org/10.3389/fphy.2021.617322.

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A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on

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Michalak, Tyler J., Chris Borst, Dan Franca, Josh Herman, and Martin Rodgers. "Simulation of Millisecond Laser Anneal on SOI: A Study of Dopant Activation and Mobility and its Application to Scaled FinFET Thermal Processing." MRS Proceedings 1562 (2013). http://dx.doi.org/10.1557/opl.2013.825.

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ABSTRACTThis work investigates scanning laser annealing used for ultra-shallow junction (USJ) activation. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scans across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to enhance the absorption of incident energy and reduce SOI reflectivity. An effective absorption coefficient of α=8000cm-1 was ca

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Tang, Zhenyu, Xiaoyan Tang, Shi Pu, et al. "Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET." Circuit World ahead-of-print, ahead-of-print (2021). http://dx.doi.org/10.1108/cw-12-2020-0351.

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Purpose To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required. Design/methodology/approach In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an acc

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Vyšniauskas, Juozas, and Eugenijus Gaubas. "Simulation of dynamic characteristics of GaN p-i-n avalanche diode operating as particle detector with internal gain." Lithuanian Journal of Physics 58, no. 2 (2018). http://dx.doi.org/10.3952/physics.v58i2.3747.

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An evolution of the transient characteristics of the GaN p-i-n diodes, operating in the avalanche mode and acting as particle sensors, has been simulated by using the Synopsys TCAD Sentaurus software package and the drift-diffusion approach. Profiling of the charge generation, recombination and drift-diffusion processes has been performed over a nanosecond time-scale with a precision of a few picoseconds and emulated through the photo-excitation of an excess carrier domain at different locations of the active volume of a diode. Shockley–Read–Hall (SRH), Auger and radiative recombination proces

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"Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (2019): 1446–50. http://dx.doi.org/10.35940/ijitee.a4244.119119.

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To solve the problems of high temperature microelectronics the influence of the self heating effect on the IV dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI C

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"Performance Analysis of Double Gate Hetero Junction Tunnel Fet." International Journal of Innovative Technology and Exploring Engineering 9, no. 2S3 (2019): 232–34. http://dx.doi.org/10.35940/ijitee.b1058.1292s319.

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In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is

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"Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (2019): 284–88. http://dx.doi.org/10.35940/ijitee.h7236.078919.

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Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Si

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