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Alali, Oussama. "Modélisation VHDL-AMS analogique et simulation SPICE /." Paris : École nationale supérieure des télécommunications, 1998. http://catalogue.bnf.fr/ark:/12148/cb367111244.
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Mitter, Chang Su. "Insulated gate bipolar transistor (IGBT) simulation using IG-Spice." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020115/.
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Leung, Hong Man. "SPICE simulation and modeling of DC-DC flyback converter." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36643.
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Badcock, Stephen G. "Viability study of SiGe/Si heterojunction MOSFET technology by computer simulation." Thesis, University of Newcastle Upon Tyne, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.324925.
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Bonhomme, Phillip. "Circuit modeling of spintronic devices: a SPICE implementation." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51818.
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Every engineer that has worked on designing an integrated circuit has to leverage an under- standing of device physics. Understanding device physics is essential when optimizing a design for speed, power, etc. These characteristics affect the bottom line when considering an integrated circuit used in a particular application. In order for there to be an under- standing of device physics, there must be a device model that is developed for a device of interest. The development of a device model often involves utilizing fundamental physical equations in a manner that is solvable by either analytical or numerical means.
This typically begins by simplifying fundamental physical equations, possibly spanning multiple domains, and considering the physical quantities of interest. In order to make simplifications, assumptions about the underlying physics must be made. It is the process of transitioning from known physics laws to simplified mathematical models that a device modeler spans.
This thesis will cover the device modeling aspects of a new classification of computing devices, spintronics. It will begin by stating the physical assumptions necessary for the operation of spintronic devices. Then it will go the process of deriving the underlying physical equations and stating them in a tractable form with the appropriate boundary conditions. Then these equations will be manipulated and mapped into an equivalent circuit. The equivalent circuits will them be validated against analytical solutions provided from other works. It will then finish by providing example devices that can be simulated with the develop device models, and some optimization results are proposed based off a simplified circuit model.
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Yen, Wen-Tsung. "Comparison of SPICE and Network C simulation models using the CAM system." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4243.
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The performance of SPICE and Network C (NC) circuit simulator when simulating MOS transistor circuits has been investigated and compared. SPICE analog model, NC analog model and NC MOS_PWL model are the three MOS transistor models being used. The comparison between SPICE and NC includes five areas. They are MOS transistor model, circuit analysis and computational methods, limitation on the ability to simulate circuits containing the MOS transistor diode configuration, run time and the ability to build new circuit component models using derived equations.
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Stein, Félix. "SPICE Modeling of TeraHertz Heterojunction bipolar transistors." Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0281/document.
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Les études qui seront présentées dans le cadre de cette thèse portent sur le développement et l’optimisation des techniques pour la modélisation compacte des transistors bipolaires à hétérojonction (TBH). Ce type de modélisation est à la base du développement des bibliothèques de composants qu’utilisent les concepteurs lors de la phase de simulation des circuits intégrés. Le but d’une technologie BiCMOS est de pouvoir combiner deux procédés technologiques différents sur une seule et même puce. En plus de limiter le nombre de composants externes, cela permet également une meilleure gestion de la consommation dans les différents blocs digitaux, analogiques et RF. Les applications dites rapides peuvent ainsi profiter du meilleur des composants bipolaires et des transistors CMOS. Le défi est d’autant plus critique dans le cas des applications analogiques/RF puisqu’il est nécessaire de diminuer la puissance consommée tout en maintenant des fréquences de fonctionnement des transistors très élevées. Disposer de modèles compacts précis des transistors utilisés est donc primordial lors de la conception des circuits utilisés pour les applications analogiques et mixtes. Cette précision implique une étude sur un large domaine de tensions d’utilisation et de températures de fonctionnement. De plus, en allant vers des nœuds technologiques de plus en plus avancés, des nouveaux effets physiques se manifestent et doivent être pris en compte dans les équations du modèle. Les règles d’échelle des technologies plus matures doivent ainsi être réexaminées en se basant sur la physique du dispositif. Cette thèse a pour but d’évaluer la faisabilité d’une offre de modèle compact dédiée à la technologie avancée SiGe TBH de chez ST Microelectronics. Le modèle du transistor bipolaire SiGe TBH est présenté en se basant sur le modèle compact récent HICUMversion L2.3x. Grâce aux lois d’échelle introduites et basées sur le dessin même des dimensions du transistor, une simulation précise du comportement électrique et thermique a pu être démontrée.Ceci a été rendu possible grâce à l’utilisation et à l’amélioration des routines et méthodes d’extraction des paramètres du modèle. C’est particulièrement le cas pour la détermination des éléments parasites extrinsèques (résistances et capacités) ainsi que celle du transistor intrinsèque. Finalement, les différentes étapes d’extraction et les méthodes sont présentées, et ont été vérifiées par l’extraction de bibliothèques SPICE sur le TBH NPN Haute-Vitesse de la technologie BiCMOS avancée du noeud 55nm, avec des fréquences de fonctionnement atteignant 320/370GHz de fT = fmaxThe aim of BiCMOS technology is to combine two different process technologies intoa single chip, reducing the number of external components and optimizing power consumptionfor RF, analog and digital parts in one single package. Given the respectivestrengths of HBT and CMOS devices, especially high speed applications benefit fromadvanced BiCMOS processes, that integrate two different technologies.For analog mixed-signal RF and microwave circuitry, the push towards lower powerand higher speed imposes requirements and presents challenges not faced by digitalcircuit designs. Accurate compact device models, predicting device behaviour undera variety of bias as well as ambient temperatures, are crucial for the development oflarge scale circuits and create advanced designs with first-pass success.As technology advances, these models have to cover an increasing number of physicaleffects and model equations have to be continuously re-evaluated and adapted. Likewiseprocess scaling has to be verified and reflected by scaling laws, which are closelyrelated to device physics.This thesis examines the suitability of the model formulation for applicability to production-ready SiGe HBT processes. A derivation of the most recent model formulationimplemented in HICUM version L2.3x, is followed by simulation studies, whichconfirm their agreement with electrical characteristics of high-speed devices. Thefundamental geometry scaling laws, as implemented in the custom-developed modellibrary, are described in detail with a strong link to the specific device architecture.In order to correctly determine the respective model parameters, newly developed andexisting extraction routines have been exercised with recent HBT technology generationsand benchmarked by means of numerical device simulation, where applicable.Especially the extraction of extrinsic elements such as series resistances and parasiticcapacitances were improved along with the substrate network.The extraction steps and methods required to obtain a fully scalable model library wereexercised and presented using measured data from a recent industry-leading 55nmSiGe BiCMOS process, reaching switching speeds in excess of 300GHz. Finally theextracted model card was verified for the respective technology
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Angel, Nathan A. "EQUIVALENT CIRCUIT IMPLEMENTATION OF DEMYELINATED HUMAN NEURON IN SPICE." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/611.
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This work focuses on modeling a demyelinated Hodgkin and Huxley (HH) neuron with Simulated Program with Integrated Circuit Emphasis (SPICE) platform. Demyelinating disorders affect over 350,000 people in the U.S and understanding the demyelination process at the cellular level is necessary to find safe ways to treat the diseases [9]. Utilizing a previous SPICE model of an electrically small cell neuron developed by Szlavik [32], an extended core conductor myelinated neuron was produced in this work. The myelinated neuron developed has seven active Nodes of Ranvier (nodes) separated by a myelin sheath. The myelin sheath can be successfully modeled with a resistive and capacitive network known as internodes. Both the Nodes of Ranvier and internode equivalent circuits were implemented in P-SPICE sub-circuit library files. Properties of the neuron can be changed in the library files to simulate neurons of different electrical or geometric properties. Using the P-SPICE code developed in this work, a myelinated neuron’s action potential was simulated and the action potential at each node was recorded. The action potential at each node was uniform in amplitude and pulse width. The conduction velocity of the action potential was calculated to be 57.15 m/s.
Demyelination can be modeled by decreasing the capacitance and increasing the resistance of the myelin [34]. Two demyelinated neuron models were simulated in this work. The first model had one internode segment demyelinated, and the second model was of three consecutive internode segments. The resulting conduction velocity was calculated for both simulations. For one and three internode segment demyelinated the conduction velocity was slowed to 44.15 m/s, and 27.15 m/s respectively. This model successfully showed that an HH neuron implemented in SPICE could show the effects of demyelination on conduction velocity
The goal of this work is to develop a demyelinated neuron so that treatments for Multiple Sclerosis (MS) and other demyelinated neurons could be simulated to test various treatments’ effectiveness. A current treatment for MS is ion channel blockers. Future work would be to use this model to test current ion channel blocker therapy and to validate if such therapies alleviate conduction slowing.
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Vu, Dinh Thanh, and Jean Chilo. "Simulation des effets de propagation couplée et dissipative sur simulateur électrique nodal (SPICE)." Grenoble INPG, 1993. http://www.theses.fr/1993INPG0101.
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Dans les circuits logiques travaillant a grande vitesse, les interconnexions entre dispositifs ou entre puces doivent etre considerees comme des lignes de transmission. La haute densite d'integration entraine une miniaturisation de ces liaisons qui engendrent des effets dissipatifs et de couplage. Ces effets sont modelises et analyses a l'aide d'un circuit equivalent original analysable par n'importe quel simulateur electrique nodal (spice ici). Les parametres de propagation et les reponses temporelles en sont deduits; les distributions de densites de courants, de densites de charges et des champs electromagnetiques sont aussi calculees. L'effet dissipatif du plan de masse, pour une geometrie donnee, est simule et l'influence de la forme du plan de masse, de la position et du nombre des acces (entree/sortie) est analysee. En utilisant spice (simulateur electrique dans lequel seul un modele de ligne isolee non dissipative existe), l'analyse du circuit equivalent des interconnexions couplees et dissipatives construit par notre methode devient simple et directe car elle ne necessite aucune transformation frequence-temps. Ce concept peut etre etendu a la simulation de circuits complets comprenant des composants passifs et actifs, lineaires et non lineaires. Notre concept permet ainsi de reunir deux outils en un, un solveur electromagnetique et un simulateur electrique
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Frank, Florian. "Effiziente Methoden zur netzwerkbasierten Modellbeschreibung für die EMV-Simulation im Automobilbereich /." Tönning ; Lübeck Marburg : Der Andere Verl, 2008. http://d-nb.info/990427889/04.
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Lemoigne, Pascal. "Simulation de la variabilité du transistor MOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10214/document.
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L’augmentation de la densité d’intégration des circuits intégrés nous a amené à étudier, dans le cadre du développement de la technologie CMOS 45 nm, les sources de variabilité inhérentes aux procédés de fabrication utilisés pour ce nœud technologique, et à en déterminer les composantes principales,dans le but ultime de permettre la simulation précise de l’impact de la variabilité technologique à la fois au niveau transistor et circuit. Après un état de l’art des sources de variabilité du transistor MOS et des moyens de simulation associés,ce travail s'est orienté sur les fluctuations d'un facteur technologique difficilement accessible à la mesure statistique qu'est le dopage canal. Ensuite le nœud 45 nm a été étudié expérimentalement via un plan d'expériences.Ceci a permis de connaitre les variations naturelles des facteurs technologiques mais surtout les sensibilités des performances électriques vis-à-vis de ces facteurs.Nous avons pu ainsi identifier les causes prépondérantes de variabilité dues au procédé.Enfin, nous proposons d’améliorer la prise en compte des déviations des facteurs process dans les simulations Monte-Carlo et pire-cas appliquées aux modèles compacts au regard de ces observations expérimentalesContinuous improvement in integrated circuits density of integration lead us to study process-induced variations in the framework of the 45 nm node, and to determine their principal contributions with the ultimate goal being to allow an accurate simulation of both transistor and circuit level variability. This work starts with a study of the state of the art of variability sources of the MOS transistor and associated simulation means. Then it focuses on the fluctuations of the channel doping, which is a difficult factor to measure statistically.After that we study the 45 nm node through a design of experiment which let us learn about natural variations of process factors but mostly about electrical performances sensitivity to those factors.Thanks to that we could identify major causes of process-induced variability at this stage of this node development. At last, with respect to those experimental results, we propose to enhance the taking in account of process variations in Monte-Carlo and corner simulations applied to compact models
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Naber, John F. "The optimization of SPICE modeling parameters utilizing the Taguchi methodology." Diss., Virginia Tech, 1992. http://hdl.handle.net/10919/38542.
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A new optimization technique for SPICE modeling parameters has been developed in this dissertation to increase the accuracy of the
circuit simulation. The importance of having accurate circuit simulation models is to prevent the very costly redesign of an
Integrated Circuit (IC). This radically new optimization technique utilizes the Taguchi method to improve the fit between measured and
simulated I-V curves for GaAs MESFETs. The Taguchi method consists of developing a Signal-to-Noise Ratio (SNR) equation that will find the optimum combination of controllable signal levels in a design or process to make it robust or as insensitive to noise as
possible. In this dissertation, the control factors are considered the circuit model curve fitting parameters and the noise is
considered the variation in the simulated I-V curves from the measured I-V curves. This is the first known application of the
Taguchi method to the optimization of IC curve fitting model parameters. In addition, this method is not technology or device dependent and can be applied to silicon devices as well. Improvements in the accuracy of the simulated I-V curve fit reaching 80% has been achieved between DC test extracted parameters and the Taguchi optimized parameters. Moreover, the computer CPU execution time of the optimization process is 96% less than a commercial optimizer utilizing the Levenberg-Marquardt algorithm (optimizing 31 FETs). This technique does a least square fit on the data comparing measured currents versus simulated currents for various combinations of SPICE parameters. The mean and standard deviation of this least squares fit is incorporated in determining the SNR, providing the best combination of parameters within the evaluated range. Furthermore, the optimum values of the parameters are found without additional simulation by fitting the response curves to a quadratic equation and finding the local maximum. This technique can easily be implemented with any simulator that utilizes simulation modeling parameters extracted from measured DC test data. In addition, two methods are evaluated to obtain the worst case modeling parameters. One method lobks at the correlation coefficients between modeling parameters and the second looks at the actual device parameters that define the +/- 30 limits of the process. Lastly, an example is given that describes the applicability of the Taguchi methodology in the design of a differential amplifier, that accounts for the effect of offset voltage.Ph. D.
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Gallardo, Saavedra Sara. "Analysis and simulation of shading effects on photovoltaic cells." Thesis, Högskolan i Gävle, Avdelningen för bygg- energi- och miljöteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-21725.
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The usage of conventional energy applications generates disproportionate emissions of greenhouse gases and the consumption of part of the energy resources available in the world. It has become an important problem which has serious effects on the climatic change. Therefore, it is crucial to reduce these emissions as much as possible. To be able to achieve this, renewable energy technologies must be used instead of conventional energy applications. Solar Photovoltaic (PV) technologies do not release greenhouse gas emissions directly and can save more than 30 million tonnes of carbon per exajoule of electricity generated relative to a natural gas turbine running at 45% efficiency. Shadowing is one of the most important aspects that affects the performance of PV systems. Consequently, many investigations through this topic are being done in order to develop new technologies which mitigate the impact of shadowing during PV production. In order to minimise the impact of shadowing it is desired to be able to predict the performance of a system with PV-modules during shadowing. In this thesis a simulation program for calculating the IV-curve for series connected PV-modules during partial shadowing has been developed and experimentally validated. PV systems modelling and simulation in LTspice environment has been presented and validated by means of a comparative analysis with the experimental results obtained in a set of tests performed in the laboratory of Gävle University. Experimental measurements were carried out in two groups. The first group corresponds with the experiments done in the string of six modules with bypass diodes while the measurements of the second group have been performed on a single PV module at HIG University. The simulation results of both groups demonstrated a remarkable agreement with the experimental data, which means that the model designed at LTspice supposes a very useful tool that can be used to study the performance of PV systems. This tool contributes to the investigations in this topic and it aims to benefit future installations providing a better knowledge of the shading problem. The master’s thesis shows an in-depth description of the required method to design a PV cell, a PV module and a PV array using LTspice IV and the input parameters as well as the needed tests to adjust the models. Moreover, it has been carried out a pedagogical study describing the effect that different shadow configurations have in the performance of solar cells. This study facilitates the understanding of the performance of PV modules under different shadowing effects. Lastly, it has also been discussed the benefits of installing some newer technologies, like DC-DC optimizers or module inverters, to mitigate the shadowing effects. The main conclusion about this topic has been that although most of the times the output power will be increased with the use of optimizers sometimes the optimizer does not present any benefits.
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Napieralska, Malgorzata. "Modélisation du transistor V. DMOS pour simulation de circuits en électronique de puissance." Toulouse, INSA, 1991. http://www.theses.fr/1991ISAT0009.
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Un modele non lineaire du transistor v. Dmos de puissance a canal court dont les elements ne dependent que des donnees physiques et technologiques du composant est presente. Par analyse des regions actives de la structure du composant en vue de l'etude des regimes de commutation, ce modele est simplifie jusqu'a une topologie compatible avec le simulateur spice. Les procedures d'acquisition de ses parametres sont precisees ainsi que les tests de validation. Une bibliotheque informatique d'interrupteurs de puissance mos, destinee a la conception des circuits de puissance est cree par caracterisation des transistors (canal n et p) couvrant les gammes de tension 50v-1000v et de courant 2a-50a. Un modele unifie du v. Dmos est ensuite propose, qui necessite pour une technologie donnee deux parametres: calibre en tension et surface de puce du silicium. Un programme etabli, base sur l'environnement hypercard (macintosh) et couple avec spice permet d'etablir les modeles de produits catalogue et creer un modele pour de nouveaux composants. Cette modelisation est completee par la prise en compte de la temperature de cristal ainsi que diverses configurations de test. Un macromodele destine a rendre compte du comportement electrique sous contraintes radiatives des v. Dmos est aussi etabli et valide par comparaison entre les resultats experimentaux et la simulation. L'elaboration d'un montage de bras de pont a base de transistors mos, et sa simulation par spice permet enfin de mettre en evidence la validite du modele dans ce type d'application en prenant en compte des problemes lies a l'existence des elements parasites dans les circuits de l'electronique de puissance
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Werner, Tony Lee 1965. "A spice enhancement for the simulation and analysis of electro-thermal interactions on integrated circuit devices." Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277863.
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Presently, the power generated by integrated circuit devices can produce significant temperature gradients across the surface of the substrate. The fluctuations to the device operating temperature alter model parameters and can adversely affect circuit operation. However, SPICE can only simulate an electrical circuit characterized by a single uniform temperature for all device elements. The following work describes TWSPICE which is an enhanced version of SPICE developed for electrical and thermal analysis. TWSPICE can accommodate individual operating temperatures for each of the resistor, diode, and bipolar junction transistor elements. Furthermore, a thermal analysis algorithm, known as the Unit Profile Method, has been incorporated within the TWSPICE code to allow iterations between electrical and thermal analyses. Therefore, TWSPICE can be utilized for simulation of electro-thermal interactions in integrated circuits and testing them under more realistic conditions. In addition, examples of application have been included.
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Li, Zhao. "SPICE-accurate iterative methods for efficient time-domain simulation of VLSI circuits with strong parasitic couplings /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5830.
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Mikkola, Esko Olavi. "Hierarchical Simulation Method for Total Ionizing Dose Radiation Effects on CMOS Mixed-Signal Circuits." Diss., The University of Arizona, 2008. http://hdl.handle.net/10150/194066.
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Total ionizing dose (TID) radiation effects modeling and simulation on digital, analog and mixed signal systems remains a significant bottle neck in the development of radiation-hardened electronics. Unverified modeling techniques and the very high computational cost with today's commercial simulation tools are among the primary hindrances to the timely hardened IC design, particularly to the design in commercially available processes. SPICE-based methods have been used for total dose radiation degradation simulations. While SPICE is effective in predicting the circuit behavior under circumstances when the electrical parameters stay constant during operation, it's not effective predicting aging behavior with gradual change with time. Behavioral modeling language, such as VHDL-AMS is needed to effectively capture the time-dependent degradation in these parameters in response to environmental stresses, such as TID radiation.This dissertation describes a method for accurate and rapid TID effect simulation of complex mixed-signal circuits. The method uses a hierarchical structure where small sub-circuits, such as voltage comparators, references, etc. are simulated using SPICE. These SPICE simulations of small circuits for multiple radiation doses are used to tune behavioral VHDL-AMS models for the sub-circuits. The created behavioral models therefore contain the electrical circuit behavior combined with the radiation response. The entire combined system is then simulated using VHDL-AMS.In a simulation experiment that was used to validate the speed and accuracy of the new method, a commercial 8-bit sub-ranging analog to digital converter netlist containing more than 2000 MOS transistors was simulated with TID models using a contemporary SPICE-based method and the new method. The new method shortened the simulation time by three orders of magnitude, while accuracy remained within reasonable limits compared to the SPICE-based method. Moreover, the automated procedures for circuit node bias monitoring, TID model replacement and result collection that are included in the simulation code of the new method decreased the "hands-on" engineering work significantly. Results from an experiment where the new TID effect simulation method was used as a hardness assurance test procedure for integrated circuits designed to be operated in radiation-harsh environments are also included in this dissertation.
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Poivey, Christian. "Methodes d'optimisation pour la cao de circuits integres : interface avec le simulateur electrique spice-pac : applications." Clermont-Ferrand 2, 1987. http://www.theses.fr/1987CLF2D203.
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La conception des circuits integres consiste a determiner des valeurs acceptables des parametres afin de satisfaire certains criteres de fonctionnement du circuit donne par sa topologie. Le probleme est reformule en un probleme non lineaire a plusieurs dimensions avec contraisntes. Les fonctions a minimiser et les contraintes dependent implicitement des parametres d'optimisation par les equations du circuit, ce qui exige une simulation complete pour obtenir l'evaluation de la fonction. Les methodes du gradient et hessienne ne conviennent pas. La methode du simplex de nelder et head adjointe a une methode de recherche globale des meilleurs points d'attraction a ete retenue. Toutefois, la dimension n doit rester inferieure a 10. On tente de resoudre le probleme d'un grand nombre de variables en le fractionnant: au lieu d'agir sur la totalite des variables, on effectue des minimisations successives sur des sous-ensembles. Des essais sur des fonctions tests comportant jusqu'a 100 variables sont satisfaisants. On obtient la proportionnalite du temps de calcul et du nombre des variables. Ces methodes ont ete interfacees avec le simulateur electrique spice-pac et appliquees a la caracterisation de modeles de transistors et a l'optimisation de circuits
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Karlsson, Mattias. "COMPARISON AND EVALUATION OF HARDWARE MODELLING AND SIMULATION TOOLS." Thesis, Tekniska Högskolan, Högskolan i Jönköping, JTH, Data- och elektroteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-16734.
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Avionics Division of Saab AB develops advanced electronics that need to be robust and work in harsh environments with for example extreme temperatures and cosmic radiation without any failure. To succeed with this the electronics need to be simulated and tested. Therefore this thesis work is done to strengthen the Avionics Division’s knowledge of hardware modelling and simulation by evaluating the simulation tools LTSpice, PSpice and SystemVision, their functions and capabilities. In this thesis a survey is carried out with help of a questionnaire to study the Avionics Division’s needs for simulation. The survey is underlying an analysis of the analyses that can be performed by the simulation tools for example Sensitivity analysis, Worst Case analysis, Monte Carlo analysis and Parametric Sweep analysis. The different analyses are discussed in the thesis. The questionnaire is also underlying an analysis of the tools LTSpice, PSpice and SystemVision. The result of the analysis is summarized in Table 1. A case study of a circuit simulation in SystemVision, based on an existing circuit used by Avionics Division, is also done within this thesis work. The study is done to evaluate the tool’s usability, to see if it is easy to perform a simulation and if it is easy to find and use suitable models from the model library. The case study describes how a simulation is performed in SystemVision and how an AC analysis of a Butterworth filter is done. A stability and reliability check of the tool is performed as well as a robustness simulation. The analyses were easy to do and the overall impression is that SystemVision is reliable and user friendly structured. In order to check and compare the results of the AC analysis the same analysis is performed using LTSpice. The comparison shows that the results differ. This depending on that the models of the circuit were some what different in LTSpice and SystemVision. The final conclusion is that SystemVision would fit within Avionics Division’s workflow. Using SystemVision demands education of the engineers to secure maximum use of all the advantages of SystemVision.
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Zhang, Xiaowei. "A METHODOLOGY OF SPICE SIMULATION TO EXTRACT SRAM SETUP AND HOLD TIMING PARAMETERS BASED ON DFF DELAY DEGRADATION." UKnowledge, 2015. http://uknowledge.uky.edu/ece_etds/75.
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SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the interface like multiple-level caches between high speed processing elements and low speed peripherals. One method to design the SRAM is to use commercial memory compiler. Such compiler can generate different density/speed SRAM designs with single/dual/multiple ports to fulfill design purpose. There are discrepancy of the SRAM timing parameters between extracted layout netlist SPICE simulation vs. equation-based Liberty file (.lib) by a commercial memory compiler. This compiler takes spec values as its input and uses them as the starting points to generate the timing tables/matrices in the .lib. Originally large spec values are given to guarantee design correctness. While such spec values are usually too pessimistic when comparing with the results from extracted layout SPICE simulation, which serves as the “golden” rule. Besides, there is no margin information built-in such .lib generated by this compiler.
A new methodology is proposed to get accurate spec values for the input of this compiler to generate more realistic matrices in .lib, which will benefit during the integration of the SRAM IP and timing analysis.
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Pouget, Vincent. "Simulation expérimentale par impulsions laser ultra-courtes des effets des radiations ionisantes sur les circuits intégrés." Bordeaux 1, 2000. http://www.theses.fr/2000BOR12250.
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Ce travail présente l'élaboration d'un banc expérimental de test des circuits intégrés par faisceau laser impulsionnel ayant pour objectif la simulation des effets des radiations ionisantes sur les composants microélectroniques. Le contexte de l'étude est présenté par une revue de la littérature, et l'interaction ion-silicium est analysée. Un modèle rigoureux de l'interaction impulsion laser-silicium est développé. Les possibilités d'équivalence entre les deux interactions sont explorées et les limitations évoquées. Un modèle électrique de la réponse transitoire d'un transistor MOS à une irradiation est proposé. Un système expérimental de test des circuits intégrés par impulsions laser ultra-courtes est conçu, développé et caractérisé. Son automatisation complète est décrite. Le système est validé par différents types de tests effectués sur dès circuits numériques et analogiques. Le potentiel d'un nouveau type de cartographie des circuits intégrés est évalué.
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Tomas, Jean. "Caractérisation par simulation de la métastabilité des circuits séquentiels : application à des structures VLSI." Bordeaux 1, 1988. http://www.theses.fr/1988BOR10580.
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Le travail presente consiste en la realisation d'un logiciel d'aide a la conception de circuits unifieurs, appele remus (recherche des etats metastables dans les circuits unifieurs par simulation), en vue de leur optimisation vis-a-vis de la metastabilite. Ce programme, ecrit en pascal, implante sur micro-vax est bati autour du simulateur electrique spice. Les algorithmes implantes permettent d'obtenir la courbe d'incertitude de l'unifieur avec en temps de calcul reduit. Les resultats de sept circuits temoins sont presentes comparativement
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Iannello, Christopher J. "A unified approach to dynamic modeling of high switching frequency pwm converters." Doctoral diss., University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/RTD/id/4918.
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University of Central Florida College of Engineering ThesisThis dissertation will present the development of a unified approach for dynamic modeling of the PWM and soft-switching power converters. Dynamic modeling of non-linear power converters is very important for the design and stability of their closed loop control. While the use of equivalent circuits is often preferred due to simulation efficiency issues, no unified and widely applicable method for the formulation of these equivalents exists.
Ph.D.
Doctorate;
School of Electrical Engineering and Computer Science
Engineering
Electrical Engineering and Computer Science
252 p.
xi, 252 leaves, bound : ill. ; 28 cm.
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Xing, Zengping. "Magnetoelectric Device and the Measurement Unit." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/27387.
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Magnetic sensors are widely used in the field of mineral, navigational, automotive, medical, industrial, military, and consumer electronics. Many magnetic sensors have been developed that are generated by specific laws or phenomena: such as search-coil, fluxgate, Hall Effect, anisotropic magnetoresistance (AMR), giant magnetoresistance (GMR), magnetoelectric (ME), magnetodiode, magnetotransictor, fiber-optic, optical pump, superconducting quantum interference device (SQUID), etc. Each of these magnetic field sensors has their merits and application areas. For low power consumption (<10uW), quasi-static frequency (<10Hz) and high sensitivity (Ph. D.
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Peters, Kevin Christopher. "TOUCHSPICE: PHYSICAL-VIRTUAL CIRCUIT EMULATOR." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/769.
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This thesis involves the creation of a system of embedded touchscreen devices called touchSPICE to aid in the learning of basic circuits. Traditionally, circuit theory is taught to students in two different methods, lectures and laboratory exercises. Lectures focus on auditory and visual learning and are largely passive learning. Lab experiments allow students to physically interact with the circuits, and learn visually through viewing output waveforms from simulators or on measurement devices. The goal of the touchSPICE project is to develop a physical system for virtual, real-time SPICE simulation that mimics the laboratory experience. In touchSPICE, touchscreen devices act as circuit nodes that communicate with immediate neighbors using physical wires. Additionally, the nodes communicate wirelessly with a host computer, running a customized version of SPICE. Data is aggregated on the host computer and plotted in real-time. Changes in configuration of the nodes (component types and values), are then reflected on the host computer’s display.
The efficacy of touchSPICE as a learning tool was evaluated by using anonymous surveys from 20 subjects including a pretest, followed by an interactive session with touchSPICE, and a follow-up posttest. Results collected showed that with a few changes to improve the responsiveness of the touchscreen, touchSPICE may be an effective method for teaching circuit theory. Additionally, users enjoyed the quick configuration time that touchSPICE provided, and felt that the real-time feedback of touchSPICE helped support understanding of how circuits operate.
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Caillé, Denis. "Contribution à l'étude de la technologie bipolaire STL : caractérisation, modélisation et simulation de diodes Schottky TiW-Si et PtSi-Si." Bordeaux 1, 1988. http://www.theses.fr/1988BOR10571.
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Etude detaillee des caracteristiques electriques des diodes tiw-si et ptsi-si en fonction de leur structure technologique et de leur dimension. Les modeles analytiques obtenus permettent de prevoir le comportement des portes en fonction des choix technologiques et des parametres d'utilisation comme la temperature
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Ben, M'Hamed Bruno. "Contribution à l’analyse de la susceptibilité des composants électroniques à des perturbations transitoires : caractérisation et modélisation des éléments de protection." Limoges, 2010. https://aurore.unilim.fr/theses/nxfile/default/81a2f024-301f-467e-b07d-748c5a35fba1/blobholder:0/2010LIMO4049.pdf.
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La présence de systèmes embarqués faisant appel à l’électronique s’est intensifiée aussi bien dans les domaines civils et militaires. De plus, l’augmentation des fréquences d’horloges et des densités d’intégration s’accompagne d’une baisse des marges d’immunité au bruit, ce qui accroît la sensibilité des circuits aux parasites électromagnétiques externes. En parallèle, le nombre de perturbateurs potentiels ne cesse de croître. Se pose alors le problème de leur cohabitation avec les systèmes. Le contexte de notre étude nous amène à analyser l’influence du couplage d’une perturbation de type intentionnel (AGREMI) sur les systèmes électroniques. A l’échelle des cartes électroniques, les premiers éléments qui vont interagir avec ce signal sont les éléments de protection. Les travaux réalisés durant cette thèse de doctorat ont consisté à développer une méthodologie analytique et expérimentale permettant d’évaluer le comportement en régime transitoire des protections présentes dans les circuits électroniques en apportant une attention particulière au comportement des charges et aux effets non-linéaires des capacités parasites. La fiabilité de la méthodologie a été évaluée sur des protections discrètes (“Off-Chip”) et sur des étages de protections (“On-Chip”) des circuits intégrés numériquesThe presence of embedded systems using electronics has widely spread in the civil and military domains. Moreover, the significant increases of operating frequencies and integration densities are accompanied by a reduction of noise margins which obviously increases the sensitivity of the circuits against external electromagnetic interferences. In parallel, the number of potential disturbances continues growing, and the main problem is to assess the proper functioning of the systems to be used in this environment. The context of our study is to analyse the influence of the coupling of powerful parasitic sources on electronic systems. At the component level, the first elements seen by the signal are the protection devices. So the investigations achieved during this thesis have consisted in developing a theoretical and experimental methodology to evaluate the transient behaviour of the protections present in electronic circuits, with a special attention to the charge behaviour and the non-linear effects of the parasitic capacitances. The accuracy of this methodology is assessed to both discrete and on-chip protection devices
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Kane, Ibrahim. "Contribution à l'analyse de la susceptibilité électromagnétique des composants : Caractérisation et modélisation des étages d'entrée des circuits intégrés numériques." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0119/document.
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La prolifération des composants électroniques fait que l'étude de leur vulnérabilité face à des agressions électromagnétiques intentionnelles ou non devient de plus en plus préoccupante. Notre étude s'inscrit dans ce contexte et s'oriente plus particulièrement vers les composants numériques. Ces derniers incorporent généralement, à toutes leurs interfaces d'entrée et de sortie, des éléments de protection contre les décharges électrostatiques permettant d'éliminer tout signal se présentant avec une amplitude élevée. Cependant, les signaux perturbateurs peuvent avoir des amplitudes moindres mais des formes d'onde complexes et capables de causer des dysfonctionnements à ces composants numériques sans activer les protections. Dans ce cas, les étages d'entrée se retrouvent au premier plan et leur comportement face à ces signaux perturbateurs peut altérer la fonctionnalité globale du circuit. Ainsi, nous nous sommes proposés d'étudier et de modéliser les comportements de ces étages d'entrée face à ces types d'agressions. Une première étape a consisté à définir une plateforme d'expérimentation pour les composants numériques. Une sélection des types de composants de test a d'abord été effectuée et le choix s'est porté naturellement sur l'inverseur CMOS, car il est présent sur la quasi-totalité des étages d'entrée, et sa structure est simple et connue. Le choix de cette technologie est également dicté par sa simplicité et son omniprésence dans les équipements électroniques actuels. Différents types de signaux perturbateurs ont été appliqués à ces inverseurs CMOS afin d'observer et de relever leurs comportements typiques et particuliers. Ensuite, à partir des résultats expérimentaux, un modèle SPICE comportemental et générique des inverseurs CMOS a été créé. Différents types de modèles de composants numériques existent mais le type SPICE est le seul à expliciter leur architecture complète. En effet, pour des raisons liées aux propriétés intellectuelles, les fabricants sont généralement discrets sur les structures internes de leurs circuits intégrés. Par contre, ces modèles SPICE ne sont à priori valables que dans des limites de fonctionnement définis par les fabricants. Nous avons apporté diverses modifications à ce modèle afin d'incorporer les comportements observés en dehors des limites de fonctionnement des inverseurs CMOS. Le besoin de trouver un modèle générique a imposé d'étudier un grand nombre d'échantillons d'inverseurs CMOS de différents fabricants et de différentes familles technologies. Enfin, une synthèse des résultats de simulations et des modèles, en fonction des fabricants et des familles technologiques, a été réalisée sous forme d'un tableau récapitulatifThe proliferation of electronic components increases the interest of investigations about their vulnerability against electromagnetic interference intentionally emitted or not. Our study falls in this context and is specifically devoted to digital devices. These devices usually include, at their input/output ports, protection elements to prevent against electrostatic discharges and all kind of signals with very high amplitude. However, the perturbating signals can have low amplitude and complex waveforms that can cause trouble to these digital devices without triggering protection elements. In this case, first stages are the front, and their behaviors against these perturbation signals can alter the good operation of the device. Thus, we propose to study and model the behaviors of these first stages against such aggressions. First of all, an experimental platform was defined for the digital devices. A selection of devices is done and CMOS inverter was naturally chosen because of its presence in almost all of the first stages of digital devices, and because its structure is simple and well known. The choice of the CMOS technology is also due to its simplicity and omnipresence in current electronic equipments. Different perturbation signals were applied to these CMOS inverters to observe and record their typical and particular behaviors. Secondly, with the experimental results, a behavioral and generic SPICE model of CMOS inverters was developed. Different models exist for digital devices, but SPICE is the only one explicitly describing their complete architecture. But, for intellectual proprieties reasons, the manufacturers are usually reluctant to share information on their devices’ internals. However, the SPICE models are only valid within some operating limits defined by manufacturers. We have brought different modifications to this SPICE model to incorporate the observed behaviors of CMOS inverters inside and outside their normal operating conditions. The generic criterion of the final model imposed to study a large number of CMOS inverters of different manufacturers and different logic families. Finally, a synthesis of models and simulation results, by manufacturer and logic family, is produced
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Zebbache, Ahmed. "Analyse et synthèse statistiques des circuits électroniques : mise en œuvre du simulateur ouvert SPICE-PAC et de la méthode du recuit simule." Châtenay-Malabry, Ecole centrale de Paris, 1996. http://www.theses.fr/1996ECAP0467.
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Dans la conception des circuits électroniques les variations statistiques des valeurs des paramètres des circuits doivent être prises en compte car elles ont un impact sur la qualité des circuits fabriques. Ces fluctuations statistiques essentiellement dues au processus de fabrication des tolérances, induisent des variations dans les réponses des circuits fabriqués. Le rendement de fabrication, qui est la proportion des circuits fabriqués répondant à un ensemble de contraintes d'acceptabilité spécifiées par le concepteur, est d'un intérêt considérable. Obtenir un rendement acceptable est l'un des principaux objectifs d'un concepteur de circuits électroniques. La méthode de Monte-Carlo a été utilisée pour simuler les variations dans les paramètres des composants ainsi que pour estimer le rendement de fabrication. Cette méthode est choisie a cause de sa généralité et de sa faible dépendance des variables stochastiques. Un programme fondée sur cette méthode a été élaboré et couplé au simulateur SPICE-PAC dont la structure modulaire se prête mieux aux exigences de l'analyse statistiques. Lorsque le rendement de fabrication est faible, il est nécessaire de l'améliorer. C’est la méthode des centres de gravite qui a été utilisée pour optimiser le rendement. L’échantillonnage statistique est amélioré grâce à la méthode des points communs. Malgré que la méthode des centres de gravite soit robuste et d'une utilisation aisée, elle peut être piégée dans optimum local du rendement. Pour résoudre ce problème, nous avons propose une approche d'optimisation du rendement de fabrication qui combine la méthode des centres de gravite et la méthode du recuit simulé
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Guitard, Nicolas. "Caractérisation de défauts latents dans les circuits intégrés soumis à des décharges électrostatiques." Phd thesis, Université Paul Sabatier - Toulouse III, 2006. http://tel.archives-ouvertes.fr/tel-00139542.
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Les agressions électriques, du type décharges électrostatiques (ESD) et surcharges électriques (EOS), sont à l'origine de plus de 50% des défaillances des circuits intégrés. De plus, avec l'avènement des technologies sans fil et des applications dites "plus électriques" en automobile et dans l'aviation, les spécifications de robustesse à ces agressions se sont considérablement durcies. Dans le même temps, la réduction des dimensions et la complexité croissante des technologies pose le problème de leur susceptibilité à ces contraintes EOS/ESD et de la probabilité non négligeable de génération de défauts latents. Enfin, les niveaux de fiabilité exigés maintenant dans la plupart des applications sont extrêmement élevés. Afin de répondre à ces nouvelles exigences, la détection des défauts latents est devenue indispensable, notamment pour des applications comme celles du domaine spatial. Or, la diminution des dimensions lithographiques a pour conséquence une augmentation des courants de repos des circuits microélectroniques. Cette augmentation rend difficile voire impossible la détection de défauts latents susceptibles de " dé-fiabiliser " des systèmes microélectroniques. Nous avons, dans cette thèse, étudié l'impact de défauts latents induits par stress ESD de type CDM sur la fiabilité de circuits et proposé une nouvelle méthodologie pour leur détection. Issue du domaine des radio fréquences, cette méthodologie basée sur des mesures du bruit basse fréquence nous a permis de mettre en évidence, avec une meilleure sensibilité, des défauts latents dans de simples structures de protections ESD mais aussi dans des circuits commerciaux complexes soumis à des décharges de type CDM. Différentes techniques de localisation par stimulation laser ont été mises en oeuvre pour la détection physique des défauts générés et corroborer l'analyse des mécanismes physiques à l'origine de l'augmentation du bruit.
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Bui, Van Diep. "Conception et modélisation de transistors TFTs en silicium microcristallin pour les écrans AMOLED." Phd thesis, Ecole Polytechnique X, 2006. http://pastel.archives-ouvertes.fr/pastel-00002258.
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Les travaux précédemment réalises au sein du LPICM ont mis en évidence que le silicium microcristallin est un semi-conducteur a faible cout, possédant une mobilité importante avec malgré tout une très bonne stabilité. Ce qui en fait un matériau particulièrement intéressant pour les transistors TFTs des écrans plats OLED 2. Il nous a donc paru logique de nous intéresser, dans le cadre de cette thèse, a la conception et a la réalisation expérimentalement des structures de pixel OLED à base de transistors TFTs en silicium microcristallin. Pour ce faire, il est indispensable de posséder des modèles comportementaux performants des composants. Ainsi, notre objectif primordial a été de concevoir des modèles Spice de transistors c-Si TFT mais aussi d'OLED. D'un point de vue technologique, nous nous sommes attaches à maitriser l'ensemble de la chaine de fabrication (conception de masques et lithographie en salle blanche). La caractérisation de nos transistors a révèle des mobilités de l'ordre de 1 cm2V−1s−1, des tensions de seuil de 4 V et a montre une bonne stabilité, sous stress, de la tension de seuil et de la mobilité. La faisabilité de ces transistors sur substrats flexibles comme le polyimide a aussi été démontre dans le cadre du Projet Intégré FlexiDis. Du point de vue de la modélisation, un modèle statique et dynamique Spice de transistor en silicium microcristallin est propose. L'écriture de ce modèle dans le langage Verilog-A nous permet de garantir une bonne portabilité et de pouvoir ainsi utiliser facilement des simulateurs professionnels comme Spectre de chez Cadence. De manière complémentaire, un modèle Spice efficient de diode OLED est également propose. Grace à ces outils, nous avons pu simuler des circuits utilisant les TFTs en silicium microcristallin. Ces simulations nous permettent de prédire que ces composants sont pertinents pour la conception de pixel OLED, de drivers de lignes, mais aussi de portes logiques NMOS simples comme l'inverseur et l'oscillateur en anneau.
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Bertrand, Géraldine. "Conception et modélisation électrique de structures de protection contre les décharges électrostatiques en technologies BICMOS et CMOS analogique." Toulouse, INSA, 2001. http://www.theses.fr/2001ISAT0037.
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Avec la réduction des dimensions lithographiques et l'introduction de nouveaux procédés technologiques, les circuits intégrés sont devenus plus vulnérables aux décharges électrostatiques (ESD). Ainsi, pour minimiser le nombre d'itérations de masques liées à ce problème, il faut désormais prendre en compte l'ESD très tôt dans le développement de nouveaux produits et, pour cela, pouvoir prédire l'efficacité d'une stratégie de protection. La mise à disposition de bibliothèques d'éléments de protection optimisés, incluant leur dessin technologique ainsi qu'un modèle électrique de type SPICE, répond à ce besoin. Cependant, les structures de protection contre les ESD sont des composants qui fonctionnent dans des régimes de claquage par avalanche et de fort courant qui ne sont pas décrits par les modèles SPICE standards. Nous présentons dans notre mémoire une méthodologie permettant l'extension des modèles classiques à ces domaines, dans le cas de deux structures respectivement utilisées en technologies BiCMOS et CMOS analogique : le transistor bipolaire NPN vertical autopolarisé, et le transistor NMOS qui fonctionne grâce à l'action de son transistor NPN latéral parasite. Cette méthodologie repose sur une analyse approfondie des mécanismes de fonctionnement et de défaillance des composants à l'aide de simulations physiques bidimensionnelles, de caractérisations en impulsion (TLP) et d'expériences de microscopie à émission lumineuse (EMMI)The sensitivity of modern integrated circuits to ElectroStatic Discharges (ESD) increases with the technology shrink and the introduction of new process techniques. To move towards a "first pass success", ESD must be taken into account at an early stage of a project development which requires capability to predict efficiency of ESD protection strategies. The availability of an ESD protection library including both optimized layouts and electrical models is part of the solution. However, ESD protection structures operate in avalanche breakdown and high current regimes, which cannot be simulated with standard SPICE models. In this thesis, a methodology to extend classical models to these regimes is first developed for the vertical bipolar NPN transistor widely used in BiCMOS technologies. This methodology is then applied to the NMOS transistor in an analog CMOS process, with the modeling of its parasitic lateral NPN transistor. Physics-based compact models are provided thanks to 2D device simulation, TLP characterization and photoemission experiments (EMMI)
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Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.
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Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.
The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.
The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.
Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions.
The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.
We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.
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Chen, Haoning (William). "LLC Resonant Current Doubler Converter." Thesis, University of Canterbury. Electrical and Computer Engineering, 2013. http://hdl.handle.net/10092/8492.
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The telecommunications market is one of the large rapidly growing fields in today’s power supply industry due to the increasing demand for telecom distributed power supply (DPS) systems. The half-bridge LLC (Inductor-Inductor-Capacitor) resonant converter is currently the most attractive topology for the design and implementation of 24V/48V DC telecom power converters. The current doubler rectifier (CDR) converter topology was invented and described in the early 1950s which can offer the unique characteristic of halving the output voltage while doubling the output current compared to a standard rectifier. In this thesis, the current doubler converter topology with its unique characteristic is evaluated as a complementary solution to improve the LLC resonant converter performance, especially for the low output voltage and high output current telecommunication applications. A novel half-bridge LLC resonant current doubler converter (LLC-CDR) is proposed in this thesis which can offer several performance benefits compared to conventional LLC-standard rectifier design . The unique characteristics of the LLC-CDR topology can offer significant improvements by transformation of a 48V converter into a 24V converter with the same power density. This thesis introduces a new SPICE-based simulation model to analyse the operation of this novel LLC-CDR converter circuit design. This model can be used to define the critical component parameters for the LLC -CDR circuit output inductor values. It can also be used to predict the circuit overall performance under different load conditions. Both time-domain based transient simulation analysis and frequency-domain based AC analysis provided by this simulation model showed favourable results in comparison to bench measurement results on a prototype. The model
provides a valuable insight to reveal some of the unique characteristics of this LLC -CDR topology. It demonstrates a proof of concept that the conventional LLC resonant
converter can be easily redesigned for low voltage, high current applications by using the LLC-CDR topology without requiring a new design for the LLC resonant stage components and the power transformer. A new magnetic integration solution was proposed to significantly improve the overall performance in the LLC-CDR topology that had not been published before. The LLC-CDR converter hardware prototypes with two output inductors coupled and uncoupled configurations were extensively modelled, constructed and bench tested.Test results demonstrated the suitability of an integrated coupled inductors design for the novel LLC-CDR converter application. The integrated coupled inductors design can significantly improve the LLC-CDR converter frequency-domain based AC simulation analysis results. In addition, these results also illustrate the potential benefit of how the magnetic integration design in general could reduce the magnetic component size, cost, and weight compared to the uncoupled inductors design. Finally, a hardware prototype circuit was constructed based on a commercial 1800 W single phase telecom power converter to verify the operation of this novel half bridge LLC-CDR topology. The converter prototype successfully operated at both no load and full load conditions with the nominal output voltage halved from 48VDC to 24VDC, and doubled the output current to match the same output power density. It also demonstrates that the efficiency of this novel half bridge LLC –CDR is 92% compares to 90% of EATON’s commercial 24VDC LLC resonant converter, which can fulfill the research goals.
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Jaulent, Patrice. "Etude des effets singuliers transitoires dans les amplificateurs opérationnels linéaires par photogénération impulsionnelle non-linéaire." Phd thesis, Bordeaux 1, 2009. http://tel.archives-ouvertes.fr/tel-00997385.
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Ce travail présente l'étude des effets des radiations sur des composants analogiques commerciaux. Une méthode de caractérisation expérimentale de la sensibilité de ces composants, par le biais de simulations électriques et de stimulations laser non linéaire, est mise en place.
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Kimoto, Daiki. "Characterization and Modeling of SiC Integrated Circuits for Harsh Environment." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223422.
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Elektronik för extrema miljöer, som kan användas vid hög temperatur, hög strålning och omgivning med frätande gaser, har varit starkt önskvärd vid utforskning av rymden och övervakning av kärnreaktorer. Kiselkarbid (SiC) är en av kandidaterna inom material för extrema miljöer på grund av sin höga temperatur- och höga strålnings-tolerans. Syftet med denna avhandling är att karakterisera 4H-SiC MOSFETar vid hög temperatur och att konstruera SPICE modeller för 4H-SiC MOSFETar. MOSFET-transistorer karakteriserades till 500°C. Med användande av karaktäristik för en 4H-SiC NMOSFET med L/W = 10 µm / 50 µm, anpassades en SPICE LEVEL 2 kretsmodell. Modellen beskriver DC karakteristiska av 4H- SiC MOSFETar mellan 25ºC och 450ºC. Baserat på SPICE-kretsmodellen simulerades egenskaper för operationsförstärkare och digitala inverterar. Därutöver analyserades driften av pseudo-CMOS vid hög temperatur och principen för konstruktion av pseudo-CMOS föreslogs. Arean och utbytet (s.k. yield) av pseudo-CMOS integrerade kretsar uppskattades och det visar sig att SiC pseudo-CMOS integrerade kretsar kan använda mindre area än SiC CMOS integrerade kretsar.Harsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance. The objective of this thesis is to characterize 4H-SiC MOSFETs at high- temperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of 25 – 450ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-CMOS at high-temperature was analyzed and the operation principle of pseudo-CMOS was suggested. The device area and yield of pseudo-CMOS integrated circuits were estimated and it is shown that SiC pseudo-CMOS integrated circuits can use less area than SiC CMOS integrated circuits.
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TREMOUILLES, David. "Optimisation et modélisation de protection intégrées contre les décharges électrostatique, par l'analyse de la physique mise en jeu." Phd thesis, INSA de Toulouse, 2004. http://tel.archives-ouvertes.fr/tel-00010263.
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Les travaux présentés dans ce mémoire visent à améliorer la méthodologie de conception et les performances des stratégies de protection contre les décharges électrostatiques (ESD) dans les circuits intégrés. Pour cela, l'approche choisie est basée sur une analyse approfondie de la physique des composants soumis aux ESD et plus particulièrement, les effets des très fortes densités de courant. L'étude, focalisée sur les transistors bipolaires autopolarisés, s'appuie sur la simulation physique 2D et l'utilisation des outils de localisation de défaillance basés sur les techniques de stimulation laser. L'analyse physique en résultant a permis d'une part, de définir des règles de dessin universelles pour l'obtention d'une robustesse ESD élevée et d'autre part, de proposer des macro-modèles de type SPICE originaux pour prendre en compte les effets des fortes densités de courant. Enfin, après avoir mis en évidence plusieurs phénomènes limitant les performances des réseaux de protection, nous avons défini une méthodologie de conception améliorée permettant de les prendre en compte et de garantir la performance des solutions de protections fournies aux concepteurs de circuits.
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Najari, Montassar. "Modélisation compacte des transistors à nanotube de carbone à contacts Schottky et application aux circuits numériques." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2010. http://tel.archives-ouvertes.fr/tel-00560346.
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Afin de permettre le développement de modèles manipulables par les concepteurs, il est nécessaire de pouvoir comprendre le fonctionnement des nanotubes, en particulier le transport des électrons et leurs propriétés électroniques. C'est dans ce contexte général que cette thèse s'intègre. Le travail a été mené sur quatre plans : • Développement de modèles permettant la description des phénomènes physiques importants au niveau des dispositifs, • Expertise sur le fonctionnement des nano-composants permettant de dégager les ordres de grandeurs pertinents pour les dispositifs, les contraintes, la pertinence de quelques procédés de fabrication (reproductibilité, taux de défauts), • Collection de caractéristiques mesurées et développement éventuel d'expériences spécifiques, • Expertise et conception des circuits innovatifs pour l'électronique numérique avec ces nano-composants. Mots clés — Modélisation compacte, transistor Schottky à nanotube de carbone, simulation circuit, cellule mémoire SRAM, effet tunnel, WKB.
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Kernstine, Kemp H. "Design space exploration of stochastic system-of-systems simulations using adaptive sequential experiments." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44799.
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The complexities of our surrounding environments are becoming increasingly diverse, more integrated, and continuously more difficult to predict and characterize. These modeling complexities are ever more prevalent in System-of-Systems (SoS) simulations where computational times can surpass real-time and are often dictated by stochastic processes and non-continuous emergent behaviors. As the number of connections continue to increase in modeling environments and the number of external noise variables continue to multiply, these SoS simulations can no longer be explored with traditional means without significantly wasting computational resources.
This research develops and tests an adaptive sequential design of experiments to reduce the computational expense of exploring these complex design spaces. Prior to developing the algorithm, the defining statistical attributes of these spaces are researched and identified. Following this identification, various techniques capable of capturing these features are compared and an algorithm is synthesized. The final algorithm will be shown to improve the exploration of stochastic simulations over existing methods by increasing the global accuracy and computational speed, while reducing the number of simulations required to learn these spaces.
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Morancho, Frédéric. "Le transistor MOS de puissance à tranchées : modélisation et limites de performances." Phd thesis, Université Paul Sabatier - Toulouse III, 1996. http://tel.archives-ouvertes.fr/tel-00165581.
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Ce mémoire traite de la modélisation et de l'évaluation des performances d'un nouveau composant de puissance, le transistor MOS à tranchées. Plus précisément, on présente tout d'abord l'évolution des structures MOS de puissance basse tension depuis les années 70 jusqu'au transistor MOS à tranchées dont les principales propriétés sont énumérées. On réalise ensuite une étude des mécanismes - analyse statique à l'état passant et à l'état bloqué, analyse dynamique - intervenant dans les diverses zones du composant. Sur la base de cette étude, on établit un modèle de ce transistor pour le logiciel de simulation des circuits SPICE. Les procédures d'acquisition des paramètres de ce modèle sont précisées. Ce modèle ainsi obtenu est ensuite validé sur deux familles de divers composants MOS de puissance industriels. Enfin, les limites de performances statiques et dynamiques des transistors VDMOS et MOS à tranchées sont étudiées et comparées. Il est principalement montré que, dans le domaine des basses tensions, le transistor MOS à tranchées affiche des performances supérieures au transistor VDMOS en termes de résistance passante spécifique et de densité d'intégration. Les études analytiques et les simulations bidimensionnelles des deux types de composants montrent également que cette supériorité est appelée à s'accroître dans les années à venir.
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Ali, Ehsan. "Fast and efficient modeling and design methodology of arbitrary ordered mixed-signal PLLs." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4352.
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La boucle à verrouillage de phase est essentielle dans la génération et la synthèse de fréquence, présent dans les communications RF, l’instrumentation, les capteurs ainsi que beaucoup d’autres domaines. Il existe deux types de dispositifs: la PLL numérique et la PLL analogique. La PLL numérique est essentiellement utilisée dans le domaine de l’instrumentation et dans la génération d’horloge, où les fréquences sont relativement faibles. Quant à la PLL analogique, elle est plus utilisée dans les communications sans fil ainsi que dans les transmetteurs à haut débit, dont la fréquence de fonctionnement est de l’ordre du GHz. Etant donné qu’une PLL est au moins du second ordre, elle peut être sujette à une instabilité pouvant mener à un disfonctionnement du système. Ainsi la méthodologie de conception d’un tel système comporte plusieurs étapes : 1) modélisation linéaire, 2) modélisation comportemental, 3) simulation niveau transistor. Les simulations électriques du comportement transitoire d’une PLL sont très gourmandes en temps. En effet des calculs dont la complexité croit avec le facteur de division sont effectués à chaque itération du signal de référence. Cela constitue un frein technologique, et rend la conception d’une PLL très difficile. Cette thèse se focalise sur le modèle comportemental des PLL analogiques fonctionnant avec des pompes de charge commandées en tension, dont la caractéristique du temps de démarrage qui est hautement non linéaire et même des fois chaotique est sujet critique. L’objectif principal est d’établir une méthodologie de conception efficiente pour les PLL analogiques et leur caractérisation en utilisant la technique évènementielleThe Charge-Pump Phase Locked Loop (CP-PLL) is a mixed-signal system and the important block for the frequency generation or frequency synthesis in radio frequency communications, instrumentations, metrology, sensors and so on. There are two types of devices: a full digital PLL and an analog PLL. The fully digital PLL is mainly used in instrumentation field and in clock and data recovery circuits where moderate frequency operation is used. For wireless communication or high data-rate optical transceiver analog CP-PLL is the most used architecture where the operating frequency is in the range of GHz. Since a PLL is at least a second order system, it is subjected to an instability that can lead to non-functional device. Thus, common design methodology contains several steps including i) Linear models ii) Behavioral modeling iii) and transistor level simulations. Electrical simulation (like SPICE) of the transient operation of PLL is time consuming and may take up to several weeks. In fact, the simulator must perform, for each time step of the reference signal, calculations where complexity increases with the division factor. This is known as technological bottleneck, designing a PLL at transistor level is very hard in a reasonable time. In this thesis the work is focused on the behavioral modeling of CP-PLL operating with voltage switched charge-pump (VSCP), where the characterization of its transient time “off-locking” and highly non-linear and even in chaotic mode remains a critical issue. The main objective is to establish a fast and efficient modeling and design methodology of high order CP-PLL and its characterization using the event driven technique
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Müller, Anne-Dorothea. "Elektrochemische Metallabscheidung mit Kapillarsonden." Doctoral thesis, Universitätsbibliothek Chemnitz, 2002. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200200103.
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Es wird ein Verfahren zur lokalisierten elektrochemischen Abscheidung metallischer Strukturen aus Kapillarsonden vorgestellt. Der experimentelle Aufbau, die Herstellung der Sonden, das Arbeiten im Nahfeld der Probe (Scherkraft-Abstandsdetektion)sowie die verschiedenen Beschaltungmöglichkeiten der elektrochemischen Zelle werden ausführlich beschrieben. Ergänzend zu den experimentellen Arbeiten werden einerseits numerische Simulationen gezeigt, die zur Veranschaulichung der Potentialverteilung in der Apexregion dienen und qualitativ beschreiben, wie sich das Schichtdickenprofil der abgeschiedenen Strukturen mit den einstellbaren Parametern (Elektrodenpotentiale, Spitze-Probe-Abstand) variieren läßt. Andererseits werden die verschiedenen Beschaltungsmöglichkeiten der Zelle anhand von Schaltungssimulationen verglichen und so die Wahl des günstigsten Arbeitspunktes für die in den Experimenten verwendete (bi)-potentiostatische Abscheidung diskutiert. Mit dieser Anordnung wurden lokalisiert Cluster in einer porösen Aluminiumoxidmembran deponiert und anschließend abgebildet. In weiteren Strukturierungsversuchen wurden Kupfer bzw. Gold lokalisiert elektrochemisch auf ITO abgeschieden, wobei das Schichtwachstum simultan optisch in Transmission beobachtet wurde. Es werden u.a. Strukturen erzeugt, deren laterale Abmessungen kleiner als der Kapillardurchmesser sind (Fokussierung, max. Verhältnis 8:1). Die derzeit kleinsten elektrochemisch erzeugbaren Strukturen haben eine laterale Ausdehnung von ca. 5 MikrometernA method for the localized electrochemical deposition of metal structures using capillary tips is presented. The experimental set-up, the tip preparation, the distance detection in near-field operation (shear-force detection), as well as the different types of circuiting of the electrochemical cell are described in detail. In addition to the experimental work, numerical simulations for the qualitative visualization of the potential distribution around the apex region show, how the films thickness profile can be adjusted with the variable parameters (electrode voltages, tip-sample distance). Circuit simulations of the electrochemical cell allow to pre-estimate the optimum working conditions for the used (bi)-potentiostatic electrode set-up. With this method, clusters have been deposited in a thin film of porous alumin oxide and imaged in shear-force mode. Gold and copper structures have been deposited on ITO, while the film growth was observed optically. The lateral dimension of the deposited structures can be smaller than the inner diameter of the capillaries (maximum focus: 8:1). The smallest structures produced in this work have lateral dimensions of 5 micrometers
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Kešner, Filip. "Design of Digital Circuits at Transistor Level." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236048.
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This work aims to design process of integrated circuits on the transistor level, specially using evolutionary algorithm. For this purpose it is necessary to choose reasonable level of abstraction during simulation, which is used for evaluation candidate solutions by fitness function. This simulation has to be fast enough to evaluate thousands of candidate solutions within seconds. This work discusses already used techniques for transistor level circuit design and it chooses useful parts for new design of faster and more reliable automated design process, which would be able to design complex logic circuits. The thesis also discusses implementation of this system and used approach with regard to encountered problems in transistor-level circuit design and optimization by evolution.
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Samant, Gajanan Balkrishna. "Verification of the "Energy Accumulation in Waves Travelling through a Checkerboard Dielectric Material Structure in Space-time" Using Spice Simulations." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/1210.
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"Recently, there has been some good interest in the field of Dynamic Materials, also referred to as Spatio-Temporal Composites. These materials have been theoretically attributed to show ability to switch their electromagnetic properties in time, as contrast to the spatial variations shown by regular materials of non-dynamic nature, existing naturally. Though there is no exhibition of dynamic material in nature yet, there are suggestions for its synthesis. This paper follows the idea of using standard lossless transmission line model approximating a material substance. Such a material though not truly homogeneous, could be made to vary its properties in time. The aim of this work is to test this idea for its functional efficiency in comparison to analytical results obtained from earlier works on the subject. We make use of Spice simulation for this. An important aspect of this work is to facilitate the dynamic operations in a static environment. Almost all the simulators available today like Spice, ADS, etc intrinsically provide no ability for parameter variations in time. Nonetheless, we make use of certain popular tricks to implement circuits imitating the dynamic circuit components we need. Such implementations are separately tested to demonstrate their success in providing us with the dynamic environment we desire. Finally, within the limitations of the computing capabilities, we could successfully show an agreement between the results obtained and the existing theory. "
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Souza, Junior Rodolfo Renato de. "Modelo de IGBT para um conversor CC-CC de 1000A usado em controle de motores de tração de locomotivas diesel-elétricas." Universidade Tecnológica Federal do Paraná, 2017. http://repositorio.utfpr.edu.br/jspui/handle/1/2854.
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O presente trabalho tem por objetivo o desenvolvimento de um modelo analógico dinâmico do IGBT 2MBI1200U4G-170 para simulação SPICE para a análise de tempos de comutação, perdas e corrente de carga. Este desenvolvimento foi motivado pelo fato de não se dispor de modelos prontos para IGBT para faixas de tensão e corrente na ordem de kV e kA, destinado ao projeto de um conversor CC para controle de motores de tração em locomotivas diesel-elétricas. Como parte do processo se fez uma tentativa de modificação do modelo padrão de IGBT da plataforma Cadence Orcad 16.5, baseada nos trabalho de Hefner, considerada uma forma de modelo físico. Verificou-se que o correto levantamento dos dados para o modelo físico não seria compensatório frente às análises desejadas, o que gerou necessidade por outras formas de modelagem. Decidiu-se por um modelo analógico, obtido com dados do catálogo do componente descritos em tabelas e como fontes de tensão e corrente. Os resultados mostraram-se adequados para projeto térmico, análise de formas de onda e corrente de porta e coletor. A simulação é comparada com curvas da documentação do fabricante e com dados obtidos a partir de testes estáticos em laboratório com duas topologias. Testes foram feitos com tensão de entrada de 74V, 300V, 900V e 1000V, frequências de comutação de 200Hz, 416Hz, 1kHz e 2kHz e correntes de carga de até 1400A. A corrente de carga apresentou diferenças de até 3% com a medida em laboratório e a temperatura divergiu em até 7% com a medida no dissipador do protótipo usado.This paper presents the design report for an analog IGBT SPICE model, part number 2MBI1200U4G-170. The modeling was perceived as a interesting tool in order to analyze the switching times and losses during the development, not performed at the University, of a chopper DC-DC converter used for current control of traction motors of diesel-electric locomotives. The main motivational factor was that an practical and quick approach was wanted and none standard model was found for the intended IGBT part number. As part of the process, an attempt to modify the standard SPICE model of the Cadence Orcad 16.5, which is a physics model based on Hefner works, was made. It was verified that the correct data collecting for the standard model would not be compensatory, so other modeling techniques were needed. It was decided an analog modeling would be used. The modeling achieved uses no more than the information found on the component datasheet described in tables format, voltage and current sources. The validation was done in two different topologies with load currents up to 1400A, switching frequencies of 200Hz, 416Hz, 1kHz and 2kHz and input voltages of 74V, 300V, 900V and 1000V . Comparatives were done with the vendor catalog and laboratory data. The model is satisfactory for heat, collector and gate currents analysis. The simulation current and temperature results showed differences up to 3% and 7%, respectively, when compared to laboratories measurements.
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Bayer, Ozgur. "Simulation Of Refrigerated Space With Radiation." Phd thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/3/12610454/index.pdf.
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Performance of a refrigerator can be characterized with its ability to maintain a preset low temperature by spending the least amount of electricity. It is important to understand natural convection inside a refrigerator for optimizing its design for performance. Computational Fluid Dynamics (CFD) together with experiments is a very powerful tool for visualizing flow and temperature fields that are essential for understanding a phenomenon that involves both fluid and heat flow. In this aspect, simulations are performed for compartment and total refrigerator models using the package program Fluent which is based on finite volume method. An experimental study is performed to determine the constant wall temperature boundary conditions for the numerical models. Effect of radiation is also investigated by comparing the numerical study of a different full refrigerator model with a similar one in literature. While evaluating the radiation effect, convection boundary condition is selected by defining overall heat transfer coefficient between the ambient room air at a constant temperature and the inner surfaces of the walls. Based on assumptions, related heat transfer analyses are done using compartment and total refrigerator model analyses. Performing CFD simulations of a refrigerator cabinet for visualizing the flow and temperature fields which is the aim of the study is achieved and some observations that can be useful in design optimization are made.
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Hällqvist, Robert. "Temperature Control of Space Simulation Chamber." Thesis, KTH, Rymd- och plasmafysik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-101931.
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Liao, Si-yu. "Caractérisation électrique et électro-optique de transistor à base de nanotube de carbone en vue de leur modélisation compacte." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14254/document.
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Afin de permettre de développer un modèle de mémoire non-volatile basée sur le transistor à nanotube de carbone à commande optique qui est utilisée dans des circuits électroniques neuromorphiques, il est nécessaire de comprendre les physiques électroniques et optoélectroniques des nanotubes de carbone, en particulier l’origine de l'effet mémoire que présente ces transistors. C’est dans ce contexte général que cette thèse s'intègre. Le travail est mené sur trois plans :• Caractériser électriquement et optoélectroniquement des structures de test des CNTFETs et des OG-CNTFETs.• Développer un modèle compact pour les contacts Schottky dans les transistors à nanotube de carbone de la façon auto-cohérente basé sur le diamètre et la nature du métal d’électrode en utilisant la méthode de la barrière effective avec les paramètres nécessaires calibrés.• Modéliser l'OG-CNTFET selon les régimes de fonctionnement, lecture, écriture, effacement ou programmation pour application à une mémoire non-volatile en intégrant le mécanisme de piégeage et dépiégeage à l’interface polymère/oxydeThis PhD thesis presents a computationally efficient physics-based compact model for optically-gated carbon nanotube field effect transistors (OG-CNTFETs), especially in the non-volatile memory application. This model includes memory operations such as “read”, “write”, “erase” or “program”, and “reset” which are modeled using trapping and detrapping mechanisms at the polymer/oxide interface. The relaxation of the memory state is taken into account. Furthermore, the self-consistent modeling of Schottky barriers at contacts between the carbon nanotube channel and metal electrodes is integrated in this model applying the effective Schottky barrier method. The Schottky contact model can be included in CNTFET based devices for a typical biasing range of carbon nanotube transistors. This compact model is validated by the good agreement between simulation results and experimental data (I-V characteristics). In the non-volatile memory application, this model can fully reproduce device behaviors in transient simulations. A prediction study of the key technological parameter, the CNT diameter variety is established to expect its impact on the transistor performance, and more importantly, on the memory operation. In the other hand, this thesis presents a preliminary electric characterization (I-V) of CNTFETs and OG-CNTFETs for the device modeling database. A preliminary optoelectronic characterization method is proposed
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Woodcock, Jonathan Peter. "Simulations of space plasma instabilities." Thesis, Queen Mary, University of London, 1997. http://qmro.qmul.ac.uk/xmlui/handle/123456789/131.
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This work describes computer simulations of the behaviour of plasmas similar to those observed in the near Earth environment The work can be split into three main threads Firstly we have developed a set of algorithms to allow the implementation of particle type simulation models on parallel computer architectures ranging from small workstation clusters to massively parallel supercomputers These algorithms allow large simulations with many particles to be performed We address the problems of e cient use of available computational resources and the scaling of algorithms as computers get larger Secondly we use a parallel implementation of a two dimensional hybrid simulation code with periodic boundaries to explore the evolution of ion beam distributions similar to those observed upstream of the Earth s bow shock We follow the evolution of the resonant instabilities of these cool tenuous proton beams both isotropic and anisotropic in temperature into the non linear regime We examine the waves generated their e ects on the ion distribution function the phenomenon of gyrophase bunching and describe the life cycles of two dimensional magnetic features including oblique propagating shocklets We suggest that such two dimensional structures may play a role in the saturation of beam instabilities Coherence lengths of the waves are calculated We see some evidence of anisotropy driven mirror waves late on in these simulations Thirdly we explore the nature of parametric instabilities in two dimensions We examine the role of parametric or wave wave instabilities in the late evolution of beam instability generated waves We nd little evidence of any parametric instability in this case The two dimensional evolution of a wave known to be unstable to one dimensional parametric instability is described We nd that in this case the instability develops in a manner similar to that found in one dimensional simulations although with some angular broadening in wavevector space There is some evidence of anisotropy driven instabilities later in the simulation
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Kucukyavuz, Fatih. "Transforming Conceptual Models Of The Mission Space Into Simulation Space Models." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613158/index.pdf.
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Helping to abstract a valid model from real system, conceptual modeling is an essential phase in simulation development lifecycle. With the development of the KAMA framework, a new methodology was presented to develop mission space conceptual model for simulation systems. It provides metamodel elements represented by graphical diagrams to develop conceptual models of mission space. BOM (Base Object Model), developed by SISO (Simulation Interoperability Standards Organization), is another conceptual modeling concept serving for simulation space.
KAMA models are very close to problem domain and intend to model real world concepts in requirement analysis and development phase. Whereas, being vital inputs for the simulation design phase, BOM models are closer to solution domain. Hence there is no defined way of using the captured mission space knowledge in simulation space, problem arises when moving from requirement analysis to design phase. In this study, to solve this problem, we propose a method for transforming mission space conceptual models in simulation space. Our solution approach will be mapping the KAMA mission space models to BOM simulation space models for automatically transport real world analysis results to simulation designers.