Academic literature on the topic 'Single Photon Avalanche Diode (SPAD)'

This thesis explores Single-Photon Avalanche Diodes (SPADs), which are solid-state devices for photon timing and counting, and concentrates on SPADs integrated in nano-scale CMOS. The thesis focuses on: the search for new theory regarding Geiger-mode operation; proving the utility of calibrated Technology Computer- Aided Design (TCAD) tools for accurately simulating SPADs for the first time; the investigation of how manufacture influences device operation; and the integration of high performance SPADs into CMOS which rival discrete devices. The accepted theories of SPAD operation are revisited and it is discovered that previously neglected minority carriers have many significant roles such as determining: after-pulsing, Dark Count Rate (DCR), bipolar “SPAD latch-up,” nonequilibrium DCR, and “quenching”. The “quenching” process is revisited and it is concluded that it is the “probability time” of ≈100-200ps, and not the previously thought latching current that is important. SPADs are also found to have transient negative differential resistance. The new theories of SPADs are also supported by steady-state 1D, 2D and 3D TCAD simulations as well as novel transient simulations and videos. It is demonstrated as possible to simulate DCR, Photon Detection Efficiency (PDE), guard ring performance, breakdown voltage, breakdown voltage variation, “quenching,” and transient operation of SPADs with great accuracy. The manufacture of SPADs is studied focusing on the operation and optimisation of guard rings and it is found that ion implantation induced asymmetry from the tilt and rotation/twist is critical. Where symmetric, guard rings fail first along the <100> directions due to enhanced mobility. Process integration rules are outlined for obtaining high performance SPADs in CMOS while maintaining compatibility with transistors. The minimisation of tunnelling with lightly-doped junctions and the reduction of ion implantation induced defects by additional annealing are found essential for achieving low DCR. The thesis demonstrates that it is possible to realise high performance SPADs in CMOS through the innovation of a “Deep SPAD” which achieves record PDE of ≈72% at 560nm with >40% PDE from 410-760nm, combined with 18Hz DCR, <60ps FWHM timing resolution, and <4% after-pulsing which is demonstrated to have potential for significant further improvement. The findings suggest that CMOS SPAD-based micro-systems could outperform existing photon timing and counting solutions in the future.

There is a pressing need to develop alternative communications links due to a number of physical phenomena, limiting the bandwidth and energy efficiency of wire-based systems or economic factors such as cost, material-supply reliability and environmental costs. Networks have moved to optical connections to reduce costs, energy use and to supply high data rates. A primary concern is that current optical-detection devices require high optical power to achieve fast data rates with high signal quality. The energy required therefore, quickly becomes a problem. In this thesis, advances in single-photon avalanche diodes (SPADs) are utilised to reduce the amount of light needed and to reduce the overall energy budget. Current high performance receivers often use exotic materials, many of which have severe environmental impact and have cost, supply and political restrictions. These present a problem when it comes to integration; hence silicon technology is used, allowing small, mass-producible, low power receivers. A reconfigurable SPAD-based integrating receiver in standard 130nm imaging CMOS is presented for links with a readout bandwidth of 100MHz. A maximum count rate of 58G photon/s is observed, with a dynamic range of ≈ 79dB, a sensitivity of ≈ −31.7dBm at 100MHz and a BER of ≈ 1x10−9. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32x32 SPAD array, achieves a minimum dead time of 5.9ns, and a median dark count rate (DCR) of 2.5kHz per SPAD. High noise devices can be weighted or removed to optimise the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed. The thesis concludes that data can be captured well with such a device but more electrical energy is needed at the receiver due to its fundamental operation. Overall, optical power can be reduced, allowing significant savings in either transmitter power or the transmission length, along with the advantages of an integrated digital chip.

Le sujet de cette thèse traite des effets des radiations spatiales sur des détecteurs CMOS à avalanches, et particulièrement sur les dispositifs SPADs (pour Single Photon Avalanche Diode en anglais, ou photodiode à avalanche à photon unique). Ces photodiodes présentent un gain interne presque infini et sont donc sensibles à des très faibles conditions de lumières. Ainsi, avec en plus une excellente résolution temporelle, ces capteurs peuvent être très intéressant pour des applications spatiales nécessitant des mesures de temps de vols, comme la topographie d’objets célestes ou les Rendez-vous spatiaux. Cependant, l’espace est un environnement hostile du fait des radiations provenant du Soleil, des particules piégées dans la magnétosphère terrestre ainsi qu’au-delà du système solaire. De ce fait, dans le cadre de ces travaux de thèse, un modèle est mis en place pour prédire la dégradation du courant d’obscurité des SPADs, le Dark Count Rate (DCR), après des irradiations aux protons. Expérimentalement, deux technologies de matrices de SPADs sont irradiées avec des protons, des rayons X et des rayons γ. De ce fait, les effets ionisants et non-ionisants sont investigués pour ces capteurs à avalanches, et des différences en comparaison avec les pixelsdes capteurs d’images standard sont soulignées. Ensuite, les caractéristiques des défauts induits par la création d’états d’interface entre les oxides et le silicium et les dommages de déplacement atomique dans le substrat sont examinées, avec notamment la présence de comportement RTS (Random Telegraph Signal). Enfin, l’identification de la nature de ces défauts est réalisée par l’intermédiaire de recuits isochrones après l’expositions des matrices de SPADs aux trois différentes radiations mentionnées au-dessus<br>The subject of this thesis deals with the effects of space radiation on CMOS avalanche detectors, particularly on Single Photon Avalanche Diodes (SPADs). These photodiodes exhibit nearly infinite internal gain and are therefore sensitive to very low light conditions. Thus, with excellent temporal resolution, these sensors can be very interesting for space applications requiring time-of-flight measurements, such as the topography of celestial objects or space Rendezvous. However, space is a hostile environment due to radiation from the Sun, particles trapped in the Earth’s magnetosphere, and beyond the solar system. Consequently, within the framework of this thesis work, a model is established to predict thedegradation of the dark current of SPADs, the Dark Count Rate (DCR), after proton irradiations. Experimentally, two SPAD array technologies are irradiated with protons, X-rays, and γ rays. Hence, ionizing and non-ionizing effects are investigated for these avalanche sensors, and differences compared to pixels of standard image sensors are highlighted. Subsequently, the characteristics of defects induced by the creation of interface traps between oxides and silicon and atomic displacement damage in the substrate are examined, including the presence of Random Telegraph Signal (RTS) behaviors. Finally, the nature of these defects is identified through isochronal annealing after irradiations of the SPAD arrays using the three different radiation types mentioned above

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining &gt;130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining &gt;130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

Cette thèse fait progresser la modélisation, la simulation et l'optimisation des diodes à avalanche à photon unique (Single-Photon Avalanche Diodes, ou SPAD), capables de détecter des photons individuels avec une grande sensibilité. Les SPAD sont essentiels dans des applications telles que les communications quantiques, l'imagerie et les mesures de temps de vol, où la détection précise de photons uniques est cruciale. Cependant, les SPAD fonctionnent par des processus complexes et stochastiques, comme la multiplication par avalanche, la gigue temporelle et l'extinction, rendant leur modélisation précise difficile. Cette thèse aborde ces complexités en développant des modèles de simulation avancés, en appliquant des techniques d'optimisation et en explorant des méthodes pour améliorer les performances des SPAD. La thèse commence par une revue de la technologie SPAD et de ses principes. Les SPAD détectent les photons en déclenchant un processus d'avalanche dans un champ électrique élevé, qui amplifie le signal du photon en une impulsion mesurable. Cette thèse étend le modèle de McIntyre, traditionnellement utilisé pour les dispositifs à avalanche, en trois dimensions, permettant des simulations plus précises des géométries complexes et des champs électriques des SPAD. Une contribution majeure est l'introduction de l'optimisation par essaim de particules (Particle Swarm Optimization, ou PSO) couplée à un solveur de Poisson non linéaire pour optimiser des paramètres de SPAD comme la tension de claquage, la largeur de la zone de déplétion et la gigue temporelle. La PSO explore efficacement l'espace de conception, équilibrant les exigences de performance et permettant la création de SPADs adaptés à diverses applications, de l'imagerie en basse lumière à la détection rapide de photons. Pour améliorer la précision des simulations de SPAD, la thèse développe une méthode Monte Carlo par advection-diffusion (ADMC), qui combine les processus d'advection et de diffusion pour modéliser de manière réaliste le transport des porteurs, notamment dans les zones de champ élevé où les avalanches se produisent. Ce modèle surmonte les limites des méthodes Monte Carlo traditionnelles, permettant une représentation précise de la gigue temporelle, de la probabilité de claquage et du taux de comptage de bruit.La thèse culmine avec le développement d'un modèle auto-cohérent Monte Carlo-Poisson pour les simulations transitoires de SPAD. En combinant ADMC avec un solveur de Poisson en 3D, ce modèle capture en temps réel des comportements critiques des SPAD, tels que l'initiation de l'avalanche, la réduction de champ et l'extinction. Cette boucle de rétroaction est essentielle pour comprendre les comportements transitoires des SPAD, car les porteurs influencent le champ électrique lorsqu'ils s'accumulent. Ce modèle est particulièrement utile pour étudier la nature stochastique de l'extinction, qui affecte la fiabilité et la temporalité des SPAD. En résumé, cette thèse apporte des contributions significatives à la modélisation, la simulation et l'optimisation des SPAD. En développant un modèle auto-cohérent Monte Carlo-Poisson et en intégrant des techniques avancées d'optimisation, ce travail fournit un cadre complet pour améliorer les performances des SPAD et soutenir les avancées futures dans des applications de haute précision<br>This thesis advances the modeling, simulation, and optimization of Single-Photon Avalanche Diodes (SPADs), which detect individual photons with high sensitivity. SPADs are essential for applications in quantum communications, imaging, and time-of-flight measurements, where precise single-photon detection is crucial. However, SPADs operate through complex, stochastic processes such as avalanche multiplication, timing jitter, and quenching, making accurate modeling a challenge. This thesis addresses these complexities by developing advanced simulation models, applying optimization techniques, and exploring methods to enhance SPAD performance. The thesis starts by reviewing SPAD technology and principles. SPADs detect photons by triggering an avalanche process in a high electric field, which amplifies the photon's signal into a measurable pulse. This thesis extends the McIntyre model, traditionally used for avalanche devices, to three dimensions, allowing for more accurate simulations of complex SPAD geometries and electric fields. A core contribution is introducing Particle Swarm Optimization (PSO) coupled with a nonlinear Poisson solver to optimize SPAD parameters like breakdown voltage, depletion width, and timing jitter. PSO navigates the design space effectively, balancing competing performance requirements and enabling customized SPADs for different applications, from low-light imaging to fast photon counting. To improve SPAD simulation accuracy, the thesis develops an Advection-Diffusion Monte Carlo (ADMC) method, which combines advection and diffusion processes for a realistic model of carrier transport, especially in high-field regions where avalanches occur. This model overcomes limitations of traditional Monte Carlo methods, achieving accurate representations of timing jitter, breakdown probability, and dark count rate. The thesis culminates in a self-consistent Monte Carlo-Poisson model for transient SPAD simulations. By combining ADMC with a 3D Poisson solver, this model captures critical SPAD behaviors like avalanche initiation, field depletion, and quenching in real time. This feedback loop is essential for understanding transient SPAD behaviors, as carriers impact the electric field as they accumulate. The model is especially useful for studying the stochastic nature of quenching, which influences SPAD reliability and timing. In summary, this thesis makes significant contributions to SPAD modeling, simulation, and optimization. By creating a self-consistent Monte Carlo-Poisson model and integrating advanced optimization techniques, this work provides a comprehensive framework for improving SPAD performance and supports further advances in high-precision applications

Ce travail a pour objectif la conception, la simulation, la modélisation et la caractérisation électrique de diodes à avalanche à photon unique (Single Photon Avalanche Diodes - SPAD) intégrées dans une technologie CMOS Fully Depleted Silicon on Insulator - FDSOI. Les SPAD sont des diodes (jonctions PN) polarisées en inverse au-delà de la tension de claquage, fonctionnant dans le mode Geiger. Grace à leur haute sensibilité et rapidité, les SPAD sont utiles pour plusieurs applications, telles que les mesures de temps de vol (Time of Flight - ToF), l’imagerie médicale (Fluorescence Lifetime Imaging Microscopy - FLIM), ainsi que la détection de particules chargées, dans le domaine de la physique de haute énergie. L’intégration de SPAD dans une technologie CMOS FDSOI permet d’obtenir une intégration 3D monolithique intrinsèque avec la diode sous l’oxyde enterré, et l’électronique associée dans le film silicium, en optimisant ainsi le facteur de remplissage. Afin d’analyser le comportement des SPAD FDSOI, plusieurs cellules ont été conçues, respectant les principales règles de dessin imposées par la fonderie, mais présentant des variantes structurelles telles que la zone d'intégration, la géométrie, la distance de garde et le circuit d’étouffement. Des simulations TCAD et des calculs analytiques ont été effectués afin d'estimer les principales figures du mérite de SPAD. Plusieurs modèles d'avalanche et de génération de porteurs ont été étudiés pour une meilleure adaptation du modèle simulé aux dispositifs fabriqués. Des caractérisations électriques ont été réalisées pour estimer des paramètres importants tels que la tension de claquage, le taux de comptage dans l'obscurité (DCR) et la réponse en l'électroluminescence. Bien que les résultats obtenus restent inférieurs par rapport à l'état de l’art, la faisabilité d’intégration de SPAD dans une technologie FDSOI a été démontrée comme preuve de concept, mais des améliorations sont nécessaires et certaines pistes sont proposées<br>This work aims at the design, simulation, modelling and electrical characterization of Single Photon Avalanche Diodes (SPAD) in an advanced Fully Depleted Silicon on Insulator (FDSOI) technology. SPADs are PN junctions reversed bias above breakdown voltage, operating in the so-called Geiger mode. Such an implementation should provide an intrinsic monolithic integration of those devices, along with their mandatory associated electronics, thanks to the buried oxide layer present in that technology, optimizing fill factor. Due to its high sensitivity, SPAD are useful for several applications, such as Time of Flight (ToF) and Fluorescence Lifetime Imaging Microscopy (FLIM) measurements, as well as the detection of charged particles, in high-energy physics domain. The designed cells follow the main design rules imposed by the foundry and present variations in aspect as integration zone, geometry, guard distance and quenching circuit. TCAD simulations were performed in order to estimate some of the SPAD main Figures of Merit. Several avalanche and carrier generation models were studied for better adapting the simulated model to the actual fabricated devices. Electrical characterizations were realized for estimating important parameters such as breakdown voltage, Dark Count Rate (DCR) and electroluminescence response. Although the obtained results are still poor when compared to State-of-the-Art, its feasibility was demonstrated and can be used as a proof of concept, at the same time that improvements are proposed

FLIM is branch of microscopy mainly used in biology which is quickly improving thanks to a rapid enhancement of instrumentation and techniques enabled by new sensors. In FLIM, the most precise method of measuring fluorescent decays is called TCSPC. High voltage PMT detection devices together with costly and bulky optical setups which scan the sample are usually required in TCSPC instrumentation. SPADs have enabled a big improvement in TCSPC measurement setup, providing a CMOS compatible device which can be designed in wide arrays format. However, sensors providing in-pixel TCSPC do not scale in size and in large array like the time-gated SPAD pixel sensors do. Time-gated pixels offer a less precise lifetime estimation, discarding any photon information outside a given time window, but this loss in photon-efficiency is offset by gains in pixel size. This work is aimed at the development of a wide field TCSPC sensor with a pixel size and fill factor able to reduce the cost of such devices and to obtain a high resolution time-resolved fluorescence image in the shortest time possible. The study focuses on SPAD and pixel design required to maximise the fill factor in sub 10 μm pixel pitch. Multiple pixel designs are proposed in order to reduce pixel area and so enable affordable wide array TCSPC systems. The first proposed pixel performs the CMM lifetime estimation in order to reduce the frame rate needed to stream the data out of the SPAD array. This pixel is designed in a 10 μm pitch and attains with the most aggressive design a fill factor of 10:17 %. A second design proposes an analogue TCSPC which consists in a S/H TAC circuitry. This simpler pixel can achieve a higher fill factor of 19:63% as well as smaller pitch of 8 μm thanks to the adoption of SPAD n-well and electronics area sharing. This last design is implemented in a 320 x 256 SPAD array in which is included part of a novel ADC aimed at reduction of the processing time required to build a TCSPC histogram. A more conventional analogue readout is used to evaluate the pixel performance as well as a more fine TCSPC histogram. The device was used to measure the fluorescence lifetime of green micro-spheres while the 2b flash ADC is used to demonstrate rapid resolution and separation of two different fluorescence decays.

Fluorescence based analysis is a fundamental research technique used in the life sciences. However, conventional fluorescence intensity measurements are prone to misinterpretation due to illumination and fluorophore concentration non-uniformities. Thus, there is a growing interest in time-resolved fluorescence detection, whereby the characteristic fluorescence decay time-constant (or lifetime) in response to an impulse excitation source is measured. The sensitivity of a sample’s lifetime properties to the micro-environment provides an extremely powerful analysis tool. However, current fluorescence lifetime analysis equipment tends to be bulky, delicate and expensive, thereby restricting its use to research laboratories. Progress in miniaturisation of biological and chemical analysis instrumentation is creating low-cost, robust and portable diagnostic tools capable of high-throughput, with reduced reagent quantities and analysis times. Such devices will enable point-of-care or in-the-field diagnostics. It was the ultimate aim of this project to produce an integrated fluorescence lifetime analysis system capable of sub-nano second precision with an instrument measuring less than 1cm3, something hitherto impossible with existing approaches. To accomplish this, advances in the development of AlInGaN micro-LEDs and high sensitivity CMOS detectors have been exploited. CMOS allows electronic circuitry to be integrated alongside the photodetectors and LED drivers to produce a highly integrated system capable of processing detector data directly without the need for additional external hardware. In this work, a 16x4 array of single-photon avalanche diodes (SPADs) integrated in a 0.35μm high-voltage CMOS technology has been implemented which incorporates two 9-bit, in-pixel time-gated counter circuits, with a resolution of 400ps and on-chip timing generation, in order to directly process fluorescence decay data. The SPAD detector can accurately capture fluorescence lifetime data for samples with concentrations down to 10nM, demonstrated using colloidal quantum dot and conventional fluorophores. The lifetimes captured using the on-chip time gated counters are shown to be equivalent to those processed using commercially available external time-correlated single-photon counting (TCSPC) hardware. A compact excitation source, capable of producing sub-nano second optical pulses, was designed using AlInGaN micro-LEDs bump-bonded to a CMOS driver backplane. A series of driver array designs are presented which are electrically contacted to an equivalent array of micro-LEDs emitting at a wavelength of 370nm. The final micro-LED driver design is capable of producing optical pulses of 300ps in width (full width half maximum, FWHM) and a maximum DC optical output power of 550μW, this is, to the best of our knowledge, the shortest reported optical pulse from a CMOS driven micro-LED device. By integrating an array of CMOS SPAD detectors and an array of CMOS driven AlInGaN micro-LEDs, a complete micro-system for time-resolved fluorescence analysis has been realised. Two different system configurations are evaluated and the ability of both topologies to accurately capture lifetime data is demonstrated. By making use of standard CMOS foundry technologies, this work opens up the possibility of a low-cost, portable chemical/bio-diagnostic device. These first-generation prototypes described herein demonstrate the first time-resolved fluorescence lifetime analysis using an integrated micro-system approach. A number of possible design improvements have been identified which could significantly enhance future device performance resulting in increased detector and micro-LED array density, improved time-gate resolution, shorter excitation pulse widths with increased optical output power and improved excitation light filtering. The integration of sample handling elements has also been proposed, allowing the sample of interest to be accurately manipulated within the micro-environment during investigation.