Journal articles: 'SOC [System-on-Chip Soc]'

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Sagar, G. Venkataramana, and Dr K. Srinivasa Rao. "Reconfigurable FFT System on Chip (SOC)." International Journal of Computer Applications 11, no. 5 (December 10, 2010): 35–38. http://dx.doi.org/10.5120/1575-2107.

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Chitti, Sridevi, P. Chandrasekhar, and M. Asharani. "A Unique Test Bench for Various System-on-a-Chip." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (December 1, 2017): 3318. http://dx.doi.org/10.11591/ijece.v7i6.pp3318-3322.

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This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

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Jia, Hao, Shanglin Yang, Ting Zhou, Sizhu Shao, Xin Fu, Lei Zhang, and Lin Yang. "WDM-compatible multimode optical switching system-on-chip." Nanophotonics 8, no. 5 (April 27, 2019): 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.

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AbstractThe development of optical interconnect techniques greatly expands the communication bandwidth and decreases the power consumption at the same time. It provides a prospective solution for both intra-chip and inter-chip links. Herein reported is an integrated wavelength-division multiplexing (WDM)-compatible multimode optical switching system-on-chip (SoC) for large-capacity optical switching among processors. The interfaces for the input and output of the processor signals are electrical, and the on-chip data transmission and switching process are optical. It includes silicon-based microring optical modulator arrays, mode multiplexers/de-multiplexers, optical switches, microring wavelength de-multiplexers and germanium-silicon high-speed photodetectors. By introducing external multi-wavelength laser sources, the SoC achieved the function of on-chip WDM and mode-division multiplexing (MDM) hybrid-signal data transmission and switching on a standard silicon photonics platform. As a proof of concept, signals with a 25 Gbps data rate are implemented on each microring modulator of the fabricated SoC. We illustrated 25 × 3 × 2 Gbps on-chip data throughput with two-by-two multimode switching functionality through implementing three wavelength-channels and two mode-channel hybrid-multiplexed signals for each multimode transmission waveguide. The architecture of the SoC is flexible to scale, both for the number of supported processors and the data throughput. The demonstration paves the way to a large-capacity multimode optical switching SoC.

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Liu, Xiang Wen, and Li Min Liu. "The IP Design for a Customized Mobile SoC." Advanced Materials Research 605-607 (December 2012): 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

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Dorothy, R., and Sasilatha T. "System on Chip Based RTC in Power Electronics." Bulletin of Electrical Engineering and Informatics 6, no. 4 (December 1, 2017): 358–63. http://dx.doi.org/10.11591/eei.v6i4.867.

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

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Patil, Mr Abhijit, and Mr A. A. Shirolkar. "A Review on System-on-Chip SoC Designs for Real-Time Industrial Application." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (December 31, 2017): 1534–37. http://dx.doi.org/10.31142/ijtsrd7077.

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IIDA, Atsuko, Yutaka ONOZUKA, Hiroshi YAMADA, Toshihiko NAGANO, and Kazuhiko ITAYA. "High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000820–27. http://dx.doi.org/10.4071/isom-2011-wp5-paper3.

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This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

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Jung, Jun-Mo. "Low Power Test for SoC(System-On-Chip)." Journal of information and communication convergence engineering 9, no. 6 (December 31, 2011): 729–32. http://dx.doi.org/10.6109/ijice.2011.9.6.729.

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Charles, Subodha, and Prabhat Mishra. "A Survey of Network-on-Chip Security Attacks and Countermeasures." ACM Computing Surveys 54, no. 5 (June 2021): 1–36. http://dx.doi.org/10.1145/3450964.

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With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-Chip (SoC) architectures to cater to their communication requirements. NoC has received significant attention from both attackers and defenders. The increased usage of NoC and its distributed nature across the chip has made it a focal point of potential security attacks. Due to its prime location in the SoC coupled with connectivity with various components, NoC can be effectively utilized to implement security countermeasures to protect the SoC from potential attacks. There is a wide variety of existing literature on NoC security attacks and countermeasures. In this article, we provide a comprehensive survey of security vulnerabilities in NoC-based SoC architectures and discuss relevant countermeasures.

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Marrouche, Wissam, Rana Farah, and Haidar M. Harmanani. "A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules." International Journal of Computational Intelligence and Applications 17, no. 02 (June 2018): 1850010. http://dx.doi.org/10.1142/s1469026818500104.

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System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

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Pan, Zhong Liang, and Ling Chen. "Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip." Materials Science Forum 663-665 (November 2010): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.663-665.670.

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The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

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Tulpule, Bhal, Bruce Ohme, Mark Larson, Al Behbahani, John Gerety, and Al Steines. "A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000278–84. http://dx.doi.org/10.4071/hitec-tha11.

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This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.

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Prasad Acharya, G., and M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.

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The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

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Tulpule, Bhal, and Alireza R. Behbahani. "System On Chip (SOC) ASIC chipset for Smart Actuators in Distributed Propulsion Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000040–45. http://dx.doi.org/10.4071/2016-hitec-40.

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Abstract This paper describes the results of the risk reduction testing task recently completed by Embedded Systems LLC under the Air Force SBIR contract {5} titled “Improved Full Authority Digital Engine Control (FADEC) System”. The objective of this program has been to develop a hierarchical, distributed architecture for future propulsion FADEC and aerospace control systems with flexible, scalable and reconfigurable Smart Nodes (SN) built with high temperature capable devices. A key part of this program is the design, development and validation of the System On Chip (SOC) chipset in high temperature (225 Deg. C) SOI (Silicon On Insulator) technology ASIC (Application Specific Integrated Circuit) devices. The SOC chipset designed by Embedded Systems LLC provides the scalability and reconfigurability that enables the Smart Node to interfaces with most sensors and actuators found in FADEC and other aircraft control systems. The analog portion of this 2-chip SOC chipset fabricated by Honeywell using their SOI process is working properly. The digital portion of the SOC chipset, currently implemented in a commercial temperature FPGA (Field Programmable Gate Array), contains important computational functions needed for reconfiguring the SOC and performing complex control functions, such as real time control of an actuator, The risk reduction task was therefore focused on verification and validation of these key functions in a real environment before converting the design into an ASIC. The recent successful demonstration of the real time actuator control capability has minimized the risks and cleared the way for the digital ASIC implementation. The complete high temperature SOC chipset is expected to be available in late 2016.

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Anil Chowdary, T., and M. Durga Prasad. "A Short Paper on Testability of a SoC." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 326. http://dx.doi.org/10.14419/ijet.v7i3.12.16051.

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The latest advances in semiconductor mix improvement accomplished assembling of expansive number of areas on a solitary chip Test organizing is an essential issue in System on-a-chip (SOC) test mechanization. Effective test masterminds minimize the general structure test application time, keep away from test asset clashes, and most outrageous power scrambling amidst test mode. For solid system on-chip, the circuit ought to be without fault since a solitary blame is likely going to make the entire chip vain. Finding the obstructions and utilization of helpful measures for same chip would diminish the running cost of the structure.. The remarkable move toward test cost emergency, where semiconductor test costs start to approach or beat in more expenses has driven test organizers to apply new reactions for the issue of testing System-On-Chip (SoC) masterminds containing different IP (Intellectual Property) centers. since it is not yet possible to apply non particular test structures to an IP focus inside a SoC, the progress of different close frameworks, and the landing of new industry measures, for instance, IEEE 1500 and IEEE 1450.6, may begin to change this condition. This paper looks rules and at several systems at present utilized by SoC tests engineers [14].

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Nurmi, Jari. "International Symposium on System-on-Chip 2011." International Journal of Embedded and Real-Time Communication Systems 3, no. 4 (October 2012): 83–90. http://dx.doi.org/10.4018/jertcs.2012100105.

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International Symposium on System-on-Chip 2011 was the 13th SoC event in Tampere, Finland. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2011 contents, and in particular in its tutorial and invited talks.

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Su, Ching-Lung, Tse-Min Chen, and Kuo-Hsuan Wu. "A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation." VLSI Design 2013 (May 16, 2013): 1–10. http://dx.doi.org/10.1155/2013/529150.

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A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally, prototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and estimation. This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of SoC performance. The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor, on-chip bus structure, IP design, embedded OS, GUI systems, and application programs. The prototype configuration, chip post-layout simulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system performance was examined according to the proposed estimation models, the profiling result of the application programs ported on prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that the proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level 2 specifications.

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Liu, Xiang Wen, and Li Min Liu. "A Mobile Computing SoC Design." Advanced Materials Research 605-607 (December 2012): 2049–52. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2049.

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System on a chip, SoC, is an advanced technology of embedded systems. Mobile computing may support modern life style. Combination of SoC and mobile computing will produce a new product. In this paper, SoC, mobile computing and mobile computing SoC design are discussed. The mobile SoC can be used all mobile control fields, such as rescue, smart houses and mobile payment.

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Huang, LinYun, Young-Pil Lee, Yong-Seon Moon, and Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device." International Journal of Humanoid Robotics 14, no. 04 (November 16, 2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.

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Currently, as the requirements for simple implementations in the motor control technologies increase, System-on-Chip (SoC) device such as Zynq All Programmable SoC was devised to meet those requirements. Because this CPU and FPGA can be assembled into one SoC device, we can consolidate motor-control functions and additional processing tasks into a single SoC device. The control algorithms, networking and other tasks, are off-loaded to the programmable logic that can include multiple control cores and multiple control system. This SoC system with a single chip can allow the hardware design with a single chip, hence, we can implement to control the motor to be simpler, more reliable, and less expensive. In this paper, in order to implement motor controller, we apply latest All Programmable SoC technologies for humanoid robot or industrial device that is integrated with FPGA technologies and embedded processor technologies. We also propose the structure of motor controller that decentralizes the function of motor driver from previous typical motor driver into FPGA and level of embedded processor by using All Programmable SoC for humanoid robot or industrial device. We verify the possibilities of applying the novel implemented motor controller in Zynq EPP (Extensible Processing Platform) which is one kind of All Programmable SoC made by Xilinx. To do this, we perform velocity control and position control with digital PI controller on the BLDC motor.

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Ritter, Philipp. "Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS." International Journal of Microwave and Wireless Technologies 13, no. 6 (February 11, 2021): 523–31. http://dx.doi.org/10.1017/s1759078721000088.

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AbstractNext-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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He, Ji Lin, Zheng Yuan, and Qing Hua He. "Clustering and Real-Time Analysis of Robot Controller Based on System on Chip." Advanced Materials Research 403-408 (November 2011): 3797–804. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.3797.

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Based on the most prosperous System on Chip (SOC) in the field of microelectronics, the open and real-time robot controller was analyzed, the application and development platform was built. By means of representative evaluation index, cohesion and coupling, the modularized design and the open architecture of robot controller were implemented. It is proved that the average distance between the same modules is short, and therefore the system is better cohesive. And the average distance between different modules is long, and therefore less coupled. Consequently, the whole system is excellent in openness. At the same time, the real-time schedule of controller tasks is analyzed from theory and experiment. It is proved that the controller based on SOC is excellent in real-time performance. The experiment showed that SOC-based robot controller is highly modularized, the parameters is clear, the architecture is easily implemented and revised, and therefore is adaptive to different controlling requirement and module building.

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Tan, Junyan, and Chunhua Cai. "An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950075. http://dx.doi.org/10.1142/s0218126619500750.

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Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.

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Wang, Cong, Yi Long Liu, Peng Long Jiang, Qing Zhen Zhang, Fei Tao, and Lin Zhang. "Multiple Faults Detection with SoC Dynamic Reconfiguration System Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2642–45. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2642.

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Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

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Borel, Joseph. "System on a chip (SoC) and design methodology challenges." Microelectronic Engineering 54, no. 1-2 (December 2000): 15–22. http://dx.doi.org/10.1016/s0167-9317(00)80055-6.

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HARMANANI, HAIDAR M., and HASSAN A. SALAMY. "A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS." International Journal of Computational Intelligence and Applications 06, no. 04 (December 2006): 511–30. http://dx.doi.org/10.1142/s1469026806002052.

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This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

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Zhang, Wei. "Based on SoC Technology Frequency Measurement Meter." Applied Mechanics and Materials 556-562 (May 2014): 2974–77. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2974.

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SoC is the ASICS (ApplieationSpeenIetgratdeCierulst) design methodology of the new technology, refers to the embedded system as the core technology used in PI-based, set of software and hardware in one, and the pursuit of products inclusive of the largest integrated system chip. The article in-depth exploration into the complexity of using VHDL language and system programmable logic device (CPLD) to develop "system-on-chip (SoC)" - such as adaptive frequency measurement accuracy of the basic methods to overcome the system of the previous frequency measurement accuracy is not high , measuring the accuracy of the process of change, approaching the speed of slow-type shift shortcomings.

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DOERING, ROBERT R. "System-on-Chip Integration." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 325–32. http://dx.doi.org/10.1142/s0129156402001289.

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Numerous "signal-processing products" are now driving the semiconductor market for SOC solutions enabling real-time performance, low-cost, low-power, portability, etc. A primary limit on the types of electronic (or other) functions that will be integrated into future SOCs is cost of integration, which tends to grow non-linearly with process complexity and chip area. A near-continuum of System-on/in-X solutions is emerging between traditional System-on-Chip and System-on-Board. These approaches span the tradeoff between bandwidth and cost. For the foreseeable future, digital CMOS will continue to serve as a "host platform" for integrating a wide range of mechanical, optical, biological, and, perhaps, even "quantum" technologies.

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N., Mohan Kumar. "ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET." Journal of Electronics and Informatics 01, no. 01 (September 29, 2019): 51–59. http://dx.doi.org/10.36548/jei.2019.1.006.

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As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

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Budiarto, Rahmat, Lelyzar Siregar, and Deris Stiawan. "Network-on-Chip Paradigm for System-on-Chip Communication." Computer Engineering and Applications Journal 6, no. 1 (March 1, 2017): 1–4. http://dx.doi.org/10.18495/comengapp.v6i1.186.

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Developments of modern technologies in electronics, such as communication, Internet, pervasive and ubiquitous computing and ambient intelligence have figured largely our life. In our day micro-electronic products inspire the ways of learning, communication and entertainment. These products such as laptop computer, mobile phones, and personal handheld sets are becoming faster, lighter in weight, smaller in size, larger in capacity, lower in power consumptions, cheaper and functionally enhanced. This trend will persistently continue. Following this trend, we could integrate more and more complex applications and even systems onto a single chip. The System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips became key driving force for the developments.

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Du, Xue Cheng, Shu Huan Liu, Chao Hui He, Xin Du, Yong Hong Li, Yao Zhang, Wei Chen, Xin Zan Liu, and Dong Sheng He. "Single Event Effects Testing of Xilinx Zynq-7010 SoC with ²³⁹Pu Alpha Irradiation." Applied Mechanics and Materials 678 (October 2014): 268–73. http://dx.doi.org/10.4028/www.scientific.net/amm.678.268.

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Estimating the radiation sensitivity and radiation response of individual electronic units embedded in System on chip (SoC) is important for SoC error rate predicting and fault tolerant system designing. In this paper, the experimental techniques for detecting the single event effects (SEE) of SoC were introduced. The test system has been established and the irradiation experiments have been performed for testing SEE of Xilinx Zynq-7010 SoC with 239Pu alpha radiation source. Several single events functional Interrupt (SEFI) of some typical registers within the SoC sample were detected after receiving the total fluence of 6.101. In the end, the mechanisms of SEFI induced by alpha irradiation on SoC were discussed and analyzed.

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Gardel, Alfredo, Pablo Montejo, Jorge García, Ignacio Bravo, and José L. Lázaro. "Parametric Dense Stereovision Implementation on a System-on Chip (SoC)." Sensors 12, no. 2 (February 10, 2012): 1863–84. http://dx.doi.org/10.3390/s120201863.

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Adiono, Trio, Syifaul Fuada, and Rosmianto Aji Saputro. "Rapid Development of System-on-Chip (SoC) for Network-Enabled Visible Light Communications." International Journal of Recent Contributions from Engineering, Science & IT (iJES) 6, no. 1 (March 19, 2018): 107. http://dx.doi.org/10.3991/ijes.v6i1.8098.

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<p class="0abstract">Visible Light Communication (VLC) is an emerging optical communication technology with rapid development nowadays. VLC is considered as a compliment and successor of radio-frequency (RF) wireless communication. There are various typical implementations of VLC in which one of them is for exchanging data TCP/IP packets, thus the user can browse the internet as in established Wireless fidelity (Wi-Fi) technology. Briefly, we can call it by Light fidelity (Li-Fi). This paper described the design and implementation of System-on-Chip (SoC) subsystem for Li-Fi application where the implemented SoC consists of hardware (H/W) and software (S/W). In the H/W aspect, Physical Layer (PHY) is made by using UART communication with Ethernet connection to communicate with Host/Device personal-computer (PC). In the S/W aspect, Xillinux operating system (OS) is used. The H/W- as well as S/W-SoC, are realized in FPGA Zybo Zynq-7000 EPP development board. The functional test result shows (without optical channel or Zybo-to-Zybo only) that the implemented SoC is working as expected. It is able to exchange TCP/IP packets between two PCs. Moreover, Ethernet connection has bandwidth up to 83.6 Mbps and PHY layer <em>baud rate</em> has bandwidth up to 921600 bps.</p>

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Kanda, Guard, Seungyong Park, and Kwangki Ryoo. "Run-Time Hardware Trojans Detection Using On-Chip Bus for System-on-Chip Design." Journal of the Korea Institute of Information and Communication Engineering 20, no. 2 (February 29, 2016): 343–50. http://dx.doi.org/10.6109/jkiice.2016.20.2.343.

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Nurmi, Jari. "International Symposium on System-on-Chip 2010." International Journal of Embedded and Real-Time Communication Systems 2, no. 4 (October 2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.

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International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks.

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HARMANANI, HAIDAR M., and HASSAN A. SALAMY. "POWER-CONSTRAINED SYSTEM-ON-A-CHIP TEST SCHEDULING USING A GENETIC ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 03 (June 2006): 331–49. http://dx.doi.org/10.1142/s0218126606003106.

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This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

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Ezhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.

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Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

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Mody, Mihir, Kedar Chitnis, Hemant Hariyani, Shyam Jagannathan, Jason Jones, Gregory Shurtz, Abhishek Shankar, et al. "Single Chip Auto-Valet Parking System with TDA4VMID SoC." Electronic Imaging 2021, no. 17 (January 18, 2021): 113–1. http://dx.doi.org/10.2352/issn.2470-1173.2021.17.avm-113.

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Auto-Valet parking is a key emerging function for Advanced Driver Assistance Systems (ADAS) enhancing traditional surround view system providing more autonomy during parking scenario. Auto-Valet parking system is typically built using multiple HW components e.g. ISP, micro-controllers, FPGAs, GPU, Ethernet/PCIe switch etc. Texas Instrument’s new Jacinto7 platform is one of industry’s highest integrated SoC replacing these components with a single TDA4VMID chip. The TDA4VMID SoC can concurrently do analytics (traditional computer vision as well as deep learning) and sophisticated 3D surround view, making it a cost effective and power optimized solution. TDA4VMID is a truly heterogeneous architecture and it can be programmed using an efficient and easy to use OpenVX based middle-ware framework to realize distribution of software components across cores. This paper explains typical functions for analytics and 3D surround view in auto-valet parking system with data-flow and its mapping to multiple cores of TDA4VMID SoC. Auto-valet parking system can be realized on TDA4VMID SOC with complete processing offloaded of host ARM to the rest of SoC cores, providing ample headroom for customers for future proofing as well as ability to add customer specific differentiation.

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STAMENKOVIĆ, ZORAN. "SOC DESIGN FOR WIRELESS COMMUNICATIONS." Journal of Circuits, Systems and Computers 20, no. 08 (December 2011): 1505–27. http://dx.doi.org/10.1142/s0218126611008055.

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The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.

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Sheng, Duo, Hsueh-Ru Lin, and Li Tai. "Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications." Electronics 10, no. 13 (June 30, 2021): 1587. http://dx.doi.org/10.3390/electronics10131587.

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High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

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Han, Xi, Zhe Ying Li, Yuan Sheng Liu, and Wen Liang Niu. "Design of SoC Verification System Based on Multi-FPGA." Advanced Materials Research 532-533 (June 2012): 1110–14. http://dx.doi.org/10.4028/www.scientific.net/amr.532-533.1110.

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As one of the most advanced research field, the problem of SoC (System on a Chip) design is getting more and more attention. With the promotion of its theory and technique, SoC verification turns to one of the most significant part in the procedure of realizing a usable integrated circuit. And verification using FPGA (Field Programmable Gate Array) which must obey a set of strict technological process is a kind of general way. With the growing complexity and integrated scale of SoC design, a single FPGA chip could hardly satisfy the verification requirement. Then the method of verification using multi-FPGA is taken and expresses some advantages in some respects. Multi-FPGA verification is still in the initial step situation and has a broad developing space. The architecture of multi-FPGA verification platform is given in this paper, as well as some related key technical problem and solutions.

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Parmar, Harikrishna, and Usha Mehta. "ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC." Journal of Low Power Electronics and Applications 9, no. 2 (June 17, 2019): 19. http://dx.doi.org/10.3390/jlpea9020019.

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Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

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Choi, M., N. Park, V. Piuri, and F. Lombardi. "Evaluating the Repair of System-on-Chip (SoC) Using Connectivity." IEEE Transactions on Instrumentation and Measurement 53, no. 6 (December 2004): 1464–72. http://dx.doi.org/10.1109/tim.2004.834603.

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Durai, Sharmila, and Rangarajan Parthasarathy. "Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 511–16. http://dx.doi.org/10.1166/jctn.2017.6355.

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System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).

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Li, Xiao Min, and Shuang Hua Huang. "Study on Bus Assignment Algorithm for SOC Test." Applied Mechanics and Materials 713-715 (January 2015): 1252–55. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.1252.

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The main concern is over rising temperature during the testing of complex system-on-chip (SOC), this paper studies SOC wrapper and test access mechanism (TAM), and proposes an improved algorithm of TAM assignment under the constraints of temperature. The algorithm uses temperature superposition method and adds compression process. This algorithm can find the test structure that uses shorter test time.

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Springer, Tom, Elia Eiroa-Lledo, Elizabeth Stevens, and Erik Linstead. "On-Device Deep Learning Inference for System-on-Chip (SoC) Architectures." Electronics 10, no. 6 (March 15, 2021): 689. http://dx.doi.org/10.3390/electronics10060689.

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As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning algorithms remain limited. In particular, better mechanisms for real-time scheduling in the context of machine learning applications will prove to be critical as these technologies move to the edge. In order to address some of these challenges, we present a resource management framework designed to provide a dynamic on-device approach to the allocation and scheduling of limited resources in a real-time processing environment. These types of mechanisms are necessary to support the deterministic behavior required by the control components contained in the edge nodes. To validate the effectiveness of our approach, we applied rigorous schedulability analysis to a large set of randomly generated simulated task sets and then verified the most time critical applications, such as the control tasks which maintained low-latency deterministic behavior even during off-nominal conditions. The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application to perform simple object detection. The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including widely-used, industry-standard real-time operating systems.

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Tang, Qi, Biao Guo, and Zhe Wang. "Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-Chip." Electronics 9, no. 9 (August 21, 2020): 1362. http://dx.doi.org/10.3390/electronics9091362.

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A heterogeneous system-on-chip (SoC) integrates multiple types of processors on the same chip. It has great advantages in many aspects, such as processing capacity, size, weight, cost, power, and energy consumption, which result in it being widely adopted in many fields. The SoC based on region-based dynamic partial reconfigurable (DPR) FPGA plays an important role in the SoC field. However, delivering its powerful capacity to the consumer depends on the efficient Sw/Hw partitioning and scheduling technology that determines the resource volume of the DPR region, the mapping of the application to the DPR region and other processors, and the schedule of the task and its reconfiguration. This paper first proposes an exact approach based on the mixed integer linear programming (MILP) for the Sw/Hw partitioning and scheduling problem. The proposed MILP is able to solve the problem optimally; however, its scalability is poor, despite that we carefully designed its formulation and tried to make it as concise as possible. Therefore, a multi-step hybrid method that combines graph partitioning and MILP is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. A set of experiments is carried out using a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.

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Gjanci, Juliana, and Masud H. Chowdhury. "A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 11 (November 2011): 1949–59. http://dx.doi.org/10.1109/tvlsi.2010.2072997.

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Guo, Gui Fang, Lin Shui, Xiao Lan Wu, and Bing Gang Cao. "SOC Estimation for Li-Ion Battery Using SVM Based on Particle Swarm Optimization." Advanced Materials Research 1051 (October 2014): 1004–8. http://dx.doi.org/10.4028/www.scientific.net/amr.1051.1004.

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State of charge (SOC) is very important parameter for monitoring the battery charge and discharge operation and estimating the drive distance of electric vehicle. Especially, with the cycle number increasing, the precision estimation of SOC for battery management system is still not well resolved. Therefore, in this study, aim at accurate sampling of voltage, current and temperature signals based on LTC6803-3 chip, the paper proposed a support vector machine (SVM) optimized by particle swarm optimization (PSO) to improve SOC estimation accuracy. The results demonstrate that the proposed PSO-SVM model has good forecasting performance.

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Gerlein, Eduardo A., Gabriel Díaz-Guevara, Henry Carrillo, Carlos Parra, and Enrique Gonzalez. "Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM." Electronics 10, no. 12 (June 9, 2021): 1378. http://dx.doi.org/10.3390/electronics10121378.

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This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

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YANG, WOOSEUNG, and CHONG-MIN KYUNG. "CONSCEP: A CONFIGURABLE SoC EMULATION PLATFORM FOR C-BASED FAST PROTOTYPING." Journal of Circuits, Systems and Computers 14, no. 01 (February 2005): 137–57. http://dx.doi.org/10.1142/s0218126605002210.

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FPGA-based emulation, which is now widely used in the design and verification of System-on-a-Chip (SoC), is applicable only when the RTL design for the whole system is available, thus resulting in a long design turn-around time. In this paper, we present a new design flow based on a C-to-hardware IMPLEmentation tool (CIMPLE) and a CONfigurable SoC Emulation Platform (CONSCEP) that emulates the on-chip bus system prior to the RTL design of each SoC component. With the emulation environment set up in the early stage of the design process, the design and verification task of each functional block in the SoC can be performed not only faster, but also more complete as a more complete set of test vectors can be applied before the integration. CONSCEP consists of (1) configurable bus components for the given on-chip bus standard and (2) a set of transactors to link the HDL models of the pre-verified IP blocks with the C models for the behavioral blocks to be designed, or software blocks. CIMPLE translates the C model for a hardware module to a SystemC code, which can be synthesized and directly attached to the CONSCEP as an IP. CIMPLE allows global variables, nested function calls, and simple pointer access, which significantly reduces the code migration. The proposed design flow is demonstrated using a JPEG encoder/decoder system and successfully applied to a commercial MPEG4 video codec chip.

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Journal articles on the topic 'SOC [System-on-Chip Soc]'

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