Journal articles: 'SoC (System-on-Chip)'

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Sagar, G. Venkataramana, and Dr K. Srinivasa Rao. "Reconfigurable FFT System on Chip (SOC)." International Journal of Computer Applications 11, no. 5 (December 10, 2010): 35–38. http://dx.doi.org/10.5120/1575-2107.

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Jia, Hao, Shanglin Yang, Ting Zhou, Sizhu Shao, Xin Fu, Lei Zhang, and Lin Yang. "WDM-compatible multimode optical switching system-on-chip." Nanophotonics 8, no. 5 (April 27, 2019): 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.

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AbstractThe development of optical interconnect techniques greatly expands the communication bandwidth and decreases the power consumption at the same time. It provides a prospective solution for both intra-chip and inter-chip links. Herein reported is an integrated wavelength-division multiplexing (WDM)-compatible multimode optical switching system-on-chip (SoC) for large-capacity optical switching among processors. The interfaces for the input and output of the processor signals are electrical, and the on-chip data transmission and switching process are optical. It includes silicon-based microring optical modulator arrays, mode multiplexers/de-multiplexers, optical switches, microring wavelength de-multiplexers and germanium-silicon high-speed photodetectors. By introducing external multi-wavelength laser sources, the SoC achieved the function of on-chip WDM and mode-division multiplexing (MDM) hybrid-signal data transmission and switching on a standard silicon photonics platform. As a proof of concept, signals with a 25 Gbps data rate are implemented on each microring modulator of the fabricated SoC. We illustrated 25 × 3 × 2 Gbps on-chip data throughput with two-by-two multimode switching functionality through implementing three wavelength-channels and two mode-channel hybrid-multiplexed signals for each multimode transmission waveguide. The architecture of the SoC is flexible to scale, both for the number of supported processors and the data throughput. The demonstration paves the way to a large-capacity multimode optical switching SoC.

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Patil, Mr Abhijit, and Mr A. A. Shirolkar. "A Review on System-on-Chip SoC Designs for Real-Time Industrial Application." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (December 31, 2017): 1534–37. http://dx.doi.org/10.31142/ijtsrd7077.

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DOERING, ROBERT R. "System-on-Chip Integration." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 325–32. http://dx.doi.org/10.1142/s0129156402001289.

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Numerous "signal-processing products" are now driving the semiconductor market for SOC solutions enabling real-time performance, low-cost, low-power, portability, etc. A primary limit on the types of electronic (or other) functions that will be integrated into future SOCs is cost of integration, which tends to grow non-linearly with process complexity and chip area. A near-continuum of System-on/in-X solutions is emerging between traditional System-on-Chip and System-on-Board. These approaches span the tradeoff between bandwidth and cost. For the foreseeable future, digital CMOS will continue to serve as a "host platform" for integrating a wide range of mechanical, optical, biological, and, perhaps, even "quantum" technologies.

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Budiarto, Rahmat, Lelyzar Siregar, and Deris Stiawan. "Network-on-Chip Paradigm for System-on-Chip Communication." Computer Engineering and Applications Journal 6, no. 1 (March 1, 2017): 1–4. http://dx.doi.org/10.18495/comengapp.v6i1.186.

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Developments of modern technologies in electronics, such as communication, Internet, pervasive and ubiquitous computing and ambient intelligence have figured largely our life. In our day micro-electronic products inspire the ways of learning, communication and entertainment. These products such as laptop computer, mobile phones, and personal handheld sets are becoming faster, lighter in weight, smaller in size, larger in capacity, lower in power consumptions, cheaper and functionally enhanced. This trend will persistently continue. Following this trend, we could integrate more and more complex applications and even systems onto a single chip. The System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips became key driving force for the developments.

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Chitti, Sridevi, P. Chandrasekhar, and M. Asharani. "A Unique Test Bench for Various System-on-a-Chip." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (December 1, 2017): 3318. http://dx.doi.org/10.11591/ijece.v7i6.pp3318-3322.

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This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

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Dorothy, R., and Sasilatha T. "System on Chip Based RTC in Power Electronics." Bulletin of Electrical Engineering and Informatics 6, no. 4 (December 1, 2017): 358–63. http://dx.doi.org/10.11591/eei.v6i4.867.

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

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Liu, Xiang Wen, and Li Min Liu. "The IP Design for a Customized Mobile SoC." Advanced Materials Research 605-607 (December 2012): 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

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Nurmi, Jari. "International Symposium on System-on-Chip 2011." International Journal of Embedded and Real-Time Communication Systems 3, no. 4 (October 2012): 83–90. http://dx.doi.org/10.4018/jertcs.2012100105.

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International Symposium on System-on-Chip 2011 was the 13th SoC event in Tampere, Finland. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2011 contents, and in particular in its tutorial and invited talks.

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Ahmed, Mohammed Altaf, and Jaber Aloufi. "A Smart Memory Controller for System on Chip-Based Devices." Journal of Nanomaterials 2022 (May 5, 2022): 1–11. http://dx.doi.org/10.1155/2022/4944335.

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This research paper deals with a system-on-chip (SoC) architecture design where multiple processors are inbuilt with other blocks of memory and control logic developed by nanomaterials. The multiprocessing-based SoC architecture is commonly used in the latest electronic devices such as smartphones, tablets, and smart wristwatches with large memory sizes. The data handing in these highly memory-dense devices is a critical task, and it needs special attention for the smooth operation of the device. This research proposed a smart controller to exchange data between various processors and input-output devices to tackle this challenge. A proposed controller block controls the data flow between memory and different SoC components and processors. A memory access controller (MAC) is presented in this research study to manage and accelerate data transmission speed and reduce the processors’ activity for SoC-based devices. The proposed MAC will integrate into the SoC with multiprocessing units, including gaming processors, at minimum hardware overhead and low power consumption. It improves the memory accessing efficiency and reduces the processors’ activity of a system. As a result, the system’s performance and power consumption improve at an acceptable level compared with the other conventional methods. This research is aimed at enhancing the performance of any SoC-based device where multiprocessing engines are inbuilt and flexible enough to serve various SoCs.

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Nurmi, Jari. "International Symposium on System-on-Chip 2010." International Journal of Embedded and Real-Time Communication Systems 2, no. 4 (October 2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.

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International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks.

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Jung, Jun-Mo. "Low Power Test for SoC(System-On-Chip)." Journal of information and communication convergence engineering 9, no. 6 (December 31, 2011): 729–32. http://dx.doi.org/10.6109/ijice.2011.9.6.729.

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IIDA, Atsuko, Yutaka ONOZUKA, Hiroshi YAMADA, Toshihiko NAGANO, and Kazuhiko ITAYA. "High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000820–27. http://dx.doi.org/10.4071/isom-2011-wp5-paper3.

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This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

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Anil Chowdary, T., and M. Durga Prasad. "A Short Paper on Testability of a SoC." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 326. http://dx.doi.org/10.14419/ijet.v7i3.12.16051.

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The latest advances in semiconductor mix improvement accomplished assembling of expansive number of areas on a solitary chip Test organizing is an essential issue in System on-a-chip (SOC) test mechanization. Effective test masterminds minimize the general structure test application time, keep away from test asset clashes, and most outrageous power scrambling amidst test mode. For solid system on-chip, the circuit ought to be without fault since a solitary blame is likely going to make the entire chip vain. Finding the obstructions and utilization of helpful measures for same chip would diminish the running cost of the structure.. The remarkable move toward test cost emergency, where semiconductor test costs start to approach or beat in more expenses has driven test organizers to apply new reactions for the issue of testing System-On-Chip (SoC) masterminds containing different IP (Intellectual Property) centers. since it is not yet possible to apply non particular test structures to an IP focus inside a SoC, the progress of different close frameworks, and the landing of new industry measures, for instance, IEEE 1500 and IEEE 1450.6, may begin to change this condition. This paper looks rules and at several systems at present utilized by SoC tests engineers [14].

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Cirstea, Marcian, Khaled Benkrid, Andrei Dinu, Romeo Ghiriti, and Dorin Petreus. "Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends." Micromachines 15, no. 2 (February 7, 2024): 247. http://dx.doi.org/10.3390/mi15020247.

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This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.

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Charles, Subodha, and Prabhat Mishra. "A Survey of Network-on-Chip Security Attacks and Countermeasures." ACM Computing Surveys 54, no. 5 (June 2021): 1–36. http://dx.doi.org/10.1145/3450964.

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With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-Chip (SoC) architectures to cater to their communication requirements. NoC has received significant attention from both attackers and defenders. The increased usage of NoC and its distributed nature across the chip has made it a focal point of potential security attacks. Due to its prime location in the SoC coupled with connectivity with various components, NoC can be effectively utilized to implement security countermeasures to protect the SoC from potential attacks. There is a wide variety of existing literature on NoC security attacks and countermeasures. In this article, we provide a comprehensive survey of security vulnerabilities in NoC-based SoC architectures and discuss relevant countermeasures.

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Pan, Zhong Liang, and Ling Chen. "Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip." Materials Science Forum 663-665 (November 2010): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.663-665.670.

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The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

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Marrouche, Wissam, Rana Farah, and Haidar M. Harmanani. "A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules." International Journal of Computational Intelligence and Applications 17, no. 02 (June 2018): 1850010. http://dx.doi.org/10.1142/s1469026818500104.

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System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

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Cong, Vo. "Industrial robot arm controller based on programmable System-on-Chip device." FME Transactions 49, no. 4 (2021): 1025–34. http://dx.doi.org/10.5937/fme2104025c.

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Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in a wide area of applications due to their flexibility for real-time implementations, increasing the processing capability on hardware as well as the speed of processing information in real-time. The most important applications based on FPGA/SoC devices are focused on signal/image processing, Internet of Things (IoT) technology, artificial intelligence (AI) algorithms, energy systems applications, automatic control and industrial applications. This paper develops a robot arm controller based on a programmable System-OnChip (SoC) device that combines the high-performance and flexibility of a CPU and the processing power of an FPGA. The CPU consists of a dual-core ARM processor that handles algorithm calculations, motion planning and manages communication and data manipulation. FPGA is mainly used to generate signals to control servo and read the feedback signals from encoders. Data from the ARM processor is transferred to the programmable logic side via the AXI protocol. This combination delivers superior parallel-processing and computing power, real-time performance and versatile connectivity. Additionally, having the complete controller on a single chip allows the hardware design to be simpler, more reliable, and less expensive.

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Kanda, Guard, Seungyong Park, and Kwangki Ryoo. "Run-Time Hardware Trojans Detection Using On-Chip Bus for System-on-Chip Design." Journal of the Korea Institute of Information and Communication Engineering 20, no. 2 (February 29, 2016): 343–50. http://dx.doi.org/10.6109/jkiice.2016.20.2.343.

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de Melo, Francisco, Horácio C. Neto, and Hugo Plácido da Silva. "System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics." Sensors 22, no. 1 (January 4, 2022): 348. http://dx.doi.org/10.3390/s22010348.

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Biometric identification systems are a fundamental building block of modern security. However, conventional biometric methods cannot easily cope with their intrinsic security liabilities, as they can be affected by environmental factors, can be easily “fooled” by artificial replicas, among other caveats. This has lead researchers to explore other modalities, in particular based on physiological signals. Electrocardiography (ECG) has seen a growing interest, and many ECG-enabled security identification devices have been proposed in recent years, as electrocardiography signals are, in particular, a very appealing solution for today’s demanding security systems—mainly due to the intrinsic aliveness detection advantages. These Electrocardiography (ECG)-enabled devices often need to meet small size, low throughput, and power constraints (e.g., battery-powered), thus needing to be both resource and energy-efficient. However, to date little attention has been given to the computational performance, in particular targeting the deployment with edge processing in limited resource devices. As such, this work proposes an implementation of an Artificial Intelligence (AI)-enabled ECG-based identification embedded system, composed of a RISC-V based System-on-a-Chip (SoC). A Binary Convolutional Neural Network (BCNN) was implemented in our SoC’s hardware accelerator that, when compared to a software implementation of a conventional, non-binarized, Convolutional Neural Network (CNN) version of our network, achieves a 176,270× speedup, arguably outperforming all the current state-of-the-art CNN-based ECG identification methods.

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Borel, Joseph. "System on a chip (SoC) and design methodology challenges." Microelectronic Engineering 54, no. 1-2 (December 2000): 15–22. http://dx.doi.org/10.1016/s0167-9317(00)80055-6.

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N., Mohan Kumar. "ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET." Journal of Electronics and Informatics 01, no. 01 (September 29, 2019): 51–59. http://dx.doi.org/10.36548/jei.2019.1.006.

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As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

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Lin, Wei, and Wen Long Shi. "An On-Chip Clock Controller for Testing Fault in System on Chip." Applied Mechanics and Materials 347-350 (August 2013): 724–28. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.724.

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In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

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Gardel, Alfredo, Pablo Montejo, Jorge García, Ignacio Bravo, and José L. Lázaro. "Parametric Dense Stereovision Implementation on a System-on Chip (SoC)." Sensors 12, no. 2 (February 10, 2012): 1863–84. http://dx.doi.org/10.3390/s120201863.

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Gjanci, Juliana, and Masud H. Chowdhury. "A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 11 (November 2011): 1949–59. http://dx.doi.org/10.1109/tvlsi.2010.2072997.

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He, Ji Lin, Zheng Yuan, and Qing Hua He. "Clustering and Real-Time Analysis of Robot Controller Based on System on Chip." Advanced Materials Research 403-408 (November 2011): 3797–804. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.3797.

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Based on the most prosperous System on Chip (SOC) in the field of microelectronics, the open and real-time robot controller was analyzed, the application and development platform was built. By means of representative evaluation index, cohesion and coupling, the modularized design and the open architecture of robot controller were implemented. It is proved that the average distance between the same modules is short, and therefore the system is better cohesive. And the average distance between different modules is long, and therefore less coupled. Consequently, the whole system is excellent in openness. At the same time, the real-time schedule of controller tasks is analyzed from theory and experiment. It is proved that the controller based on SOC is excellent in real-time performance. The experiment showed that SOC-based robot controller is highly modularized, the parameters is clear, the architecture is easily implemented and revised, and therefore is adaptive to different controlling requirement and module building.

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Prasad Acharya, G., and M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.

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The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

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Tulpule, Bhal, Bruce Ohme, Mark Larson, Al Behbahani, John Gerety, and Al Steines. "A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000278–84. http://dx.doi.org/10.4071/hitec-tha11.

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This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.

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Tulpule, Bhal, and Alireza R. Behbahani. "System On Chip (SOC) ASIC chipset for Smart Actuators in Distributed Propulsion Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000040–45. http://dx.doi.org/10.4071/2016-hitec-40.

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Abstract This paper describes the results of the risk reduction testing task recently completed by Embedded Systems LLC under the Air Force SBIR contract {5} titled “Improved Full Authority Digital Engine Control (FADEC) System”. The objective of this program has been to develop a hierarchical, distributed architecture for future propulsion FADEC and aerospace control systems with flexible, scalable and reconfigurable Smart Nodes (SN) built with high temperature capable devices. A key part of this program is the design, development and validation of the System On Chip (SOC) chipset in high temperature (225 Deg. C) SOI (Silicon On Insulator) technology ASIC (Application Specific Integrated Circuit) devices. The SOC chipset designed by Embedded Systems LLC provides the scalability and reconfigurability that enables the Smart Node to interfaces with most sensors and actuators found in FADEC and other aircraft control systems. The analog portion of this 2-chip SOC chipset fabricated by Honeywell using their SOI process is working properly. The digital portion of the SOC chipset, currently implemented in a commercial temperature FPGA (Field Programmable Gate Array), contains important computational functions needed for reconfiguring the SOC and performing complex control functions, such as real time control of an actuator, The risk reduction task was therefore focused on verification and validation of these key functions in a real environment before converting the design into an ASIC. The recent successful demonstration of the real time actuator control capability has minimized the risks and cleared the way for the digital ASIC implementation. The complete high temperature SOC chipset is expected to be available in late 2016.

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Ritter, Philipp. "Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS." International Journal of Microwave and Wireless Technologies 13, no. 6 (February 11, 2021): 523–31. http://dx.doi.org/10.1017/s1759078721000088.

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AbstractNext-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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Zhang, Wei. "Based on SoC Technology Frequency Measurement Meter." Applied Mechanics and Materials 556-562 (May 2014): 2974–77. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2974.

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SoC is the ASICS (ApplieationSpeenIetgratdeCierulst) design methodology of the new technology, refers to the embedded system as the core technology used in PI-based, set of software and hardware in one, and the pursuit of products inclusive of the largest integrated system chip. The article in-depth exploration into the complexity of using VHDL language and system programmable logic device (CPLD) to develop "system-on-chip (SoC)" - such as adaptive frequency measurement accuracy of the basic methods to overcome the system of the previous frequency measurement accuracy is not high , measuring the accuracy of the process of change, approaching the speed of slow-type shift shortcomings.

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Tan, Junyan, and Chunhua Cai. "An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950075. http://dx.doi.org/10.1142/s0218126619500750.

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Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.

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Wang, Cong, Yi Long Liu, Peng Long Jiang, Qing Zhen Zhang, Fei Tao, and Lin Zhang. "Multiple Faults Detection with SoC Dynamic Reconfiguration System Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2642–45. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2642.

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Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

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wang, Lijun, and Xiaolu Liu. "Design and Implementation of an Automatic Test and Verification System for SoC." Journal of Physics: Conference Series 2474, no. 1 (April 1, 2023): 012053. http://dx.doi.org/10.1088/1742-6596/2474/1/012053.

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Abstract With the development of semiconductor technology in recent years, the design of SoC has become more and more complex. [1]In order to ensure the correctness of chip design and the success rate of chip taping out, the verification test of SoC becomes more and more important. This paper designs an automated test and verification system based on STM32 and analog switch matrix chips. The system has high reusability, good scalability, convenient maintenance and automated test, and can improve the efficiency of test and verification, reduce the cost and shorten the development cycle of SoC.

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HARMANANI, HAIDAR M., and HASSAN A. SALAMY. "POWER-CONSTRAINED SYSTEM-ON-A-CHIP TEST SCHEDULING USING A GENETIC ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 03 (June 2006): 331–49. http://dx.doi.org/10.1142/s0218126606003106.

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This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

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Gerlein, Eduardo A., Gabriel Díaz-Guevara, Henry Carrillo, Carlos Parra, and Enrique Gonzalez. "Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM." Electronics 10, no. 12 (June 9, 2021): 1378. http://dx.doi.org/10.3390/electronics10121378.

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This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

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Guang, Liang, Juha Plosila, Jouni Isoaho, and Hannu Tenhunen. "Hierarchical Agent Monitored Parallel On-Chip System." International Journal of Embedded and Real-Time Communication Systems 1, no. 2 (April 2010): 86–105. http://dx.doi.org/10.4018/jertcs.2010040105.

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In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated.

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Huang, LinYun, Young-Pil Lee, Yong-Seon Moon, and Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device." International Journal of Humanoid Robotics 14, no. 04 (November 16, 2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.

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Currently, as the requirements for simple implementations in the motor control technologies increase, System-on-Chip (SoC) device such as Zynq All Programmable SoC was devised to meet those requirements. Because this CPU and FPGA can be assembled into one SoC device, we can consolidate motor-control functions and additional processing tasks into a single SoC device. The control algorithms, networking and other tasks, are off-loaded to the programmable logic that can include multiple control cores and multiple control system. This SoC system with a single chip can allow the hardware design with a single chip, hence, we can implement to control the motor to be simpler, more reliable, and less expensive. In this paper, in order to implement motor controller, we apply latest All Programmable SoC technologies for humanoid robot or industrial device that is integrated with FPGA technologies and embedded processor technologies. We also propose the structure of motor controller that decentralizes the function of motor driver from previous typical motor driver into FPGA and level of embedded processor by using All Programmable SoC for humanoid robot or industrial device. We verify the possibilities of applying the novel implemented motor controller in Zynq EPP (Extensible Processing Platform) which is one kind of All Programmable SoC made by Xilinx. To do this, we perform velocity control and position control with digital PI controller on the BLDC motor.

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Choi, M., N. Park, V. Piuri, and F. Lombardi. "Evaluating the Repair of System-on-Chip (SoC) Using Connectivity." IEEE Transactions on Instrumentation and Measurement 53, no. 6 (December 2004): 1464–72. http://dx.doi.org/10.1109/tim.2004.834603.

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Springer, Tom, Elia Eiroa-Lledo, Elizabeth Stevens, and Erik Linstead. "On-Device Deep Learning Inference for System-on-Chip (SoC) Architectures." Electronics 10, no. 6 (March 15, 2021): 689. http://dx.doi.org/10.3390/electronics10060689.

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As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning algorithms remain limited. In particular, better mechanisms for real-time scheduling in the context of machine learning applications will prove to be critical as these technologies move to the edge. In order to address some of these challenges, we present a resource management framework designed to provide a dynamic on-device approach to the allocation and scheduling of limited resources in a real-time processing environment. These types of mechanisms are necessary to support the deterministic behavior required by the control components contained in the edge nodes. To validate the effectiveness of our approach, we applied rigorous schedulability analysis to a large set of randomly generated simulated task sets and then verified the most time critical applications, such as the control tasks which maintained low-latency deterministic behavior even during off-nominal conditions. The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application to perform simple object detection. The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including widely-used, industry-standard real-time operating systems.

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Adiono, Trio, Syifaul Fuada, and Rosmianto Aji Saputro. "Rapid Development of System-on-Chip (SoC) for Network-Enabled Visible Light Communications." International Journal of Recent Contributions from Engineering, Science & IT (iJES) 6, no. 1 (March 19, 2018): 107. http://dx.doi.org/10.3991/ijes.v6i1.8098.

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<p class="0abstract">Visible Light Communication (VLC) is an emerging optical communication technology with rapid development nowadays. VLC is considered as a compliment and successor of radio-frequency (RF) wireless communication. There are various typical implementations of VLC in which one of them is for exchanging data TCP/IP packets, thus the user can browse the internet as in established Wireless fidelity (Wi-Fi) technology. Briefly, we can call it by Light fidelity (Li-Fi). This paper described the design and implementation of System-on-Chip (SoC) subsystem for Li-Fi application where the implemented SoC consists of hardware (H/W) and software (S/W). In the H/W aspect, Physical Layer (PHY) is made by using UART communication with Ethernet connection to communicate with Host/Device personal-computer (PC). In the S/W aspect, Xillinux operating system (OS) is used. The H/W- as well as S/W-SoC, are realized in FPGA Zybo Zynq-7000 EPP development board. The functional test result shows (without optical channel or Zybo-to-Zybo only) that the implemented SoC is working as expected. It is able to exchange TCP/IP packets between two PCs. Moreover, Ethernet connection has bandwidth up to 83.6 Mbps and PHY layer <em>baud rate</em> has bandwidth up to 921600 bps.</p>

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Lv, Hao, Shengbing Zhang, Wei Han, Yongqiang Liu, Shuo Liu, Yaoqin Chu, and Lei Zhang. "Design and Realization of an Aviation Computer Micro System Based on SiP." Electronics 9, no. 5 (May 7, 2020): 766. http://dx.doi.org/10.3390/electronics9050766.

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In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity.

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Zitouni, Abdelkrim. "Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems." Micromachines 14, no. 9 (September 17, 2023): 1780. http://dx.doi.org/10.3390/mi14091780.

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Ezhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.

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Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

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Huang, Jincheng. "Design and Implementation of IIC Interface IP Core." Academic Journal of Science and Technology 5, no. 1 (March 6, 2023): 208–11. http://dx.doi.org/10.54097/ajst.v5i1.5634.

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With the development of SOC (System on Chip) design technology, IPcore reuse technology and on-chip bus technology, which are the basis of SOC design technology, have attracted wide attention from the society. IP core reuse technology can save repetitive work and greatly speed up chip development. At present, China's large-scale SOC design uses more foreign IP cores, which are expensive. IIC(Inter-integrated Circuit) interface is an important peripheral interface in AMBA (Advanced Microcontroller Bus Architecture) bus. It is used for communication between CPU and peripheral devices, and can be used in embedded, radio frequency communication and other fields. Therefore, designing an IIC interface IP has great use value.

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Parmar, Harikrishna, and Usha Mehta. "ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC." Journal of Low Power Electronics and Applications 9, no. 2 (June 17, 2019): 19. http://dx.doi.org/10.3390/jlpea9020019.

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Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

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HARMANANI, HAIDAR M., and HASSAN A. SALAMY. "A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS." International Journal of Computational Intelligence and Applications 06, no. 04 (December 2006): 511–30. http://dx.doi.org/10.1142/s1469026806002052.

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This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

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Su, Ching-Lung, Tse-Min Chen, and Kuo-Hsuan Wu. "A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation." VLSI Design 2013 (May 16, 2013): 1–10. http://dx.doi.org/10.1155/2013/529150.

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A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally, prototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and estimation. This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of SoC performance. The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor, on-chip bus structure, IP design, embedded OS, GUI systems, and application programs. The prototype configuration, chip post-layout simulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system performance was examined according to the proposed estimation models, the profiling result of the application programs ported on prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that the proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level 2 specifications.

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Alali, Abdelhakim, Zineb El Hariti, Mohamed Sadik, and Kaoutar Aamali. "SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study." International Journal of Emerging Technology and Advanced Engineering 12, no. 3 (March 11, 2022): 74–91. http://dx.doi.org/10.46338/ijetae0322_09.

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Abstract—As electric energy consumption becomes a more pressing concern in System-on-a-Chip (SOC) design, accurate and efficient power analysis and estimation at all levels of abstraction throughout the design phase is becoming increasingly important in order to achieve low power without an expensive redesign process. This study examines dynamic power and leaky power analysis and estimation strategies for SOC design at several design levels that have recently been proposed, with the goal of presenting a unified view of power estimation methodologies at all design levels of abstraction, focusing especially on the high level. Keywords— System on Chip; Energy estimation; SoC modelling; Accuracy; High level of abstraction.

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Journal articles on the topic 'SoC (System-on-Chip)'

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