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Relevant bibliographies by topics / Soft-edge flip-flops

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Journal articles
Dissertations / Theses
Conference papers

Academic literature on the topic 'Soft-edge flip-flops'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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Journal articles on the topic "Soft-edge flip-flops"

1

Raja, G. Abhinaya, and P. Srinivas. "Asynchronous Model of Flip-Flop’s and Latches for Low Power Clocking." International Journal of Computer and Communication Technology, April 2016, 106–10. http://dx.doi.org/10.47893/ijcct.2016.1348.

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There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Transmission gated flip-flop, are made up of two stages, one master and one slave Alternatively, pulse-triggered flip-flops reduce the two stages into one stage and are characterized by the soft edge property. The concepts discussed in the related work are related to synchronous design’s novel method for low power dissipation asynchronous methods have been improving so as to reduce the power consumption an asynchronous methods for flip-flops are being implemented.

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Dissertations / Theses on the topic "Soft-edge flip-flops"

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Ustun, Huseyin Mert. "Soft-edge flip-flop technique for aggressive voltage scaling in low-power digital designs." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-05-3623.

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Low-power digital design has been a widely researched area for the past twenty years. The growing demand for mobile computing made low power an especially important quality for such systems and encouraged researchers to find new ways of reducing power dissipation. Aggressive voltage scaling was recently published as a new paradigm for reducing power dissipation in digital circuits and the use of soft-edge flip-flops is one such technique in this category. In this thesis, we propose a soft-edge flip-flop topology that is better suited to implement the soft-edge property compared to the previously published implementations. In addition, we present the effectiveness of the soft-edge flip-flop technique by applying it to a practical VLSI design implemented with the TSMC 0.18um standard cell library. Using HSIM transistor-level SPICE simulator, we show that at least 25% power reduction is achievable in the whole circuit with a negligible area overhead.<br>text

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Conference papers on the topic "Soft-edge flip-flops"

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Duraisami, Karthik, Enrico Macii, and Massimo Poncino. "Using soft-edge flip-flops to compensate NBTI-induced delay degradation." In the 19th ACM Great Lakes symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1531542.1531585.

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2

Joshi, Vivek, David Blaauw, and Dennis Sylvester. "Soft-edge flip-flops for improved timing yield: design and optimization." In 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2007. http://dx.doi.org/10.1109/iccad.2007.4397342.

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Ghasemazar, Mohammad, Behnam Amelifard, and Massoud Pedram. "A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops." In Proceeding of the thirteenth international symposium. ACM Press, 2008. http://dx.doi.org/10.1145/1393921.1393935.

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4

Dillen, Steve J., Don A. Priore, Aaron K. Horiuchi, and Samuel D. Naffziger. "Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules." In 2012 IEEE Custom Integrated Circuits Conference - CICC 2012. IEEE, 2012. http://dx.doi.org/10.1109/cicc.2012.6330707.

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5

Manikanth, Kosanam, and S. R. Ramesh. "Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits." In 2018 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2018. http://dx.doi.org/10.1109/iccsp.2018.8524364.

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