Log in

Relevant bibliographies by topics / Software co-design / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Software co-design.

Dissertations / Theses on the topic 'Software co-design'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Software co-design.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Nilsson, Per. "Hardware / Software co-design for JPEG2000." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.

Full text

Abstract:

<p>For demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.</p><p>This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for

APA, Harvard, Vancouver, ISO, and other styles

2

Bappudi, Bhargav. "Example Modules for Hardware-software Co-design." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1470043472.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

TIWARI, ANURAG. "HARDWARE/SOFTWARE CO-DEBUGGING FOR RECONFIGURABLE COMPUTING APPLICATIONS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1011816501.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Cadenelli, Luca. "Hardware/software co-design for data-intensive genomics workloads." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/668250.

Full text

Abstract:

Since the last decade, the main components of computer systems have been evolving, diversifying, to overcome their physical limits and to minimize their energy footprint. Hardware specialization and heterogeneity have become key to design more efficient systems and tackle ever-important problems with ever-larger volumes of data. However, to fully take advantage of the new hardware, a tighter integration between hardware and software, called hardware/software co-design, is also needed. Hardware/software co-design is a time-consuming process that poses its challenges, such as code and performanc

APA, Harvard, Vancouver, ISO, and other styles

5

Subramanian, Sriram. "Software Performance Estimation Techniques in a Co-Design Environment." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1061553201.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Ramírez, Bellido Alejandro. "High performance instruction fetch using software and hardware co-design." Doctoral thesis, Universitat Politècnica de Catalunya, 2002. http://hdl.handle.net/10803/5969.

Full text

Abstract:

En los últimos años, el diseño de procesadores de altas prestaciones ha progresado a lo largo de dos corrientes de investigación: incrementar la profundidad del pipeline para permitir mayores frecuencias de reloj, y ensanchar el pipeline para permitir la ejecución paralela de un mayor numero de instrucciones. Diseñar un procesador de altas prestaciones implica balancear todos los componentes del procesador para asegurar que el rendimiento global no esta limitado por ningún componente individual. Esto quiere decir que si dotamos al procesador de una unidad de ejecución mas rápida, hay que asegu

APA, Harvard, Vancouver, ISO, and other styles

7

Zhang, Jingyao. "Hardware-Software Co-Design for Sensor Nodes in Wireless Networks." Diss., Virginia Tech, 2013. http://hdl.handle.net/10919/50972.

Full text

Abstract:

Simulators are important tools for analyzing and evaluating different design options for wireless sensor networks (sensornets) and hence, have been intensively studied in the past decades. However, existing simulators only support evaluations of protocols and software aspects of sensornet design. They cannot accurately capture the significant impacts of various hardware designs on sensornet performance. As a result, the performance/energy benefits of customized hardware designs are difficult to be evaluated in sensornet research. To fill in this technical void, in first section, we describe t

APA, Harvard, Vancouver, ISO, and other styles

8

TOMIYAMA, Hiroyuki, Hiroyuki KANBARA, Yoshiyuki ISHIMORI, Nagisa ISHIURA, and Masanari NISHIMURA. "High-Level Synthesis of Software Function Calls." Institute of Electronics, Information and Communication Engineers, 2008. http://hdl.handle.net/2237/15044.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Cavalcante, Sergio Vanderlei. "A hardware-software co-design system for embedded real-time applications." Thesis, University of Newcastle Upon Tyne, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360339.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

El, bouazzaoui Imad. "Hardware Software Co-design of an Embedded RGB-D SLAM System." Electronic Thesis or Diss., université Paris-Saclay, 2022. http://www.theses.fr/2022UPAST156.

Full text

Abstract:

Les capteurs de vision délivrant des images en couleur et l'information de profondeur ont récemment gagné en popularité. Les véhicules autonomes bénéficient de nouvelles méthodes de perception 3D grâce à ces capteurs. Nous avons étudié les différentes étapes de traitement d’un système afin d'apporter des contributions au niveau du couplage capteur-algorithme et de l'architec ture de calcul. Cette étude a commencé par une analyse expérimentale approfondie de l’impact des modalités d’acquisition des capteurs sur la précision de la localisation. Nous avons développé la méthode HOOFR-SLAM RGB-D

APA, Harvard, Vancouver, ISO, and other styles

11

O'Connor, R. Brendan. "Dataflow Analysis and Optimization of High Level Language Code for Hardware-Software Co-Design." Thesis, Virginia Tech, 1996. http://hdl.handle.net/10919/36653.

Full text

Abstract:

Recent advancements in FPGA technology have provided devices which are not only suited for digital logic prototyping, but also are capable of implementing complex computations. The use of these devices in multi-FPGA Custom Computing Machines (CCMs) has provided the potential to execute large sections of programs entirely in custom hardware which can provide a substantial speedup over execution in a general-purpose sequential processor. Unfortunately, the development tools currently available for CCMs do not allow users to easily configure multi-FPGA platforms. In order to exploit the capabilit

APA, Harvard, Vancouver, ISO, and other styles

12

Heß, Jan [Verfasser]. "Evolving practices of end user articulation in software co-design / Jan Heß." Siegen : Universitätsbibliothek der Universität Siegen, 2014. http://d-nb.info/1053119488/34.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Cornevaux-Juignet, Franck. "Hardware and software co-design toward flexible terabits per second traffic processing." Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2018. http://www.theses.fr/2018IMTA0081/document.

Full text

Abstract:

La fiabilité et la sécurité des réseaux de communication nécessitent des composants efficaces pour analyser finement le trafic de données. La diversification des services ainsi que l'augmentation des débits obligent les systèmes d'analyse à être plus performants pour gérer des débits de plusieurs centaines, voire milliers de Gigabits par seconde. Les solutions logicielles communément utilisées offrent une flexibilité et une accessibilité bienvenues pour les opérateurs du réseau mais ne suffisent plus pour répondre à ces fortes contraintes dans de nombreux cas critiques.Cette thèse étudie des s

APA, Harvard, Vancouver, ISO, and other styles

14

Liang, Cao. "Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA." ScholarWorks@UNO, 2006. http://scholarworks.uno.edu/td/416.

Full text

Abstract:

During the last years, multiple-input multiple-output (MIMO) technology has attracted great attentions in the area of wireless communications. The hardware implementation of MIMO decoders becomes a challenging task as the complexity of the MIMO system increases. This thesis presents hardware/software co-design architecture and implementations of two typical lattice decoding algorithms, including Agrell and Vardy (AV) algorithm and Viterbo and Boutros (VB) algorithm. Three levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft

APA, Harvard, Vancouver, ISO, and other styles

15

Adhipathi, Pradeep. "Model based approach to Hardware/ Software Partitioning of SOC Designs." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9986.

Full text

Abstract:

As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage o

APA, Harvard, Vancouver, ISO, and other styles

16

Vilanova, García Lluís. "Code-Centric Domain Isolation : a hardware/software co-design for efficient program isolation." Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/385746.

Full text

Abstract:

Current software systems contain a multitude of software components: from simple libraries to complex plugins and services. System security and resiliency depends on being able to isolate individual components onto separate domains. Conventional systems impose large performance and programmability overheads when isolating components. Importantly, when performance and isolation are at stake, performance often takes precedence at the expense of security and reliability. These performance and programmability overheads are rooted at the co-evolution of conventional architectures and OSs, which e

APA, Harvard, Vancouver, ISO, and other styles

17

Jin, Liwu. "Hardware and software co-design in space compaction of cores-based digital circuit." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26670.

Full text

Abstract:

Implementation of fault testing environment for embeded cores-based digital circuits is a challenging endeavor. The subject thesis aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embeded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design for testability. Specifically, applications of built-in self-test (BIST) methodology in testing embeded cores a

APA, Harvard, Vancouver, ISO, and other styles

18

Ying, Victor A. "Scaling sequential code with hardware-software co-design for fine-grain speculative parallelization." Thesis, Massachusetts Institute of Technology, 2019.

Find full text

Abstract:

This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 51-55).<br>Multicores are now ubiquitous, but most programmers still write sequential code. Speculative parallelization is an enticing approach to parallelize code while retaining the ease and simplicity of sequential programming, making paralleli

APA, Harvard, Vancouver, ISO, and other styles

19

Sander, Ingo. "System Modeling and Design Refinement in ForSyDe." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3525.

Full text

Abstract:

<p>Advances in microelectronics allow the integration of more andmore functionality on a single chip. Emerging system-on-a-chiparchitectures include a large amount of heterogeneous componentsand are of increasing complexity. Applications using thesearchitectures require many low-level details in order to yield anefficient implementation. On the other hand constanttime-to-market pressure on electronic systems demands a shortdesign process that allows to model a system at a highabstraction level, not taking low-level implementation detailsinto account. Clearly there is a significant abstraction

APA, Harvard, Vancouver, ISO, and other styles

20

Restrepo, Calle Felipe. "Co-diseño de sistemas hardware/software tolerantes a fallos inducidos por radiación." Doctoral thesis, Universidad de Alicante, 2011. http://hdl.handle.net/10045/23522.

Full text

Abstract:

En la presente tesis se propone una metodología de desarrollo de estrategias híbridas para la mitigación de fallos inducidos por radiación en los sistemas empotrados modernos. La propuesta se basa en los principios del co-diseño de sistemas y consiste en la combinación selectiva, incremental y flexible de enfoques de tolerancia a fallos basados en hardware y software. Es decir, la exploración del espacio de soluciones se fundamenta en una estrategia híbrida de grano fino. El flujo de diseño está guiado por los requisitos de la aplicación. Esta metodología se ha denominado: co-endurecimiento. D

APA, Harvard, Vancouver, ISO, and other styles

21

Dias, Maurício Acconcia. "Co-Projeto de hardware/software para correlação de imagens." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-31082011-124626/.

Full text

Abstract:

Este trabalho de pesquisa tem por objetivo o desenvolvimento de um coprojeto de hardware/software para o algoritmo de correlação de imagens visando atingir um ganho de desempenho com relação à implementação totalmente em software. O trabalho apresenta um comparativo entre um conjunto bastante amplo e significativo de configurações diferentes do soft-processor Nios II implementadas em FPGA, inclusive com a adição de novas instruções dedicadas. O desenvolvimento do co-projeto foi feito com base em uma modificação do método baseado em profiling adicionando-se um ciclo de desenvolvimento e de otim

APA, Harvard, Vancouver, ISO, and other styles

22

Alhamwi, Ali. "Co-design hardware/software of real time vision system on FPGA for obstacle detection." Thesis, Toulouse 3, 2016. http://www.theses.fr/2016TOU30342/document.

Full text

Abstract:

La détection, localisation d'obstacles et la reconstruction de carte d'occupation 2D sont des fonctions de base pour un robot navigant dans un environnement intérieure lorsque l'intervention avec les objets se fait dans un environnement encombré. Les solutions fondées sur la vision artificielle et couramment utilisées comme SLAM (simultaneous localization and mapping) ou le flux optique ont tendance a être des calculs intensifs. Ces solutions nécessitent des ressources de calcul puissantes pour répondre à faible vitesse en temps réel aux contraintes. Nous présentons une architecture matérielle

APA, Harvard, Vancouver, ISO, and other styles

23

Rudraiah, Dakshinamurthy Amruth. "A Compiler-based Framework for Automatic Extraction of Program Skeletons for Exascale Hardware/Software Co-design." Master's thesis, University of Central Florida, 2013. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5695.

Full text

Abstract:

The design of high-performance computing architectures requires performance analysis of large-scale parallel applications to derive various parameters concerning hardware design and software development. The process of performance analysis and benchmarking an application can be done in several ways with varying degrees of fidelity. One of the most cost-effective ways is to do a coarse-grained study of large-scale parallel applications through the use of program skeletons. The concept of a "program skeleton" that we discuss in this paper is an abstracted program that is derived from a larger pr

APA, Harvard, Vancouver, ISO, and other styles

24

Tuncali, Cumhur Erkan. "Implementation And Simulation Of Mc68hc11 Microcontroller Unit Using Systemc For Co-design Studies." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12609177/index.pdf.

Full text

Abstract:

In this thesis, co-design and co-verification of a microcontroller hardware and software using SystemC is studied. For this purpose, an MC68HC11 microcontroller unit, a test bench that contains input and output modules for the verification of microcontroller unit are implemented using SystemC programming language and a visual simulation program is developed using C# programming language in Microsoft .NET platform. SystemC is a C++ class library that is used for co-designing hardware and software of a system. One of the advantages of using SystemC in system design is the ability to design each

APA, Harvard, Vancouver, ISO, and other styles

25

Liu, Ming-Lun, and 劉明倫. "Efficient Hardware/Software Co-design with System Software Co-simulation via Native Translation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/43299696572914011209.

Full text

Abstract:

碩士<br>國立中正大學<br>資訊工程研究所<br>91<br>In the past years, System-on-Chip (SOC) becomes an industry in great demand. As the chip designs reach larger gate counts and time-to-market windows shrink, the cost of simulation and vari‾cation in the process of hardware/software co-design rises outstandingly. Slowdown is one of the most important factors of simulations, since the practicability of the simulation depends on the length of the simulation time. In this thesis, we introduce a native translator which is embedded in the instruction-set simulator, translating the translatable b

APA, Harvard, Vancouver, ISO, and other styles

26

Lin, Huang-Cang, and 林煌翔. "On Software/Hardware Co-Design of FFT." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/03182064851667338426.

Full text

Abstract:

碩士<br>國立交通大學<br>電機資訊學院碩士在職專班<br>93<br>In this thesis, we propose a new platform for software/hardware co-design of FFT based on the SID hardware simulation software with ARM processor simulation core. With this platform, we compare the different hardware structures and analyze their efficiency, cost and speed improvements. Experiments show that this platform provides a very good simulation environment for system designers. The area and timing optimization for the hardware FFT can be easily achieved.

APA, Harvard, Vancouver, ISO, and other styles

27

Leong, Mun-kit, and 梁文傑. "Design and Implementation of SoC Hardware-Software Co-design Platform." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/zdv3j6.

Full text

Abstract:

碩士<br>國立中山大學<br>電機工程學系研究所<br>96<br>Reconfigurable supercomputing has been used by many high-performance computer systems to accelerate the processing speed. Thus, it is the present trend to use the microprocessor to combine with reconfigurable FPGA as the embedded system platform. However, the hardware-software co-design and integration of embedded system become great challenges of the designer. Beside this, the communication between hardware and software is crucial for the system to be operated effectively. Our concept consists of the design of FPGA configuration, described in I-Link hardware

APA, Harvard, Vancouver, ISO, and other styles

28

Lee, Jen-Chieh, and 李仁傑. "Hardware/Software Co-design for Image Object Segmentation." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/67040552908716287125.

Full text

Abstract:

碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>95<br>In modern system, image processing becomes more and more important, binarziation is the most usallay approach in the image technologies.However, the tradintionally binarziaiton was easily effected by illumination changes, and the currently image processings are always based on software. Thus, how to improve an effective image technology and design the hardware to reduce timing cost will become the focus.In this paper, we purpose an improved automatic thresholding algorithm to enhance the traditionally algorithm which have the insufficient performance probl

APA, Harvard, Vancouver, ISO, and other styles

29

Lee, Yuan-Cheng, and 李沅臻. "Optimizing Memory Virtualization through Hardware/Software Co-design." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ujxkag.

Full text

Abstract:

博士<br>國立臺灣大學<br>資訊網路與多媒體研究所<br>105<br>Virtualization is a technology enabling consolidation of multiple operating systems into a single physical machine. It originated from the need to create a multi-user time-sharing operating system based on multiple single-user operating systems. This long-lasting technology has evolved constantly. In addition to the popular applications for server-side virtualization, the advances of the capabilities of embedded processors make virtualization available on various systems much wider than before. The diversity of the target systems demands new design approac

APA, Harvard, Vancouver, ISO, and other styles

30

Ramesh, Chinthala. "Hardware-Software Co-Design Accelerators for Sparse BLAS." Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4276.

Full text

Abstract:

Sparse Basic Linear Algebra Subroutines (Sparse BLAS) is an important library. Sparse BLAS includes three levels of subroutines. Level 1, Level2 and Level 3 Sparse BLAS routines. Level 1 Sparse BLAS routines do computations over sparse vector and spare/dense vector. Level 2 deals with sparse matrix and vector operations. Level 3 deals with sparse matrix and dense matrix operations. The computations of these Sparse BLAS routines on General Purpose Processors (GPPs) not only suffer from less utilization of hardware resources but also takes more compute time than the workload due to poor data loc

APA, Harvard, Vancouver, ISO, and other styles

31

Lin, Shien-Tsan, and 林顯燦. "The Design of Hardware-Software Co-design Platform for Embedded Applications." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/47368555803335823374.

Full text

Abstract:

碩士<br>國立東華大學<br>電機工程學系<br>91<br>Abstract Modern embedded systems can be utilized in widespread applications, and the type of the signal processing functions varies enormously. Therefore, the difficulties of designing an embedded system are growing substantially. In general, Many modern embedded systems are composed of several heterogeneous subsystems, including programmable digital signal processor (PDSP), memory, programmable logic device (PLD), and application specify integrated circuit (ASIC), etc., to overcome the developing problem of great complexity. heterogeneous units compose such a

APA, Harvard, Vancouver, ISO, and other styles

32

"Application hardware-software co-design for reconfigurable computing systems." THE GEORGE WASHINGTON UNIVERSITY, 2008. http://pqdtopen.proquest.com/#viewpdf?dispub=3297468.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Yang, Chian-Hsin, and 楊謙信. "HARDWARE/SOFTWARE CO-DESIGN FOR A TKIP IP CORE." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/9jet93.

Full text

Abstract:

碩士<br>國立東華大學<br>資訊工程學系<br>94<br>In this thesis, a TKIP cipher following the hardware/software co-design and co-verification principle is implemented on SOC development platform which includes ARM7TDMI microprocessor and chipset. From the analysis of computational TKIP cipher, RC4 is highly repetitive and occupy 58% in the total computation. Therefore, we implemented RC4 algorithm in hardware. The hardware of RC4 is implemented in recursive architecture. Concerning the integration of TKIP cipher, we use a wrapper to serve as the communicational interface between the proposed chip and AHB bus. T

APA, Harvard, Vancouver, ISO, and other styles

34

Choi, Jongsok. "Enabling Hardware/Software Co-design in High-level Synthesis." Thesis, 2012. http://hdl.handle.net/1807/33380.

Full text

Abstract:

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework w

APA, Harvard, Vancouver, ISO, and other styles

35

Sheng-HsinLo and 羅聖心. "Hardware and Software Co-design of IPsec Database Query." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/06182288128288495542.

Full text

Abstract:

碩士<br>國立成功大學<br>電腦與通信工程研究所<br>100<br>With the popularity of the Internet, confidentiality requirements for the Internet have become more critical. The IEFT has proposed IP security to provide services of encryption/decryption and authentication without changing current network architecture. After enabling IPsec, every transmitted or received packet must query the IPsec database. As the speed of network increases, software searching of the IPsec database may become the critical path. The purpose of this thesis is to describe and analyze a database structure as well as its querying flow for IPs

APA, Harvard, Vancouver, ISO, and other styles

36

Liu, Yu-Chi, and 劉祐齊. "The Hardware and Software Co-Design for a Software Defined Networking Switch System." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/9azskd.

Full text

Abstract:

碩士<br>國立臺灣科技大學<br>電子工程系<br>104<br>In this paper, primarily for the design is implement of hardware acceleration switch. Experimental environment is based on the Xilinx ZC706 development platform and 4-port Ethernet expansion card. ZC706 platform feature is integration of embedded processors and field programmable gate array hardware array (FPGA). It is combines the advantages of software and hardware. Through software and hardware co-design approach to achieve low-power and high-performance. In this paper, the design approach, the main use of FPGA hardware can be for a specific network environ

APA, Harvard, Vancouver, ISO, and other styles

37

"High performance instruction fetch using software and hardware co-design." Universitat Politècnica de Catalunya, 2002. http://www.tesisenxarxa.net/TDX-0723102-090122/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Hou, Zong-hui, and 侯宗輝. "Hardware/Software Co-design for Power Aware H.264 Encoder." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/80916528535046918845.

Full text

Abstract:

碩士<br>國立中央大學<br>電機工程研究所<br>99<br>In era when the multimedia communication of digit is vigorous, the action communicator is everybody''s indispensable article; even some people have many kinds of actions communicators at the same time. Some of the devices will have the functions of cameras and video cassette recorder by the way, the more top-grade action communicator can offer the better taking pictures and making video recording function, though ordinary action device can be offered, the quality of taking a picture and making video recording would not be very good. This thesis wants to realize

APA, Harvard, Vancouver, ISO, and other styles

39

Chang, Cheng-Ji, and 張昌吉. "Hardware/Software Co-design Platform for Embedded Signal Compression System." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/60414372632440429747.

Full text

Abstract:

碩士<br>國立雲林科技大學<br>電子與資訊工程研究所碩士班<br>90<br>In this thesis, we propose a DSP + FPGAs embedded system platform with application domains in speech, audio and image compression. The proposed platform contains a TI TMS320C6201 DSP processor, two XilinxTM XCV300 FPGAs, memory modules, PCI interface and data access peripherals. This platform can be used as an independent rapid prototyping system or served as an attached system to a Host PC via the PCI bus interface. Based on this platform, the system designers can rapid prototype a target application for system integration verification and shortening d

APA, Harvard, Vancouver, ISO, and other styles

40

Hsiao, Chin-Mu, and 蕭金木. "Hardware/Software Co-design of AES Algorithms Using Custom Instructions." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/35389142457501490628.

Full text

Abstract:

碩士<br>輔仁大學<br>電子工程學系<br>96<br>The Advanced Encryption Standard (AES) is the new encryption standard appointed by NIST. To shorten the encryption/decryption time of plenty of data, it is necessary to adopt the algorithm of hardware implementation; however, it is possible to meet the requirement for low cost by completely using software only. How to reach a balance between the cost and efficiency of software and hardware implementation is a question worth of being discussed. In this paper, we implemented the AES encryption algorithm with hardware in combination with part of software using the cu

APA, Harvard, Vancouver, ISO, and other styles

41

Hsu, Wei-hsiang, and 徐偉翔. "Image tracking with software and hardware co-design on SOPC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/98935567430630976983.

Full text

Abstract:

碩士<br>國立雲林科技大學<br>電子與光電工程研究所碩士班<br>100<br>This paper presents an embedded SOPC system for tracking mobile objects on DE2-70 from Altera and Terasic. In SOPC Builder in Quartus II, two NIOS cores were. One NIOS core is to do image processing and shows the resulting image on an LCD screen and the other core transmits the image data to an Android smartphone through Bluetooth. The entire system was constructed on the FPGA chip on DE2-70. Using a hardware circuit and an external memory, we can achieve automatic detection of target and wireless image transmission. Non-synchronous computations were d

APA, Harvard, Vancouver, ISO, and other styles

42

Su, Sheng-Shuan, and 蘇聖軒. "Research on Video Coding and Its Hardware/Software Co-Design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/68350382222926425882.

Full text

Abstract:

碩士<br>國立中央大學<br>電機工程學系<br>102<br>As the technology progressing, the requirement of video quality and resolution for human being is getting higher and higher, from previous HD or Full HD to nowadays 4K, 8k, or even higher. In the corresponding applications of video, such as: video streaming, surveillance system, video storage, and image analysis. For preserving the relative video quality and compression rate, the Joint Video Team (JVT) established by VCEG and MPEG announced the H.264/AVC video coding standard in 2003. It brings high resolution video into our daily life. Furthermore, these two b

APA, Harvard, Vancouver, ISO, and other styles

43

Lin, Yin-Hsin, and 林殷旭. "Hardware-Software Co-design of an Automatic White Balance Algorithm." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/b4636z.

Full text

Abstract:

碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>94<br>As electronic techniques is continuous improved rapidly cameras or video camcorders used for image retrieval technology and development become digitalized. The color of the photographs would look very different due to differences in light projection illumination when we take a picture. Human eyes are able to automatically adjust the color when the illuminations of the light source vary. However, the most frequently used image sensor, charge coupled device, CCD device can not correct the color as human eyes. This paper presents a hardware-software co-design m

APA, Harvard, Vancouver, ISO, and other styles

44

Kent, Kenneth Blair. "The co-design of virtual machines using reconfigurable hardware." Thesis, 2003. http://hdl.handle.net/1828/7938.

Full text

Abstract:

The prominence of the internet and networked computing has driven research efforts into providing support for heterogeneous computing platforms. This has been exemplified by the emergence of virtual machines, such as the Java virtual machine. Unfortunately, most virtual computing platforms come with a performance penalty. This dissertation investigates a new approach for providing virtual computing platforms through the use of reconfigurable computing devices and hardware/software co-design. Traditionally, when designing a hardware/software solution, instance specific methods are used t

APA, Harvard, Vancouver, ISO, and other styles

45

Lee, Yi-Feng, and 李宜峰. "Hardware/Software Co-design for Multi-Object Tracking in Surveillance System." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/71260325645612626394.

Full text

Abstract:

碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>93<br>The increasing demand for security by society leads to a growing need for surveillance activities in many environments. In this thesis, we propose an intelligent surveillance system for multiple objects tracking. The surveillance system mainly consists of object detection and tracking. In object detection, the quality of detection result is easily interfered by noise. We use spatial information to eliminate noise effect. The object tracking utilizes motion vector prediction to reduce search region. Based on object moving direction, distance and area, our a

APA, Harvard, Vancouver, ISO, and other styles

46

Liu, Tai-Ying, and 劉岱穎. "Hardware Software Co-Design for Deep Packet Inspection with String Matching." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/14238979166290547433.

Full text

Abstract:

碩士<br>國立交通大學<br>網路工程研究所<br>96<br>String matching is the bottleneck of anti-virus and deep packet inspection. It is a promising trend to offload the inspection to a specific hardware engine for high-speed applications that demand the throughput up to multi-giga bit rate. Most papers emphasized that raising the throughput of hardware engine but not whole system. This work integrates string matching hardware with ClamAV, and discusses why it can’t stay high throughput when integrating hardware with software. This work also discovers that the data moving time is the bottleneck. The experiment is i

APA, Harvard, Vancouver, ISO, and other styles

47

Su, Yong-Long, and 蘇永隆. "Content-Based Music Retrieval Systems Based on Hardware/Software Co-Design." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/65574244975932155440.

Full text

Abstract:

碩士<br>國立臺灣師範大學<br>資訊工程研究所<br>96<br>A FPGA (novel field programmable gate array) implementation of content-based music retrieval system is presented in this thesis. The system adopts a novel hardware architecture for approximate string matching. The architecture is based on a simple shift-and-or algorithm. It has the advantages of low area cost and high throughput. The content-based music retrieval system based on the proposed architecture is implemented on a system-on-programmable-chip (SOPC) platform with a softcore NIOS II CPU for physical performance measurement. It can accept query request

APA, Harvard, Vancouver, ISO, and other styles

48

Chieh, Lin Sheng, and 林盛傑. "The Hardware and Software co-design of Cloud Connected Embedded Device." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/n55d3c.

Full text

Abstract:

碩士<br>逢甲大學<br>資電碩士在職專班<br>102<br>The development of the embedded system usually goes with limited memory to integrate the design of software and hardware. This study provides a methodology for Internet of Things(IOT) gateway design with a general purpose MCU and Internet module. The device can work without complicated real time OS and can be very low material cost on hardware. This study not only provides the selections for hardware module but also provides a portable software framework to help developers design or improve their system to become a cloud connected embedded device. User can moni

APA, Harvard, Vancouver, ISO, and other styles

49

Guo, Yi-Tai, and 郭以太. "Hardware and Software Co-design of the Moving Object Tracking System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/h9emve.

Full text

Abstract:

碩士<br>國立雲林科技大學<br>電機工程系<br>102<br>With the development of the field of computer vision, many researches for moving object tracking systems have been proposed, but most of the methods was developed for high-precision recognition. These systems typically involve highly complex algorithms and are dependent on high-performance processors to meet the requirement. The methods achieve excellent results but also increase the cost of the product, and might not meet the requirement of real-time applications. This thesis implements a moving object tracking system on a mobile camera by using hardware/soft

APA, Harvard, Vancouver, ISO, and other styles

50

Chang, Po-Hao, and 張博皓. "Hardware Software Co-design and Implementationof Wavelet-based Video Compression System." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/89707902571777803281.

Full text

Abstract:

碩士<br>國立成功大學<br>電機工程學系<br>89<br>In this thesis, we propose a wavelet based video coding system and its corresponding implementation. This video coding system is capable of compress a moving picture sequence in more efficient way than the traditional hybrid DCT compression algorithm. Its base architecture is in much the same way as the MPEG system, with DCT/IDCT replaced with DWT/IDWT. Because the special property of DWT coefficients, compression stage is also replaced for VLC to a tree based coding algorithm, which compress DWT coefficients more efficiently than VLC. This proposed video coding

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!