Relevant bibliographies by topics / SOI Device

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'SOI Device'

Author: Grafiati
Published: 4 June 2021
Last updated: 9 February 2022

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Journal articles on the topic "SOI Device"

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Maleville, Christophe, Eric Neyret, Daniel Delprat, and Ludovic Ecarnot. "High Temperature RTP Application in SOI Manufacturing." Materials Science Forum 573-574 (March 2008): 61–74. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.61.

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Significant performance enhancements are offered by silicon on insulator (SOI) or strained silicon, SOI being adopted for advanced devices in sustaining Moore’s law. Sub-45 nm device options are including fully depleted (FD) devices, that are stressing even more specifications for thickness uniformity. Nano-uniformity, considering thickness variation contributions from device level to wafer scale, has been introduced in substrate optimization and latest Unibond products are verifying FD requirements. Rapid Thermal Processing (RTP) based surface smoothing has been introduced in Unibond processing to combine thickness control and product quality requirements.
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Samuel, T. S. Arun, and M. Karthigai Pandian. "Comparative Performance Analysis of Multi Gate Tunnel Field Effect Transistors." Journal of Nano Research 41 (May 2016): 1–8. http://dx.doi.org/10.4028/www.scientific.net/jnanor.41.1.

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In this paper, analytical modelling and performance analysis of novel device structures such as single gate SOI Tunnel Field Effect transistor (SG SOI TFET), Dual-Material Gate TFET (DMG TFET) and Dual Material Double Gate TFET (DMDG TFET) are proposed. The performance of the three devices is studied and compared in terms of surface potential, electric field and drain current. The DMDG TFET shows better performance in suppressing leakage current and enhancing ION current than the SG SOI TFET and DMG TFET. The analytical models of the devices are found to be in good agreement with the results obtained using two-dimensional TCAD device simulator.
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Uryu, Yuko, and Tanemasa Asano. "SOI-MOSFET/Diode Composite Photodetection Device." Japanese Journal of Applied Physics 40, Part 1, No. 4B (April 30, 2001): 2897–902. http://dx.doi.org/10.1143/jjap.40.2897.

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Xiong, Yan, and Yu Shu Lai. "Thermal Conductivity of SOI LDMOS Device." Advanced Materials Research 571 (September 2012): 8–12. http://dx.doi.org/10.4028/www.scientific.net/amr.571.8.

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In this paper, the thermal conductivity of lateral double diffused metal oxide semiconductor (LDMOS) was studied. In order to optimize their properties, the LDMOS device based on the lower surface of field (RESURF) theory join the second field plate technology. Power device self-heating effect will affect the carrier mobility, making its negative resistance effect in IV characteristic curve under the high-power condition. As the thermal conductivity of SiO2 is low, the self-heating effect of SOI device is more obvious. The simulation using Silvaco -TCAD software for different buried oxide (BOX) with different SOI layer thickness accordingly show that the thicker SOI layer and the thinner buried oxide layer, the smaller the self-heating effect.
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Wakita, Shigeyuki, and Yasuhisa Omura. "Device Models of SOI Insulated-Gate p-n Junction Devices." Journal of The Electrochemical Society 150, no. 12 (2003): G816. http://dx.doi.org/10.1149/1.1624844.

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Kumar, K. Senthil, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, and Subir Kumar Sarkar. "Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance." Applied Mechanics and Materials 110-116 (October 2011): 5150–54. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5150.

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With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.
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Ashaf, Arjimand, Manisha Tyagi, and Prashant Mani. "To study high performance analysis of surround gate SOI MOSFET." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 191. http://dx.doi.org/10.14419/ijet.v7i2.8.10405.

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In this paper, we are presenting a rigorous study about SOI MOSFET devices development. The development of SOI devices based on gate structure from single gate to surround gate is presented in this paper. We compared the various electrical characteristics between Single gate, double gate, and bulk and also discussed the device modeling based on surround gate structure.
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Li, B., K. Zhao, J. Wu, X. Zhao, J. Su, J. Gao, C. Gao, and J. Luo. "Electromagnetic susceptibility characterization of double SOI device." Microelectronics Reliability 64 (September 2016): 168–71. http://dx.doi.org/10.1016/j.microrel.2016.07.121.

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Colinge, J. P. "An SOI voltage-controlled bipolar-MOS device." IEEE Transactions on Electron Devices 34, no. 4 (April 1987): 845–49. http://dx.doi.org/10.1109/t-ed.1987.23005.

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Rios, R., R. Amantea, R. K. Smeltzer, and A. Rothwarf. "Requirements for accurate MOS-SOI device simulations." IEEE Transactions on Electron Devices 39, no. 3 (March 1992): 581–86. http://dx.doi.org/10.1109/16.123481.

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Dissertations / Theses on the topic "SOI Device"

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Lim, T. C. "Device and circuit simulation of nanoscale double gate SOI transistors." Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.484976.

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This thesis addresses the design and application of a state-of-the-art nano-scaled Undoped-Thinned Body (UTE) Double Gate Silicon-On-Insulator (DGSOI) for digital and RF applications using TCAD. A novel structure ofooSOI, which focuses on the source/drain extension regions, has been proposed. The research covers the characterizations, optimisations and application of this nano-scaled ooSOI incorporating gate underlap concept by way ofanalytical investigations, numerical device simulations and circuit simulations. MixedMode simulator; a sub-module from ATLAS Silvaco' allows the effect of significant external parasitics in a nano-scaled device to be investigated in the circuit environment. Therefore, the impact of the source/drain engineering ofa nano-scaled ooSOI has been directly analysed in various circuit applications, such as 2-stage CMOS inverter for digital application and Operational Transconductance Amplifier (OTA) for RF application. . . For the digital application, the sensitivity and trend of the gate delay TD and lOljlOFF current ratio of the ooSOI have been established and have shown to be able to meet the IlRS roadrnap for 65nm node and below for three types oflogic applications (lIP, LOP, LSTP). Whilst the optimal performance ofooSOI in a digital circuit requires spacer length s - O.5Le;, ensuring off-eurrent meets the IlRS roadrnap whilst achievrng minimum TD, the optimised s for RF performance of a single device requires longer spacer s - La to maximise.fr andfAro''' When a RF circuit is considered employing several devices, such as OTA, an even longer s exceeding gate length has been shown to be beneficial in maximising Early voltage (Vw, hence intrinsic gain (AI-1_0T.J without comprornisingfT_OTA' The sensitivity of both dc and RF design to the lateral source/drain doping profile has been assessed and an optimal profJ.1e has been identified by its gradient at the gate edge. Value in the range of 3 - 5 nrnIdecade represents an optimised d of a typical ooSOI for both digital and RF performance. The effect ofparasitic resistances to RF performance has been reviewed. More rigorous expressions for.fr and fAro'' have been proposed to demonstrate that the effect of the contact resistance at the drain is more significant onfAro'' than the contact resistance at the source. The overall research has yield valuable insights into the potential performance of ooSOI in circuit applications.
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Wei, Andy 1972. "Device design and process technology for sub-100 nm SOI MOSFET's." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/51569.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2001.
Includes bibliographical references (leaves 203-207).
Silicon-on-insulator (SOI) MOSFET's are an attractive alternative to bulk-silicon MOSFET's in the sub-100 nm gate length regime due to improved performance and/or scalability. The SOI layer thickness in SOI MOSFET's can be sized so that the channel is either partially- or fully-depleted-of majority carriers. Partially-depleted (PD) SOI MOSFET's are easier to manufacture than fully-depleted (FD) SOI MOSFET's because a thicker SOI film can be used. However, PDSOI MOSFET's are difficult to design due to floating-body effects. FD-SOI MOSFET's are easier to design and are more scalable than PD-SOI MOSFET's. However, in the sub- 100 nm gate length regime, fully-depleted SOI MOSFET's are difficult to manufacture because a bottom gate is required for electrostatic integrity. In this thesis, floating-body effects in PD-SOI MOSFET's and process technology for fabrication of double-gate FD-SOI MOSFET's will be investigated. Floating-body effects in PD-SOI MOSFET's result from floating-body voltage modulation by AC and DC changes in source, drain, gate, and substrate terminal voltages. This modulation of the floating-body voltage results in modulation of the drain current. AC modulation of the floating-body voltage occurs through capacitive coupling to rapidly switching terminal voltages. DC modulation of the floating-body voltage occurs through diode currents and impact ionization. Because the time constants of these processes are very different, the DC and AC I-V behavior of floating-body PD-SOI MOSFET's are very different from each other, as well as very different from body-contacted SOI MOSFET's or bulk MOSFET's with the body tied to a fixed voltage. Floating-body effects on I-V behavior, how they are important in CMOS digital operation, and how they are affected by device design are described and modeled. Another consequence of floating-body behavior is history dependence in I-V behavior. Rapid switching of terminal voltages induce nearly-negligible changes in body majority carrier content since body majority carriers are trapped by body-source/drain junction diodes. However, the change in body majority carrier content can become significant over many switching cycles, eventually reaching a "switching-steady-state" value if kept switching (different value for different switching patterns), and can return to the initial value if the terminal voltages are returned to the initial settings and enough time is allowed to reach equilibrium. This "hysteretic" variation of the body majority hole content is problematic because device I-V behavior changes with changing body majority carrier content. Device design to minimize hysteretic behavior will be presented. Once the hysteretic I-V behavior of floating-body PD-SOI MOSFET's has been understood, floating-body PD-SOI CMOS technology can be optimized to maximize drive current while minimizing hysteresis. This optimized PD-SOI technology can then be compared to bulk CMOS technology. This was done using the 2-D numerical simulator MEDICI in a optimization framework based on the International Technology Roadmap for Semiconductors for the 100 nm-, 70 nm-, and 50 nm-technology nodes. And finally, double-gate fully-depleted SOI MOSFET's technology was explored. A method to fabricate bury a bottom-gate under a FD-SOI MOSFET was developed based on a flip-bond- transfer technique. This technique is based on chemical-mechanical-polish and wafer fusion bonding. Double-gate SOI MOSFET's were fabricated based with this technique, and a self-alignment scheme for alignment of the bottom-gate which to the top-gate was explored.
by Andy Wei.
Ph.D.
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Haralson, Erik. "Device design and process integration for SiGeC and Si/SOI bipolar transistors." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3836.

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SiGe is a significant enabling technology for therealization of integrated circuits used in high performanceoptical networks and radio frequency applications. In order tocontinue to fulfill the demands for these applications, newmaterials and device structures are needed. This thesis focuseson new materials and their integration into heterojunctionbipolar transistor (HBT) structures as well as using devicesimulations to optimize and better understand the deviceoperation. Specifically, a SiGeC HBT platform was designed,fabricated, and electrically characterized. The platformfeatures a non-selectively grown epitaxial SiGeC base,in situdoped polysilicon emitter, nickel silicide,LOCOS isolation, and a minimum emitter width of 0.4 μm.Alternately, a selective epitaxy growth in an oxide window wasused to form the collector and isolation regions. Thetransistors exhibited cutoff frequency (fT) and maximum frequency of oscillation (fMAX) of 40-80 GHz and 15-45 GHz, respectively.Lateral design rules allowed the investigation of behavior suchas transient enhanced diffusion, leakage current, and theinfluence of parasitics such as base resistance and CBC. The formation of nickel silicide on polysiliconSiGe and SiGeC films was also investigated. The formation ofthe low resistivity monosilicide phase was shown to occur athigher temperatures on SiGeC than on SiGe. The stability of themonosilicide was also shown to improve for SiGeC. Nickelsilicide was then integrated into a SiGeC HBT featuring aselectively grown collector. A novel, fully silicided extrinsicbase contact was demonstrated along with the simultaneousformation of NiSi on thein situdoped polysilicon emitter.

High-resolution x-ray diffraction (HRXRD) was used toinvestigate the growth and stability of SiGeC base layers forHBT integration. HRXRD proved to be an effective, fast,non-destructive tool for monitoring carbon out-diffusion due tothe dopant activation anneal for different temperatures as wellas for inline process monitoring of epitaxial growth of SiGeClayers. The stability of the SiGe layer with 0.2-0.4 at% carbonwhen subjected to dopant activation anneals ranging from1020-1100°C was analyzed by reciprocal lattice mapping.It was found that as the substitutional carbon increases theformation of boron clusters due to diffusion is suppressed, buta higher density of carbon clusters is formed.

Device simulations were performed to optimize the DC and HFperformance of an advanced SiGeC HBT structure with low baseresistance and small dimension emitter widths. The selectivelyimplanted collector (SIC) was studied using a design ofexperiments (DOE) method. For small dimensions the lateralimplantation straggle has a significant influence on the SICprofile (width). A significant influence of the SIC width onthe DC gain was observed. The optimized structure showedbalanced fT/fMAXvalues of 200+ GHz. Finally, SOI BJT transistorswith deep trench isolation were fabricated in a 0.25μmBiCMOS process and self-heating effects were characterized andcompared to transistors on bulk silicon featuring deep trenchand shallow trench isolation. Device simulations based on SEMcross-sections and SIMS data were performed and the resultscompared to the fabricated transistors.

Key words:Silicon-Germanium(SiGe), SiGeC,heterojunction bipolar transistor(HBT), nickel silicide,selectively implanted collector(SIC), device simulation, SiGeClayer stability, high resolution x-ray diffraction(HRXRD),silicon-on-insulator(SOI), self-heating.

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Keyvaninia, Shahram [Verfasser], Martin [Akademischer Betreuer] Schell, Martin [Gutachter] Schell, and Jonathan [Gutachter] Klamkin. "Novel technology and device approaches for InP-on-SOI and InP photonic integrated circuits / Shahram Keyvaninia ; Gutachter: Martin Schell, Jonathan Klamkin ; Betreuer: Martin Schell." Berlin : Technische Universität Berlin, 2021. http://d-nb.info/1231908769/34.

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BREED, ANIKET A. "DESIGN, SIMULATION AND ANALYSIS OF THE SWITCHING AND RF PERFORMANCE OF MULTI-GATE SILICON-ON-INSULATOR MOSFET DEVICE STRUCTURES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1121014432.

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Ferreira, Luiz Fernando. "Double-gate nanotransistors in silicon-on-insulator : simulation of sub-20 nm FinFETs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/65631.

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Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs.
This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.
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Park, So Jeong. "Propriétés électriques et modélisation des dispositifs MOS avanvés : dispositif FD-SOI, transistors sans jonctions (JLT) et transistor à couche mince à semi-conducteur d'oxyde amorphe." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00954637.

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Selon la feuille de route des industriels de la microélectronique (ITRS), la dimension critiqueminimum des MOSFET en 2026 ne devrait être que de 6 nm [1]. La miniaturisation du CMOS reposeessentiellement sur deux approches, à savoir la réduction des dimensions géométriques physiques etdes dimensions équivalentes. La réduction géométrique des dimensions conduit à la diminution desdimensions critiques selon la " loi " de Moore, qui définit les tendances de l'industrie dessemiconducteurs. Comme la taille des dispositifs est réduite de façon importante, davantage d'effortssont consentis pour maintenir les performances des composants en dépit des effets de canaux courts,des fluctuations induites par le nombre de dopants.... [2-4]. D'autre part, la réduction des dimensionséquivalentes devient de plus en plus importante de nos jours et de nouvelles solutions pour laminiaturisation reposant sur la conception et les procédés technologiques sont nécessaires. Pour cela,des solutions nouvelles sont nécessaires, en termes de matériaux, d'architectures de composants et detechnologies, afin d'atteindre les critères requis pour la faible consommation et les nouvellesfonctionnalités pour les composants futurs ("More than Moore" et "Beyond CMOS"). A titred'exemple, les transistors à film mince (TFT) sont des dispositifs prometteurs pour les circuitsélectroniques flexibles et transparents.
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Jin, M. "SOI technology for MOS devices and mixed signal applications." Thesis, Queen's University Belfast, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.437426.

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Reid, Richard A. "Triaxial permeability device." Thesis, Georgia Institute of Technology, 1987. http://hdl.handle.net/1853/20036.

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Mogniotte, Jean-François. "Conception d'un circuit intégré en SiC appliqué aux convertisseur de moyenne puissance." Thesis, Lyon, INSA, 2014. http://www.theses.fr/2014ISAL0004/document.

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L’émergence d’interrupteurs de puissance en SiC permet d’envisager des convertisseurs de puissance capables de fonctionner au sein des environnements sévères tels que la haute tension (> 10 kV ) et la haute température (> 300 °C). Aucune solution de commande spécifique à ces environnements n’existe pour le moment. Le développement de fonctions élémentaires en SiC (comparateur, oscillateur) est une étape préliminaire à la réalisation d’un premier démonstrateur. Plusieurs laboratoires ont développé des fonctions basées sur des transistors bipolaires, MOSFETs ou JFETs. Cependant les recherches ont principalement portées sur la conception de fonctions logiques et non sur l’intégration de drivers de puissance. Le laboratoire AMPERE (INSA de Lyon) et le Centre National de Microélectronique de Barcelone (Espagne) ont conçu un MESFET latéral double grille en SiC. Ce composant élémentaire sera à la base des différentes fonctions intégrées envisagées. L’objectif de ces recherches est la réalisation d’un convertisseur élévateur de tension "boost" monolithique et de sa commande en SiC. La démarche scientifique a consisté à définir dans un premier temps un modèle de simulation SPICE du MESFET SiC à partir de caractérisations électriques statique et dynamique. En se basant sur ce modèle, des circuits analogiques tels que des amplificateurs, oscillateurs, paires différentielles, trigger de Schmitt ont été conçus pour élaborer le circuit de commande (driver). La conception de ces fonctions s’avère complexe puisqu’il n’existe pas de MESFETs de type P et une polarisation négative de -15 V est nécessaire au blocage des MESFETs SiC. Une structure constituée d’un pont redresseur, d’un boost régulé avec sa commande basée sur ces différentes fonctions a été réalisée et simulée sous SPICE. L’ensemble de cette structure a été fabriqué au CNM de Barcelone sur un même substrat SiC semi-isolant. L’intégration des éléments passifs n’a pas été envisagée de façon monolithique (mais pourrait être considérée pour les inductances et capacités dans la mesure où les valeurs des composants intégrés sont compatibles avec les processus de réalisation). Le convertisseur a été dimensionné pour délivrer une de puissance de 2.2 W pour une surface de 0.27 cm2, soit 8.14 W/cm2. Les caractérisations électriques des différents composants latéraux (résistances, diodes, transistors) valident la conception, le dimensionnement et le procédé de fabrication de ces structures élémentaires, mais aussi de la majorité des fonctions analogiques. Les résultats obtenus permettent d’envisager la réalisation d’un driver monolithique de composants Grand Gap. La perspective des travaux porte désormais sur la réalisation complète du démonstrateur et sur l’étude de son comportement en environnement sévère notamment en haute température (> 300 °C). Des analyses des mécanismes de dégradation et de fiabilité des convertisseurs intégrés devront alors être envisagées
The new SiC power switches is able to consider power converters, which could operate in harsh environments as in High Voltage (> 10kV) and High Temperature (> 300 °C). Currently, they are no specific solutions for controlling these devices in harsh environments. The development of elementary functions in SiC is a preliminary step toward the realization of a first demonstrator for these fields of applications. AMPERE laboratory (France) and the National Center of Microelectronic of Barcelona (Spain) have elaborated an elementary electrical compound, which is a lateral dual gate MESFET in Silicon Carbide (SiC). The purpose of this research is to conceive a monolithic power converter and its driver in SiC. The scientific approach has consisted of defining in a first time a SPICE model of the elementary MESFET from electric characterizations (fitting). Analog functions as : comparator, ring oscillator, Schmitt’s trigger . . . have been designed thanks to this SPICE’s model. A device based on a bridge rectifier, a regulated "boost" and its driver has been established and simulated with the SPICE Simulator. The converter has been sized for supplying 2.2 W for an area of 0.27 cm2. This device has been fabricated at CNM of Barcelona on semi-insulating SiC substrate. The electrical characterizations of the lateral compounds (resistors, diodes, MESFETs) checked the design, the "sizing" and the manufacturing process of these elementary devices and analog functions. The experimental results is able to considerer a monolithic driver in Wide Band Gap. The prospects of this research is now to realize a fully integrated power converter in SiC and study its behavior in harsh environments (especially in high temperature > 300 °C). Analysis of degradation mechanisms and reliability of the power converters would be so considerer in the future
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Books on the topic "SOI Device"

1

Patel, Monica. Novel simox/soi device structure with body contact for reduction of floating body effects. Ottawa: National Library of Canada, 1990.

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2

Kiihamäki, Jyrki. Fabrication of SOI micromechanical devices. [Espoo, Finland]: VTT Technical Research Centre of Finland, 2005.

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Kuo, James B., and Shih-Chia Lin. Low-Voltage SOI CMOS VLSI Devices and Circuits. New York, USA: John Wiley & Sons, Inc., 2002. http://dx.doi.org/10.1002/0471221562.

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Colinge, J. P. Physical and Technical Problems of SOI Structures and Devices. Dordrecht: Springer Netherlands, 1995.

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Colinge, J. P., V. S. Lysenko, and A. N. Nazarov, eds. Physical and Technical Problems of SOI Structures and Devices. Dordrecht: Springer Netherlands, 1995. http://dx.doi.org/10.1007/978-94-011-0109-7.

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Olsen, Peter Bo. Flue gas cleaning device reduces HC1 and SO2 emissions. Houston: MacDonlad Communications, 1993.

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NATO Advanced Research Workshop on Progress in SOI Structures and Devices Operating at Extreme Conditions (2000 Kiev, Ukraine). Progress in SOI structures and devices operating at extreme conditions. Dordrecht: Kluwer Academic, 2002.

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Balestra, F., A. Nazarov, and V. S. Lysenko, eds. Progress in SOI Structures and Devices Operating at Extreme Conditions. Dordrecht: Springer Netherlands, 2002. http://dx.doi.org/10.1007/978-94-010-0339-1.

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Wei na liu kong xin pian shi yan shi. Beijing Shi: Ke xue chu ban she, 2013.

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Wise, Michael. Deviance: Sociological explanations. Dubuque, Iowa: Kendall/Hunt Pub. Co., 2001.

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Book chapters on the topic "SOI Device"

1

Balestra, Francis, and Gérard Ghibaudo. "SOI MOSFETs." In Device and Circuit Cryogenic Operation for Low Temperature Electronics, 37–67. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3318-1_3.

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Ioannou, Dimitris E. "Reliability of Short Channel Silicon and SOI VLSI Devices and Circuits." In Semiconductor Device Reliability, 507–16. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-2482-6_30.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "Modeling of Classical SOI MESFET." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 43–58. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_3.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "Design and Modeling of Triple-Material Gate SOI MESFET." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 59–71. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_4.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "Analytical Investigation of Subthreshold Performance of SOI MESFET Devices." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 93–111. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_6.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "Three-Dimensional Analytical Model of the Non-Classical Three-Gate SOI MESFET." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 73–92. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_5.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "Future Works on Silicon-on-Insulator Metal–Semiconductor Field Effect Transistors (SOI MESFETs)." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 113–15. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_7.

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Ahmed, Shaikh S., and Dragica Vasileska. "Modeling of Narrow-Width SOI Devices: The Role of Quantum Mechanical Narrow Channel Effects on Device Performance." In Large-Scale Scientific Computing, 105–11. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-24588-9_10.

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Amiri, Iraj Sadegh, Hossein Mohammadi, and Mahdiar Hosseinghadiry. "General Overview of the Basic Structure and Operation of a Typical Silicon on Insulator Metal–Semiconductor Field Effect Transistor (SOI-MESFET)." In Device Physics, Modeling, Technology, and Analysis for Silicon MESFET, 11–41. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-04513-5_2.

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Mehta, Hema, and Harsupreet Kaur. "Junctionless Gaussian Doped Negative Capacitance SOI Transistor: Investigation of Device Performance for Analog and Digital Applications." In Micro-Electronics and Telecommunication Engineering, 245–53. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2329-8_25.

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Conference papers on the topic "SOI Device"

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Harris, H. R., H. Adhikari, C. E. Smith, G. Smith, J. W. Yang, P. Majhi, and R. Jammy. "Adjusting to 3D devices in a 2D device world." In 2008 IEEE International SOI Conference. IEEE, 2008. http://dx.doi.org/10.1109/soi.2008.4656321.

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Pelella, Mario, and Thierry Poiroux. "Device Physics and Modeling." In 2006 IEEE international SOI. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284446.

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Doris, Bruce, and Samuel Fung. "Session #2 Planar SOI device." In 2008 IEEE International SOI Conference. IEEE, 2008. http://dx.doi.org/10.1109/soi.2008.4656271.

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"Device Physics and Modeling." In 2006 IEEE international SOI Conferencee Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284447.

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Jurczak, Malgorzata, and Wade Xiong. "Session #7 Multi-gate SOI device." In 2008 IEEE International SOI Conference. IEEE, 2008. http://dx.doi.org/10.1109/soi.2008.4656320.

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Kennard, M. "Strained SOI/GOI." In 2006 International SiGe Technology and Device Meeting. IEEE, 2006. http://dx.doi.org/10.1109/istdm.2006.246516.

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"Session 7 Device characteristics, modeling & simulation." In 2004 IEEE International SOI Conference. IEEE, 2004. http://dx.doi.org/10.1109/soi.2004.1391592.

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Trivedi, Vishal, and Jiro Ida. "Session #9 Device characterization, reliability, and modeling." In 2008 IEEE International SOI Conference. IEEE, 2008. http://dx.doi.org/10.1109/soi.2008.4656334.

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Lundstrom, M. S. "The MOSFET Revisited: Device Physics and Modeling at the Nanoscale." In 2006 IEEE international SOI. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284404.

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Xiaorong Luo, Lei Lei, Zhan Zhan, Wei Zhang, Bo Zhang, and Zhaoji Li. "A new membrane SOI power device." In 2008 International Conference on Communications, Circuits and Systems (ICCCAS). IEEE, 2008. http://dx.doi.org/10.1109/icccas.2008.4658001.

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Reports on the topic "SOI Device"

1

Surya, Charles. Leakage Current Measurements in SOI Devices. Fort Belvoir, VA: Defense Technical Information Center, December 1991. http://dx.doi.org/10.21236/ada247694.

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Berney, IV, Kyzar Ernest S., Oyelami James D., and Lawrence O. Device Comparison for Determining Field Soil Moisture Content. Fort Belvoir, VA: Defense Technical Information Center, November 2011. http://dx.doi.org/10.21236/ada552792.

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Tai, Changfeng. An Implantable Neuroprosthetic Device to Normalize Bladder Function after SCI. Fort Belvoir, VA: Defense Technical Information Center, December 2014. http://dx.doi.org/10.21236/ada624765.

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Tai, Changfeng. An Implantable Neuroprosthetic Device to Normalize Bladder Function after SCI. Fort Belvoir, VA: Defense Technical Information Center, October 2012. http://dx.doi.org/10.21236/ada574687.

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Sanders, Thomas J. Statistical Modeling of SOI Devices for the Low Power Electronics Program. Phase 1. Fort Belvoir, VA: Defense Technical Information Center, September 1995. http://dx.doi.org/10.21236/ada299702.

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Benicewicz, Brian C., Glenn A. Eisman, S. K. Kumar, and S. G. Greenbaum. Sol-Gel Based Polybenzimidazole Membranes for Hydrogen Pumping Devices. Office of Scientific and Technical Information (OSTI), February 2014. http://dx.doi.org/10.2172/1121336.

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Susan S. Sorini, John F. Schabron, and Joseph F. Rovani Jr. NEW SOIL VOC SAMPLERS: EN CORE AND ACCU CORE SAMPLING/STORAGE DEVICES FOR VOC ANALYSIS. Office of Scientific and Technical Information (OSTI), June 2006. http://dx.doi.org/10.2172/886850.

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Taylor, Oliver-Denzil, Amy Cunningham,, Robert Walker, Mihan McKenna, Kathryn Martin, and Pamela Kinnebrew. The behaviour of near-surface soils through ultrasonic near-surface inundation testing. Engineer Research and Development Center (U.S.), September 2021. http://dx.doi.org/10.21079/11681/41826.

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Abstract:
Seismometers installed within the upper metre of the subsurface can experience significant variability in signal propagation and attenuation properties of observed arrivals due to meteorological events. For example, during rain events, both the time and frequency representations of observed seismic waveforms can be significantly altered, complicating potential automatic signal processing efforts. Historically, a lack of laboratory equipment to explicitly investigate the effects of active inundation on seismic wave properties in the near surface prevented recreation of the observed phenomena in a controlled environment. Presented herein is a new flow chamber designed specifically for near-surface seismic wave/fluid flow interaction phenomenology research, the ultrasonic near-surface inundation testing device and new vp-saturation and vs-saturation relationships due to the effects of matric suction on the soil fabric.
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Corriveau, Elizabeth, Ashley Mossell, Holly VerMeulen, Samuel Beal, and Jay Clausen. The effectiveness of laser-induced breakdown spectroscopy (LIBS) as a quantitative tool for environmental characterization. Engineer Research and Development Center (U.S.), April 2021. http://dx.doi.org/10.21079/11681/40263.

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Laser-induced breakdown spectroscopy (LIBS) is a rapid, low-cost analytical method with potential applications for quantitative analysis of soils for heavy metal contaminants found in military ranges. The Department of Defense (DoD), Army, and Department of Homeland Security (DHS) have mission requirements to acquire the ability to detect and identify chemicals of concern in the field. The quantitative potential of a commercial off-the-shelf (COTS) hand-held LIBS device and a classic laboratory bench-top LIBS system was examined by measuring heavy metals (antimony, tungsten, iron, lead, and zinc) in soils from six military ranges. To ensure the accuracy of the quantified results, we also examined the soil samples using other hand-held and bench-top analytical methods, to include Inductively Coupled Plasma Optical Emission Spectrometry (ICP-OES) and X-Ray Fluorescence (XRF). The effects of soil heterogeneity on quantitative analysis were reviewed with hand-held and bench-top systems and compared multivariate and univariate calibration algorithms for heavy metal quantification. In addition, the influence of cold temperatures on signal intensity and resulting concentration were examined to further assess the viability of this technology in cold environments. Overall, the results indicate that additional work should be performed to enhance the ability of LIBS as a reliable quantitative analytical tool.
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Susan S. Sorini, John F. Schabron, and Joseph F. Rovani. Validation of a New Soil VOC Sampler: Revision of ASTM Practice D 6418, Standard Practice for Using the Disposable En Core Sampler for Sampling and Storing Soil for Volatile Organic Analysis, and Development of a Subsurface Sampling/Storage Device for VOC Analysis. Office of Scientific and Technical Information (OSTI), September 2003. http://dx.doi.org/10.2172/910128.

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