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1
Suh, Seigi, Ryan Persons, Doug Hargrove, and Gregory Berube. "Solderable Polymer Thick-film Conductors for Low Temperature Substrates." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000310–16. http://dx.doi.org/10.4071/2380-4505-2018.1.000310.
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Abstract For decades, polymer thick-film (PTF) systems have provided a low cost, non-fired option for screen-printing simple electronic circuits. The ability to apply these types of pastes on temperature sensitive substrates such as PET, polycarbonate, polyimide, and other polymers has facilitated a variety of applications, for instance membrane touch-switch keypads, buss bars for touch screens, various types of sensors, and flexible circuitry. Polymer thick-film is also one of the primary technology solutions utilized in the rapidly emerging Printed Electronic market, where flexible, durable materials are paramount to the success of these technologies. One of the largest emerging markets for polymer thick-film is wearable electronics, where engineers are designing “smart fabrics” with active circuitry for medical monitoring, performance enhancement in sports, and personal comfort. Polymer thick-film pastes include silver pastes for conductors, carbon pastes for resistive applications, silver-silver chloride fillers for glucose sensors, and dielectric pastes. The major challenge with PTF silver conductors is that they are not conducive to soldering. This hinders the ability to attach components, leads, dies, wires, or other features to the prints. As copper is solderable, one possible solution would be a copper polymer thick-film metallization; however they start oxidizing at the typical paste curing temperatures, 110 – 130°C, rendering them unsuitable for the vast majority of conductive applications. In order to meet these challenges, Heraeus has developed a new line of solderable polymer thick-film conductors based on a high-performance silver-coated copper conductive filler. These metallizations are solderable, resistant to solder leaching, and result in sheet resistivities approaching that of pure silver polymer conductors. The prints do not degrade in performance when cured at temperatures as high as 200°C. The new product line was formulated to accept different types of solders, especially traditional SAC-305, which provides a complete matched solution for designers. The new metallization opens up new applications given its ability to print polymer circuitry on a variety of substrates including aluminum, steel, FR4, Kapton, Mylar, and glass. The technology also allows for the fabrication of more complex circuitry on these types of substrates, giving circuit designers a powerful new tool in their toolbox in applications such as LED lighting, sensors, and heaters. Finally, these materials may provide a lower-cost option for solderable flexible polymer end terminations for components used in vibration sensitive applications, for instance the automotive industry. In our paper, we will present the properties of the new pastes and printed conductors. Performance testing includes surface resistivity, solderability, solder leach resistance, voiding, and adhesion on two substrates: FR4 and Kapton. Furthermore, we show that the solderable PTF conductor will provide a potential cost- savings over the current technology used on FR4 boards, stamped copper films. By replacing the stamped copper with our solderable PTF conductor, manufacturers will have the advantage of replacing a subtractive process for etching their patterns with an additive, environmentally friendly process, not only saving processing time but eliminating a large, dangerous copper waste stream. Finally, we will summarize the applications that the new technology enables.
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Abdul Aziz, M. S., M. Z. Abdullah, and C. Y. Khor. "Thermal fluid-structure interaction of PCB configurations during the wave soldering process." Soldering & Surface Mount Technology 27, no. 1 (February 2, 2015): 31–44. http://dx.doi.org/10.1108/ssmt-07-2014-0013.
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Purpose – This paper aims to investigate the thermal fluid–structure interactions (FSIs) of printed circuit boards (PCBs) at different component configurations during the wave soldering process and experimental validation. Design/methodology/approach – The thermally induced displacement and stress on the PCB and its components are the foci of this study. Finite volume solver FLUENT and finite element solver ABAQUS, coupled with a mesh-based parallel code coupling interface, were utilized to perform the analysis. A sound card PCB (138 × 85 × 1.5 mm3), consisting of a transistor, diode, capacitor, connector and integrated circuit package, was built and meshed by using computational fluid dynamics pre-processing software. The volume of fluid technique with the second-order upwind scheme was applied to track the molten solder. C language was utilized to write the user-defined functions of the thermal profile. The structural solver analyzed the temperature distribution, displacement and stress of the PCB and its components. The predicted temperature was validated by the experimental results. Findings – Different PCB component configurations resulted in different temperature distributions, thermally induced stresses and displacements to the PCB and its components. Results show that PCB component configurations significantly influence the PCB and yield unfavorable deformation and stress. Practical implications – This study provides PCB designers with a profound understanding of the thermal FSI phenomenon of the process control during wave soldering in the microelectronics industry. Originality/value – This study provides useful guidelines and references by extending the understanding on the thermal FSI behavior of molten solder for PCBs. This study also explores the behaviors and influences of PCB components at different configurations during the wave soldering process.
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Abdul Aziz, M. S., M. Z. Abdullah, and C. Y. Khor. "Effects of Solder Temperature on Pin Through-Hole during Wave Soldering: Thermal-Fluid Structure Interaction Analysis." Scientific World Journal 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/482363.
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An efficient simulation technique was proposed to examine the thermal-fluid structure interaction in the effects of solder temperature on pin through-hole during wave soldering. This study investigated the capillary flow behavior as well as the displacement, temperature distribution, and von Mises stress of a pin passed through a solder material. A single pin through-hole connector mounted on a printed circuit board (PCB) was simulated using a 3D model solved by FLUENT. The ABAQUS solver was employed to analyze the pin structure at solder temperatures of 456.15 K (183°C) <T< 643.15 K (370°C). Both solvers were coupled by the real time coupling software and mesh-based parallel code coupling interface during analysis. In addition, an experiment was conducted to measure the temperature difference (ΔT) between the top and the bottom of the pin. Analysis results showed that an increase in temperature increased the structural displacement and the von Mises stress. Filling time exhibited a quadratic relationship to the increment of temperature. The deformation of pin showed a linear correlation to the temperature. TheΔTobtained from the simulation and the experimental method were validated. This study elucidates and clearly illustrates wave soldering for engineers in the PCB assembly industry.
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Guéné, Emmanuelle, Richard Anisko, and Céline Puechagut. "Solderability and Reliability Evolution of No-Clean Solder Fluxes For Selective Soldering." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000547–56. http://dx.doi.org/10.4071/isom-2017-tha26_146.
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Abstract Flux consumption for wave soldering tends to decrease, mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However, in several cases, wave soldering still remains a must, with an increasing share of “selective” soldering processes, either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation, since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus, flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level, with several types of alloys (tin-lead, tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered. The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based, halides, alcohol-based or water-based flux…), and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes. Then, the development of two low-residue new generation fluxes, an alcohol-based flux and a true VOC-free flux, will be described, according to requirements: the lab tests results (surface tension, spread tests, wettability tests…) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance, electro-chemical migration test, ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally, the performance of flux will be assessed through customer tests, involving several types of boards, finishes and different solder alloys and wave equipment.
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Fonseka, C. L. S. C., and J. A. K. S. Jayasinghe. "Localization of component lead inside a THT solder joint for solder defects classification." Journal of Achievements in Materials and Manufacturing Engineering 2, no. 83 (August 1, 2017): 57–66. http://dx.doi.org/10.5604/01.3001.0010.7033.
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Purpose: Automatic Optical Inspection (AOI) systems, used in electronics industry have been primarily developed to inspect soldering defects of Surface Mount Devices (SMD) on a Printed Circuit Board (PCB). However, no commercially available AOI system exists that can be integrated to a desktop soldering robotic system, which is capable of identifying soldering defects of Through Hole Technology (THT) solder joints along with the soldering process. In our research, we have implemented an AOI platform that is capable of performing automatic quality assurance of THT solder joints in a much efficient way. In this paper, we have presented a novel approach to identify soldering defects of THT solder joints, based on the location of THT component lead top. This paper presents the methodologies that can be used to precisely identify and localize THT component lead inside a solder joint. Design/methodology/approach: We have discussed the importance of lead top localization and presented a detailed description on the methodologies that can be used to precisely segment and localize THT lead top inside the solder joint. Findings: It could be observed that the precise localization of THT lead top makes the soldering quality assurance process more accurate. A combination of template matching algorithms and colour model transformation provide the most accurate outcome in localizing the component lead top inside solder joint, according to the analysis carried out in this paper. Research limitations/implications: When the component lead top is fully covered by the soldering, the implemented methodologies will not be able to identify the actual location of it. In such a case, if the segmented and detected lead top locations are different, a decision is made based on the direction in which the solder iron tip touches the solder pad. Practical implications: The methodologies presented in this paper can be effectively used to have a precise localization of component lead top inside the solder joint. The precise identification of component lead top leads to have a very precise quality assurance capability to the implemented AOI system. Originality/value: This research proposes a novel approach to identify soldering defects of THT solder joints in a much efficient way based on the component lead top. The value of this paper is quite high, since we have taken all the possibilities that may appear on a solder joint in a practical environment.
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Schwebig, Alida Ilse Maria, and Rainer Tutsch. "Compilation of training datasets for use of convolutional neural networks supporting automatic inspection processes in industry 4.0 based electronic manufacturing." Journal of Sensors and Sensor Systems 9, no. 1 (July 1, 2020): 167–78. http://dx.doi.org/10.5194/jsss-9-167-2020.
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Abstract. Ensuring the highest quality standards at competitive prices is one of the greatest challenges in the manufacture of electronic products. The identification of flaws has the uppermost priority in the field of automotive electronics, particularly as a failure within this field can result in damages and fatalities. During assembling and soldering of printed circuit boards (PCBs) the circuit carriers can be subject to errors. Hence, automatic optical inspection (AOI) systems are used for real-time detection of visible flaws and defects in production. This article introduces an application strategy for combining a deep learning concept with an optical inspection system based on image processing. Above all, the target is to reduce the risk of error slip through a second inspection. The concept is to have the inspection results additionally evaluated by a convolutional neural network. For this purpose, different training datasets for the deep learning procedures are examined and their effects on the classification accuracy for defect identification are assessed. Furthermore, a suitable compilation of image datasets is elaborated, which ensures the best possible error identification on solder joints of electrical assemblies. With the help of the results, convolutional neural networks can achieve a good recognition performance, so that these can support the automatic optical inspection in a profitable manner. Further research aims at integrating the concept in a fully automated way into the production process in order to decide on the product quality autonomously without human interference.
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Straubinger, Daniel, István Bozsóki, David Bušek, Balázs Illés, and Attila Géczy. "Modelling of temperature distribution along PCB thickness in different substrates during reflow." Circuit World 46, no. 2 (December 21, 2019): 85–92. http://dx.doi.org/10.1108/cw-07-2019-0074.
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Purpose In this paper, analytical modelling of heat distribution along the thickness of different printed circuit board (PCB) substrates is presented according to the 1 D heat transient conduction problem. This paper aims to reveal differences between the substrates and the geometry configurations and elaborate on further application of explicit modelling. Design/methodology/approach Different substrates were considered: classic FR4 and polyimide, ceramics (BeO, Al2O3) and novel biodegradables (polylactic-acid [PLA] and cellulose acetate [CA]). The board thicknesses were given in 0.25 mm steps. Results are calculated for heat transfer coefficients of convection and vapour phase (condensation) soldering. Even heat transfer is assumed on both PCB sides. Findings It was found that temperature distributions along PCB thicknesses are mostly negligible from solder joint formation aspects, and most of the materials can be used in explicit reflow profile modelling. However PLA shows significant temperature differences, pointing to possible modelling imprecisions. It was also shown, that while the difference between midplane and surface temperatures mainly depend on thermal diffusivity, the time to reach solder alloy melting point on the surface depends on volumetric heat capacity. Originality/value Results validate the applicability of explicit heat transfer modelling of PCBs during reflow for different heat transfer methods. The results can be incorporated into more complex simulations and profile predicting algorithms for industrial ovens controlled in the wake of Industry 4.0 directives for better temperature control and ultimately higher soldering quality.
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Che Ani, Fakhrozi, Azman Jalar, Abdullah Aziz Saad, Chu Yee Khor, Roslina Ismail, Zuraihana Bachok, Mohamad Aizat Abas, and Norinsan Kamil Othman. "SAC–xTiO2 nano-reinforced lead-free solder joint characterizations in ultra-fine package assembly." Soldering & Surface Mount Technology 30, no. 1 (February 5, 2018): 1–13. http://dx.doi.org/10.1108/ssmt-04-2017-0011.
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Purpose This paper aims to investigate the characteristics of ultra-fine lead-free solder joints reinforced with TiO2 nanoparticles in an electronic assembly. Design/methodology/approach This study focused on the microstructure and quality of solder joints. Various percentages of TiO2 nanoparticles were mixed with a lead-free Sn-3.5Ag-0.7Cu solder paste. This new form of nano-reinforced lead-free solder paste was used to assemble a miniature package consisting of an ultra-fine capacitor on a printed circuit board by means of a reflow soldering process. The microstructure and the fillet height were investigated using a focused ion beam, a high-resolution transmission electron microscope system equipped with an energy dispersive X-ray spectrometer (EDS), and a field emission scanning electron microscope coupled with an EDS and X-ray diffraction machine. Findings The experimental results revealed that the intermetallic compound with the lowest thickness was produced by the nano-reinforced solder with a TiO2 content of 0.05 Wt.%. Increasing the TiO2 content to 0.15 Wt.% led to an improvement in the fillet height. The characteristics of the solder joint fulfilled the reliability requirements of the IPC standards. Practical implications This study provides engineers with a profound understanding of the characteristics of ultra-fine nano-reinforced solder joint packages in the microelectronics industry. Originality/value The findings are expected to provide proper guidelines and references with regard to the manufacture of miniaturized electronic packages. This study also explored the effects of TiO2 on the microstructure and the fillet height of ultra-fine capacitors.
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Gera, Günter, Udo Welzel, Yin Jizhe, and Harald Feufel. "Qualitative Model Describing Hot Tear Above VIPPO and Numerous Other Design Elements." Journal of Surface Mount Technology 33, no. 1 (July 14, 2020): 28–33. http://dx.doi.org/10.37665/smt.v33i1.15.
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Over the last couples of years there have been numerous reports of a unique soldering failure resulting in a separation of BGA solder joints from the intermetallic compound at the interposer during reflow. In most cases, the failures were correlated with the use of Via-In-Pad-Plated-Over-Technology. Since the separation could be proven to occur during the phase transition from solid to liquid [1] the term Hot Tear was used. Even though this term is traditionally only used for tears during solidification its scope was extended to tears during any phase transition. Since the Hot Tear results in a very thin separation it is usually not inspectable, neither by means of X-Ray inspection nor by electrical testing, but results in very early field failures.
In this paper, the general mechanism for the formation of Hot Tears will be discussed and applied to numerous other design elements that can be found on Printed Circuit Board Assemblies. We will show that due to several industry trends e.g. VIPPO, heavy copper PCBs, buried vias, non-eutectic alloys, thinner components, thicker boards, via in pad, etc. the probability of Hot Tears is steadily increasing.
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Géczy, Attila, Bíborka Kvanduk, Balazs Illes, and Gábor Harsányi. "Comparative study on proper thermocouple attachment for vapour phase soldering profiling." Soldering & Surface Mount Technology 28, no. 1 (February 1, 2016): 7–12. http://dx.doi.org/10.1108/ssmt-10-2015-0033.
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Purpose – The paper aims to present a comparative study of various thermocouple (TC) attaching methods for the proper measurement of soldering temperature profiling during vapour phase soldering (VPS). The heat transfer process during VPS is different from common methods, while the required heat for reflow is provided by the condensation. The condensate is a flowing layer on the board, where the dynamic behaviour also affects the local conditions on the surfaces. Temperature measurements based on TCs are also affected this way; it is important to investigate the process for deeper understanding. Design/methodology/approach – Bare printed circuit boards (PCBs) were prepared for standard K-Type TCs attachment with industry standard materials: kapton polyimide tape, aluminium tape, SMD adhesive and high-temperature solder (HTS). Heating experiments were performed in a batch-type VPS oven with Galden LS240 fluid and fixed oven parameters. Findings – According to the specific attachment requirements, HTS and Alu-tape are the suggested methods for better profiling reliability and repeatability. Alu-tape is the preferred all-around method, for fast, exchangeable, cheap, reliable and repeatable profiling in a VPS oven. It was presented that the heating factor (Q?) gives more reliable comparison overview; the time period-based comparisons may be affected by the thermal inertia, while heating factor also includes temperature conditions at the given time points. Originality/value – The paper presents the reliability of the presented methods for VPS and present suggestions for the use of different TC ends and attaching materials during condensation heating of the PCBs. Also a new approach on profiling data evaluation based on the heating factor is presented and suggested for wider use.
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Carpenter, Burton, Andrew Mawer, Mollie Benson, John Arthur, and Betty Young. "Solder-Joint Reliability of BGA Packages in Automotive Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000236–57. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_ta3_040.
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The solder-joint interconnect between an IC component and the PCB (printed circuit board) is a critical link in the system overall reliability. Trends in the automotive market are driving increased focus on solder-joint performance: (1) increasing electronics content for new functions, especially for ADAS (advanced driver-assistance systems), (2) use in safety critical systems and sub-systems, (3) decreasing interconnect pitches which reduces the stand-off and available solder, (4) increasing industry reliability expectations, and (5) package variations (ex. multi-die). In particular, BGA (Ball Grid Array) packages are used throughout the vehicle across various systems including engine control, braking, communication, infotainment, and radar to name only a few. Among these, under-the-hood applications often require high sustained operating temperatures and many heating/cooling cycles during the vehicle lifetime. The reliability of these interconnects is routinely assessed by cyclical thermal stress (temperate cycling) of components mounted to boards. While AEC (Automotive Electronics Council) offers no standards for solder-joint testing (for example, board level reliability criteria is not included in the AEC Q100 “Failure Mechanism Based Stress Test Qualification for Integrated Circuits”), IPC 9701A “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments” can be followed. For automotive under-the-hood the specified cycle range is 40°C to 125°C (TC3). This paper summarizes the BL-TC (board level temperature cycle) performance of various BGA packages used in automotive applications. In all cases the test vehicle packages were daisy-chain versions of production devices, while maintaining critical features such as BGA footprint, physical dimensions, BOM (bill of materials), die size and thickness and substrate layer metal densities. All used Pb-free solders for both the BGA solder ball and the paste printed onto the PCB. The PCB designs were complementary to the packages establishing daisy-chain connections winding through the PCB, the solder-joint and package substrate. Each chain (net) was continuously monitored in situ during cycling. An event detector logged a failure when a net resistance exceeded 300 ohms. Wirebonded and flip chip packages were studied, ranging in size from 10mm to 29mm with BGA pitches including 0.65mm, 0.80mm and 1.00mm. In addition to these primary attributes, various other factors were found to alter the solder-joint lifetimes. For example, increasing BGA pad and solder sphere diameters improved solder-joint lifetime, but increasing the PCB pad diameter often did not. Among solder materials, eutectic SnAg typically showed longer lifetimes than other high Ag SAC alloys such as SAC305 and SAC405. The addition of Bi to the SAC alloy showed promise for further improvements. Other factors that were studied include die thickness, die size, and BGA pad finish. Both mechanical cross-section and dye penetrant analysis (dye-and-pry) were employed for failure analysis, enabling study of crack propagation and crack location within the solder-joint. Additionally, failure location (failing solder-joint) was identified for each as package corner, under the die edge, or package center in a predictable pattern depending on the package type. Examined in total, two opposing trends will force future innovation. Industry reliability requirements continue to drive expectations (i.e. cycles to failure) higher, while increasing package size and decreasing pitch will naturally reduce the solder-joint lifetimes. Solutions will be found in package design, package material and solder selections.
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Hegde, Rama, Anne Anderson, Sam Subramanian, Andrew Mawer, Ed Hall, VK Leong, and A. Selvakumar. "Analysis of 16 QFN Device I/O Pads for Solderability Failures." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000675–84. http://dx.doi.org/10.4071/isom-2015-tha53.
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In-process failures were experienced during printed circuit board (PCB) SMT assembly of a 16 Quad Flat No Leads (QFN) device. The failures appeared to be solderability related with QFN unit I/O pads not soldering robustly and sometimes leading to QFN detachment following board mounting. When assembly did take place on affected QFN units, the resulting solder joint was observed to be weak. This paper reports on very systematic analyses of the QFN device I/O pads using optical inspections, AES surface, AES depth profiling, SEM/EDX, SIMS, FIB and TEM cross-sectional measurements to determine the root cause of the failure and the failure mechanism. The detached QFN units, suspect and good unsoldered units, passing and failing units obtained from customers were examined. The industry standard surface mount solderability testing was performed on good and suspect parts, and all were observed to pass as evidenced by >95% coverage of the I/O pads. Optical inspections and a wide variety of physical analysis of the pads on fresh parts showed no anomalies with only the expected Au over Pd over Ni found. AES analysis was performed including depth profiling to look for any issues in the NiPdAu over base Cu plating layers that could be contributing the solderability failures. The AES depth profiling indicated AuPd film on the Ni under layer for the I/O pads as expected. No unexpected elements or oxide layers were observed at any layer. Then, one failing and one passing units were compared by doing FIB cross-section, FIB planar section and TEM cross-section analysis. The cross-sectional analysis showed rough Ni surface for the failing units, while the Ni surface was relatively smooth for the passing unit. Further, finer Cu grains and Ni grains were observed on the passing units. Additionally, the lead frame fabrication process mapping showed rough Cu, Ni “texturing” and use of low electro chemical polishing (ECP) current on the bad units compared to that of the good units. All affected bad units were confirmed coming from a second source Cu supplier with the rough Cu. The weak and irregular NiSn IMC formation on the bad units caused IMC separation and possible spalling during board solder reflow primarily due to the rough base Cu and irregular grain sizes and resulting lower ECP lead frame plating current. A possible final factor was marginally low Pd thickness. In conclusion, the 16 QFN device solderability failure root cause summary and the lessons learned from a wide variety of analysis techniques will be discussed.
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Carvalho, Violeta, Bruno Arcipreste, Delfim Soares, Luís Ribas, Nelson Rodrigues, Senhorinha F. C. F. Teixeira, and José Carlos Teixeira. "Numerical Modeling of the Wave Soldering Process and Experimental Validation." Journal of Electronic Packaging 144, no. 1 (August 6, 2021). http://dx.doi.org/10.1115/1.4050981.
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Abstract One of the most important procedures in the electronics industry is the assembly of electronic components onto printed circuit boards (PCBs) through the soldering process. Among the various soldering methods available, wave soldering is a very effective technique. In this process, the components are placed onto the PCB, which, subsequently, is coated with a flux and then passed across a preheat zone. In the end, the assembly is moved by the conveyor and passed over the surface of the molten solder wave in order to create a reliable connection both mechanically and electrically. Although this process has been frequently used, there are soldering defects that remain unsolved and continue to emerge, such as the missing of surface-mount components in the PCB after the soldering process. Aiming to understand if such defects are related to the force exerted by the solder wave in the PCB, a numerical and experimental study was performed in this article. For this purpose, a computational fluid dynamic model was developed by using the fluent software to describe the interaction between the solder jet and the PCB with the integrated circuits, and the multiphase method, volume of fluid, was also applied to track the solder–air interface boundary. The results obtained were numerically validated by using an experimental setup designed and built to this end. In general, the data obtained showed to be in good agreement and it was concluded that the force exerted by the solder wave is approximately 0.02 N.
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Wang, Xiaoping, Jun Yang, Xiaogang Liu, Panpan Zheng, Qinglin Song, Bin Song, and Sheng Liu. "Reliability Analysis of Solder Joints on Rigid-Flexible Printed Circuit Board for MEMS Pressure Sensors Under Combined Temperature Cycle and Vibration Loads With Continuously Monitored Electrical Signals." Journal of Electronic Packaging 144, no. 1 (August 6, 2021). http://dx.doi.org/10.1115/1.4049813.
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Abstract The reliability of lead-free solder joints on flexible printed circuit board (PCB) has created significant new challenges in the industry, especially in automotive electronics, and possibly for future wearable electronics. In the automotive industry, thermal cycling test and random vibration test need to be conducted to certify every electronic product to be used in harsh automotive environments. In order to accelerate the testing time, we may need to subject the electronic components, in particular, sensors to both loadings such as thermal cycling and vibration. During all the experiments, the electrical signals of each specimen were continuously monitored by using an event detector. One advantage of this method is that any individual soldering interconnect failure will result in the diagnostic signal of the circuit, which could be detected in real-time. A simulation was used to confirm the possibility of the stress concentration location caused by the vibration and thermal cycling loads. The influence of vibration frequency and acceleration on the vibration fatigue life of solid joints was investigated. In this paper, the submodeling technique was used to construct the finite element model of the rigid-flexible printed circuit board (rigid-flexible PCB) coupled with a MEMS pressure sensor subjected to temperature cycle and random vibration loadings. The research results are helpful to effectively characterize the performance of the MEMS sensors under both thermal cycling test and vibration test. Two kinds of land shapes and two kinds of PCB assemblies were selected. In order to investigate the crack growth in the solder joint, the solder joint is sliced and the crack on the cross section of the solder joint was observed. Results of finite element modeling analysis were consistent with the experimental results. Two design parameters have been identified in our research as being important to soldering usage in automotive environments: pad type (teardrop versus nonteardrop) and pad size (big versus small, matching size for Cu-wire and pad). Experimental results also showed that the solder joint with a big land shape presented a relatively good thermal fatigue resistance.
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Carvalho, Violeta, Bruno Arcipreste, Delfim Soares, Luís Ribas, Nelson Rodrigues, Senhorinha Teixeira, and José C. Teixeira. "Experimental measurements of the shear force on surface mount components simulating the wave soldering process." Soldering & Surface Mount Technology ahead-of-print, ahead-of-print (June 7, 2021). http://dx.doi.org/10.1108/ssmt-12-2020-0057.
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Purpose This study aims to determine the minimum force required to pull out a surface mount component in printed circuit boards (PCBs) during the wave soldering process through both experimental and numerical procedures. Design/methodology/approach An efficient experimental technique was proposed to determine the minimum force required to pull out a surface mount component in PCBs during the wave soldering process. Findings The results showed that the pullout force is approximately 0.4 N. Comparing this value with the simulated force exerted by the solder wave on the component ( ≅ 0.001158 N), it can be concluded that the solder wave does not exert sufficient force to remove a component. Originality/value This study provides a deep understanding of the wave soldering process regarding the component pullout, a critical issue that usually occurs in the microelectronics industry during this soldering process. By applying both accurate experimental and numerical approaches, this study showed that more tests are needed to evaluate the main cause of this problem, as well as new insights were provided into the depositing process of glue dots on PCBs.
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Turbini, Laura J., Garth B. Freeman, and David Cauffiel. "Characterizing Soldering Fluxes." MRS Proceedings 323 (1993). http://dx.doi.org/10.1557/proc-323-147.
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AbstractFor a number of years electronic manufacturers of printed circuit assemblies have used rosin-based soldering fluxes. Post-solder cleaning was accomplished with chlorinated or chlorofluorocarbon (CFC) solvents. With the elimination of these solvent options due to their destructive effect on the stratospheric ozone layer, manufacturers are looking to alternative cleaners for rosin flux or to new flux choices which can be cleaned with water, or left uncleaned.Many of the flux formulations are new and their long-term effect on the performance of product manufactured with them is unknown. Although ionic contamination testers can alert one to the ionic levels remaining on an assembly, the corrosivity of the residues is not directly related to the total ionic level, but only to certain ionic species. Surface insulation resistance testing is used by many in the industry, but the results are complex and often misunderstood.All of these factors have been the driving force to develop a quantitative screening test for soldering flux residues. This test, originally conceived by Dr. David Bono, has been modified and developed at Georgia Tech to provide a quantitative evaluation of flux residue corrosivity. This work, in collaboration with the work being performed by the French standards group, will result in a new international industry standard. This paper reports the latest data on this important test development.
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Korhonen, M. A., D. D. Brown, C. Y. Li, and J. E. Steinwall. "Mechanical Properties of Plated Copper." MRS Proceedings 323 (1993). http://dx.doi.org/10.1557/proc-323-103.
Full textAbstract:
AbstractBoth electrodeposited and electroless copper are widely used in the electronics industry to form signal lines and plated-through holes in printed circuit cards and boards. Because of widely differing thermal expansion coefficients of copper and of the ceramic and polymeric substrates, large mechanical stresses develop in the metallization during thermal cycles, as e.g. during solder reflow. To safeguard against premature fracture it is imperative that the metallization is sufficiently ductile. Plated thin foil copper of poor ductility is known to be susceptible to cracks in plated-through holes which, besides causing problems in the manufacture, poses a threat to device reliability in service. In this paper we show that such cracks arise as a combination of reduced ductility due to presence of initial porosity in copper and due to grain boundary sliding and diffusional cavity growth during the soldering cycle. We emphasize that there exists strong interactions between these ductility reducing effects, such that their coupled action may exceed the effect when each mechanism operates independently. We review recent research on deformation and fracture of bulk and plated copper between RT and 300°C. Finally, we briefly discuss approaches to improve mechanical properties of plated thin foil copper.