Academic literature on the topic 'Space Vector Pulse Width Modulation (SVPWM)'

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

L’impact des stratégies Modulation de Largeur d'Impulsion (MLI) sur les sollicitations des condensateurs de découplage en entrée d’un onduleur triphasé est bien connu à l’heure actuelle au même titre que le comportement de la charge alimentée (facteur de puissance). On dispose à l’heure actuelle d’un large panel de techniques de modulation applicables en fonction des diverses contraintes d’environnement (stress des condensateurs mais aussi qualité des courants dans la charge ou pertes par commutation dans les semi-conducteurs). Toutefois, dans de nombreux contextes applicatifs, le bus continu peut être mutualisé entre plusieurs convertisseurs qui vont solliciter individuellement le ou les condensateurs de découplage. L’objectif de cette thèse est d'étudier la mise en œuvre des stratégies MLI coordonnées entre plusieurs onduleurs mutualisant leur bus continu. Plus précisément, une étude du cas des convertisseurs back-to-back dans le cas de MADA a été faite. De plus, cette étude vise à évaluer l'impact de stratégies MLI entrelacées sur le courant efficace traversant le condensateur de découplage associé à deux convertisseurs en parallèle. En effet, cette valeur est généralement le paramètre clé pour le dimensionnement de ce (ou ces) composant(s), bien au-delà de la capacité, notamment pour les condensateurs électrolytiques à l'aluminium. La technique d'entrelacement est appliquée selon deux stratégies différentes : - La stratégie classique SVPWM ; - La stratégie MLI à double porteuse unifié (Uni-DCPWM) qui est dédié à la réduction du courant efficace pour un seul convertisseur. Notre étude vise également à réduire le courant RMS dans le condensateur et à trouver la valeur optimale du temps d'entrelacement de manière dynamique pour tous les points de fonctionnement<br>The impact of Pulse Width Modulation (PWM) strategies on the stresse of the decoupling capacitors at the input of a three-phase converter is currently well known, as well as the behavior of the supplied load (power factor). A large panel of modulation techniques is currently available and can be applied according to the various environmental constraints (stress on the capacitors but also quality of the currents in the load or switching losses in the semiconductors). However, in many application contexts, the DC bus can be shared between several converters that will individually stress the decoupling capacitor(s). The objective of this thesis is to study the implementation of PWM strategies between several converters sharing their DC bus. More precisely, a study of the case of back-to-back converters connected on Doubly Fed Induction Machine (DFIM) has been done. The aim of this study is to evaluate the impact of interleaved PWM strategies on the RMS current flowing through the DC link capacitor associated to two back-to-back three-phase Full Bridges (FB). Indeed, this value is usually the key-parameter for the sizing of this (or these) component(s), far above the capacitance, especially for aluminum electrolytic capacitors. Interleaving technique is applied on two different strategies: - Classical (single carrier) Space-Vector PWM strategy (SVPWM) ; - Unified Double Carrier PWM (Uni-DCPWM) that is dedicated to the reduction of the RMS current for a single FB. Our study also aims to reduce the RMS current in the capacitor and find the optimal value of the interleaving time dynamically for all operating points