Dissertations / Theses on the topic 'Space Vector Pulse Width Modulation (SVPWM)'

The dissertation documents research work carried out on Pulse Width Modulation (PWM) strategies for hard switched Voltage Source Inverters (VSI) for variable speed electric drives. This research is aimed at Hybrid Electric Vehicles (HEV). PWM is at the heart of all variable speed electric drives; they have a huge influence on the overall performance of the system and may also help eventually give us an extra degree of freedom in the possibility to rethink the inverter design including the re-dimensioning of the inverter components.HEVs tend to cost more than conventional internal combustion engine (ICE) vehicles as they have to incorporate two traction systems, which is the major discouraging factor for consumers and in turn for manufacturers. The two traction system increases the maintenance cost of the car as well. In addition the electric drives not only cost extra money but space too, which is already scarce with an ICE under the hood. An all-electric car is not yet a viable idea as the batteries have very low energy density compared with petrol or diesel and take considerable time to charge. One solution could be to use bigger battery packs but these add substantially to the price and weight of the vehicle and are not economically viable. To avoid raising the cost of such vehicles to unreasonably high amounts, autonomy has to be compromised. However hybrid vehicles are an important step forward in the transition toward all-electric cars while research on better batteries evolves. The objective of this research is to make electric drives suitable for HEVs i.e. lighter, more compact and more efficient -- requiring less maintenance and eventually at lower cost so that the advantages, such as low emissions and better fuel efficiency, would out-weigh a little extra cost for these cars. The electrical energy source in a vehicle is a battery, a DC Voltage source, and the traction motor is generally an AC motor owing to the various advantages it offers over a DC motor. Hence the need for a VSI, which is used to transform the DC voltage into AC voltage of desired amplitude and frequency. Pulse width modulation techniques are used to control VSI to ensure that the required/calculated voltage is fed to the machine, to produce the desired torque/speed. PWM techniques are essentially open loop systems where no feedback is used and the instantaneous values differ from the required voltage, however the same average values are obtained. Pulse width modulated techniques produce a low frequency signal (desired average value of the switched voltage) also called the fundamental component, along with unwanted high frequency harmonics linked to the carrier signal frequency or the PWM period. In modern cars we see more and more mechanical loads driven by electricity through digital processors. It is very important to eliminate the risk of electromagnetic interference between these systems to avoid failure or malfunction. Hence these unwanted harmonics have to be filtered so that they do not affect the electronic control unit or other susceptible components placed in the vicinity. Randomised modulation techniques (RPWM) are used to dither these harmonics at the switching frequency and its multiple. In this thesis a random modulator based on space vector modulation is presented which has additional advantages of SVM. Another EMI problem linked to PWM techniques is that they produce common mode voltages in the load. For electric machines, common mode voltage produces shaft voltage which in turn provokes dielectric stress on the motor bearings, its lubricant and hence the possibility of generating bearing currents in the machine that can be fatal for the machine. To reduce the common mode voltage a space vector modulation strategy is developed based on intelligent placement of zero vectors. (...)

Ce travail de recherche s'intéresse à la commande sans capteur mécanique du moteur synchrone à aimants permanents (MSAP) à pôles saillants, particulièrement en basse vitesse, avec détection de la position initiale du rotor. Après une présentation des techniques et approches qui ont initié nos travaux, en terme d'estimation de la vitesse et/ou de la position, nous avons choisi celles qui présentent plus d'intérêt de point de vue stabilité, robustesse, précision et simplicité d'implémentation. La première approche est basée sur le Système Adaptatif avec Modèle de Référence (MRAS). Quant à la deuxième, elle est réalisée autour d'un observateur non-linéaire pour l'estimation de la position et de la vitesse du MSAP à pôles saillants. Les deux techniques d'observation de la vitesse sont associées à une commande par orientation du flux rotorique avec la technique MLI vectorielle. Pour détecter la position initiale du rotor, nous avons utilisé une nouvelle approche qui permet d'estimer cette position avec une incertitude de 5° mécanique. Cette nouvelle approche est basée sur l'application de signaux tests aux bornes des phases statoriques du MSAP. Des résultats de simulation et expérimentaux sont présentés tout au long de ces travaux pour valider les études théoriques de la commande vectorielle sans capteur mécanique du MSAP. Enfin, nous avons étudié et analysé les performances de la commande tolérante aux défauts sans capteur mécanique du MSAP en présence de défaillances de types transistors à l'état-off. Les résultats expérimentaux obtenus avec les deux approches d'estimation de la vitesse en utilisant l'observateur MRAS et un observateur non linéaire ont permis d'améliorer la fiabilité du système de manière à rendre possible la commande vectorielle sans capteur mécanique en mode dégradé (alimentation avec deux bras de l'onduleur). En effet, les résultats de la commande sans capteur mécanique de la MSAP en mode dégradé montrent que l'observateur non linéaire est le mieux adapté pour ce type de fonctionnement car il présente de faible ondulation du couple et de vitesse. A l'aide d'un banc d'essais que nous avons développé au laboratoire LSIS-pôle Ecole Centrale de Marseille (ECM), nous avons pu valider expérimentalement les différentes approches proposées dans ce travail de recherche. Les résultats obtenus montrent l'efficacité des techniques mises en œuvre pour la commande vectorielle sans capteur mécanique du MSAP à pôle saillant en termes de robustesse, stabilité, précision et rapidité.

Orientador: Prof. Dr. José Alberto Torrico Altuna<br>Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2016.<br>O presente trabalho estuda as técnicas de modulação de inversores trifásicos com aplicação principal em controle de máquinas de indução. Na primeira parte é realizada a pesquisa bilbiográfica considerando as principais técnicas de modulação, sendo apresentado depois o princípio de funcionamento destes moduladores. A operação do inversor é estudada apresentando os sinais trifásicos gerados a partir de uma fonte de tensão C.C. É feita a descrição do PWM senoidal baseado em portadora seno¿triangulo e o PWM baseado em vetores espaciais. Também é apresentada uma estratégia de modulação na região de sobre modulação. O principio de modulação aleatorea é estudado citando as contribuições principais nesta área. Finalmente é apresentada a modulação por eliminação seletiva de harmônicas e as principais referências. São apresentados resultados de simulação dos principais métodos de modulação considerando os principais parâmetros de desempenho. Como aplicação de técnicas de modulação em inversores, é apresentada uma estratégia para compensação de tensão usando restauradores dinâmicos de tensão DVR.<br>This dissertation studies modulation techniques for three-phase inverters intended to induction motor control. The First part is literature review regarding the main modulation techniques. Secondly it is described the operation principle of voltage source inverter showing three-phase signals generated from a C.C voltage. It is made a PWM description based on carrier (sine-triangle) and space vector modulation in both linear and over modulation region. The principle of random modulation is presented mentioning the main contributions in this area. It is showed the modulation by selective elimination of harmonics and the main references. Simulation results from modulation schemes are presented taking into account performance of each method. As application it is presented a strategy for Dynamic Voltage Restorer (DVR).

Orientadores: Ernesto Ruppert Filho, Marcelo Gradella Villalva<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação<br>Made available in DSpace on 2018-08-21T14:53:53Z (GMT). No. of bitstreams: 1 Espindola_MarcosFernando_M.pdf: 5114547 bytes, checksum: 1601ee84cd6d17c671ba644a288c398d (MD5) Previous issue date: 2012<br>Resumo: Apresenta-se a implementação de um inversor trifásico de tensão a três níveis para ser utilizado no controle de velocidade de um motor síncrono trifásico a imãs permanentes usando o método de controle vetorial. Realizou-se o estudo, projeto e construção de um inversor de tensão a três níveis com neutro grampeado ou inversor NPC neutral point clamped. Utilizou-se modulação em largura de pulsos por vetores espaciais no controle vetorial de velocidade do motor. Foram realizadas simulações do sistema proposto usando os aplicativos computacionais Matlab/Simulink e PSIM. Realizou-se em seguida uma montagem experimental constituída de um motor síncrono a imãs permanentes de 0,75 kW acoplado a um freio eletromagnético que lhe serviu de carga mecânica. O sistema motor e carga foi acionado pelo inversor com modulação em largura de pulsos por vetores espaciais e os resultados obtidos do controle de velocidade realizado, incluindo reversão de velocidade e frenação do motor, são apresentados no trabalho. Comparou-se também o desempenho de um inversor a três níveis usando modulação em largura de pulsos por vetores espaciais com o desempenho de um inversor a dois níveis usando modulação em largura de pulsos por vetores espaciais na alimentação de uma carga resistiva. Resultados de simulação e resultados experimentais são apresentados. Neste trabalho realizou-se uma comparação qualitativa entre o uso do inversor a dois níveis e do inversor a três níveis que mostra em que situações é conveniente utilizar o inversor a três níveis<br>Abstract: It is presented the implementation of a three phase three level voltage inverter to be used in the speed control of a three phase permanent magnet synchronous motor using the vector control method. To achieve this goal, it was carried out the study, design and construction of a three level neutral point clamped voltage inverter or NPC inverter. For the control of the motor it was used a space vector modulation. The proposed system was simulated using Matlab/Simulink and PSIM softwares. It was carried out an experimental assembly consisting of a 0.75 kW permanent magnet synchronous motor coupled to an electromagnetic brake as a mechanical load. The motor and load system were triggered by the inverter with space vector modulation. The results of the speed control, including reversal of speed and motor breaking, are presented in the study. The performance of a three level inverter using space vector modulation is compared to the performance of a two level inverter using space vector modulation feeding a resistive load. The simulation and experimental results are presented. In this work a qualitative comparison between the two level inverter and three level inverter was done showing in wich situations it is better to use the three level inverter<br>Mestrado<br>Energia Eletrica<br>Mestre em Engenharia Elétrica

Ces travaux de thèse s’inscrivent dans le cadre du projet EDC (Electrical Driven Compressor), qui vise à développer des compresseurs de climatisation électriques fiables, compacts, conformes aux normes automobiles et à faible coût de production. Cette thèse est composée de deux parties. La première partie est consacrée à la suppression des capteurs de courants de phase et à leur remplacement par un seul capteur de courant au niveau du bus continu. Cette suppression a été accompagnée du développement d'un algorithme de reconstruction des courants de phase. La modification de la loi de commande SVPWM par un algorithme analytique a été rendue nécessaire afin d'assurer la reconstruction des courants de phase sur toute la plage de fonctionnement. Des résultats de simulation et d’expérimentation ont montré le bon fonctionnement de l’algorithme de reconstruction des courants de phase en utilisant la SVPWM modifiée. La deuxième partie de ce travail a consisté à réduire les interférences électromagnétiques via la commande, en utilisant des techniques d’étalement spectral basée sur la PWM aléatoire. La complexité de cette partie a principalement concerné l'adaptation de cette méthode à notre algorithme de reconstruction basé sur la SVPWM modifiée. Les résultats de simulation et les résultats expérimentaux ont montré un bon étalement spectral des différentes harmoniques des courants de phase et des tensions de sortie de l’onduleur<br>This thesis work is part of the EDC (Electrical Driven Compressor) project, which aims to develop reliable, compact electric air conditioning compressors that comply with automotive standards and have low production costs. This thesis is made up of two parts. The first one is devoted to the elimination of phase current sensors and their replacement by a single current sensor at the DC bus level. This removal was performed with the help of an algorithm for the reconstruction of phase currents. The modification of the SVPWM control law by an analytical algorithm was made necessary in order to ensure the reconstruction of the phase currents over the entire operating range. Simulation and experimentation results have shown the good working of the phase current reconstruction algorithm using the modified SVPWM. The aim of the second part of this work was to reduce electromagnetic interference by control, using spread spectral techniques based on random PWM. The complexity of this part mainly concerned the adaptation of this method to our reconstruction algorithm based on the modified SVPWM. The simulation results and the experimental results showed good spectral spreading of the different harmonics of the phase currents and the output voltages of the inverter

Ce sujet s’inscrit dans la continuité des activités de recherche du laboratoire GREAH sur les problématiques de la gestion optimale d’énergie électrique embarqué à bord des véhicules électriques hybrides. En effet, le couplage de plusieurs sources de natures différentes entraîne des problématiques de dimensionnement, de qualité d’énergie et de la durée de vie des éléments interconnectés. Pour les applications de transport par exemple, les principaux facteurs de ces problématiques reposent sur : - les fluctuations de la puissance demandée par la chaîne de propulsion/ traction, la durée de vie limitée des éléments de stockage d’énergie électrique, l’absence de profil de mission standard réaliste et la nécessité d’optimisation de la consommation énergétique du bord. La méthode adéquate pour l’étude des systèmes multi-sources passe par une approche systémique. Cette approche est nécessaire pour établir des modèles comportementaux des sources et des convertisseurs en vue de l'élaboration des stratégies de gestion optimale des flux énergétiques entre les organes. Le premier objectif de la thèse repose sur le développement des modèles de comportement des batteries et supercondensateurs soumis aux contraintes thermiques et électriques spécifiques aux applications de transport. Le second vise le développement de la stratégie de la gestion d’énergie prenant en compte de l’impact de la température et les fluctuations de puissance demandée par la chaîne de propulsion/ traction (charge)<br>The research work presented in this document is a continuation of the GREAH laboratory research activities on the issues of optimal energy management on board of electric and hybrid electric vehicles. Indeed, the coupling of several electrical energy sources with different characteristics causes several issues like energy sources sizing, energy exchange quality and the lifetime of the interconnected elements. In the case of transport applications, the main factors of these problems are based on the high fluctuations in the power required by the propulsion/traction chain; the limited life expectancy of the electrical energy storage elements; the lack of realistic standard mission profile and the need to optimize the electric vehicles energy consumption. The appropriate method for studying the multi-source systems is by using systemic approach. This approach is necessary to establish behavioral models of energies sources and power converters for the development of optimal energy management strategies. The contribution of this thesis is focused on the investigation and the development of energy management strategies considering the electrical energy sources performances and their state of functioning according to the power fluctuations from the propulsion/traction chain, which presents the load in a touristic vehicle

In recent years, multilevel converters are becoming more popular and attractive than traditional converters in high voltage and high power applications. Multilevel converters are particularly suitable for harmonic reduction in high power applications where semiconductor devices are not able to operate at high switching frequencies or in high voltage applications where multilevel converters reduce the need to connect devices in series to achieve high switch voltage ratings. This thesis investigated two aspects of multilevel converters: structure and control. The first part of this thesis focuses on inductance between a DC supply and inverter components in order to minimise loop inductance, which causes overvoltages and stored energy losses during switching. Three dimensional finite element simulations and experimental tests have been carried out for all sections to verify theoretical developments. The major contributions of this section of the thesis are as follows: The use of a large area thin conductor sheet with a rectangular cross section separated by dielectric sheets (planar busbar) instead of circular cross section wires, contributes to a reduction of the stray inductance. A number of approximate equations exist for calculating the inductance of a rectangular conductor but an assumption was made that the current density was uniform throughout the conductors. This assumption is not valid for an inverter with a point injection of current. A mathematical analysis of a planar bus bar has been performed at low and high frequencies and the inductance and the resistance values between the two points of the planar busbar have been determined. A new physical structure for a voltage source inverter with symmetrical planar bus bar structure called Reduced Layer Planar Bus bar, is proposed in this thesis based on the current point injection theory. This new type of planar busbar minimises the variation in stray inductance for different switching states. The reduced layer planar busbar is a new innovation in planar busbars for high power inverters with minimum separation between busbars, optimum stray inductance and improved thermal performances. This type of the planar busbar is suitable for high power inverters, where the voltage source is supported by several capacitors in parallel in order to provide a low ripple DC voltage during operation. A two layer planar busbar with different materials has been analysed theoretically in order to determine the resistance of bus bars during switching. Increasing the resistance of the planar busbar can gain a damping ratio between stray inductance and capacitance and affects the performance of current loop during switching. The aim of this section is to increase the resistance of the planar bus bar at high frequencies (during switching) and without significantly increasing the planar busbar resistance at low frequency (50 Hz) using the skin effect. This contribution shows a novel structure of busbar suitable for high power applications where high resistance is required at switching times. In multilevel converters there are different loop inductances between busbars and power switches associated with different switching states. The aim of this research is to consider all combinations of the switching states for each multilevel converter topology and identify the loop inductance for each switching state. Results show that the physical layout of the busbars is very important for minimisation of the loop inductance at each switch state. Novel symmetrical busbar structures are proposed for multilevel converters with diode-clamp and flying-capacitor topologies which minimise the worst case in stray inductance for different switching states. Overshoot voltages and thermal problems are considered for each topology to optimise the planar busbar structure. In the second part of the thesis, closed loop current techniques have been investigated for single and three phase multilevel converters. The aims of this section are to investigate and propose suitable current controllers such as hysteresis and predictive techniques for multilevel converters with low harmonic distortion and switching losses. This section of the thesis can be classified into three parts as follows: An optimum space vector modulation technique for a three-phase voltage source inverter based on a minimum-loss strategy is proposed. One of the degrees of freedom for optimisation of the space vector modulation is the selection of the zero vectors in the switching sequence. This new method improves switching transitions per cycle for a given level of distortion as the zero vector does not alternate between each sector. The harmonic spectrum and weighted total harmonic distortion for these strategies are compared and results show up to 7% weighted total harmonic distortion improvement over the previous minimum-loss strategy. The concept of SVM technique is a very convenient representation of a set of three-phase voltages or currents used for current control techniques. A new hysteresis current control technique for a single-phase multilevel converter with flying-capacitor topology is developed. This technique is based on magnitude and time errors to optimise the level change of converter output voltage. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimise switching losses. Logic controls require handling a large number of switches and a Programmable Logic Device (PLD) is a natural implementation for state transition description. The simulation and experimental results describe and verify the current control technique for the converter. A novel predictive current control technique is proposed for a three-phase multilevel converter, which controls the capacitors' voltage and load current with minimum current ripple and switching losses. The advantage of this contribution is that the technique can be applied to more voltage levels without significantly changing the control circuit. The three-phase five-level inverter with a pure inductive load has been implemented to track three-phase reference currents using analogue circuits and a programmable logic device.

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

The ability of a piezoelectric transducer in energy conversion is rapidly expanding in several applications. Some of the industrial applications for which a high power ultrasound transducer can be used are surface cleaning, water treatment, plastic welding and food sterilization. Also, a high power ultrasound transducer plays a great role in biomedical applications such as diagnostic and therapeutic applications. An ultrasound transducer is usually applied to convert electrical energy to mechanical energy and vice versa. In some high power ultrasound system, ultrasound transducers are applied as a transmitter, as a receiver or both. As a transmitter, it converts electrical energy to mechanical energy while a receiver converts mechanical energy to electrical energy as a sensor for control system. Once a piezoelectric transducer is excited by electrical signal, piezoelectric material starts to vibrate and generates ultrasound waves. A portion of the ultrasound waves which passes through the medium will be sensed by the receiver and converted to electrical energy. To drive an ultrasound transducer, an excitation signal should be properly designed otherwise undesired signal (low quality) can deteriorate the performance of the transducer (energy conversion) and increase power consumption in the system. For instance, some portion of generated power may be delivered in unwanted frequency which is not acceptable for some applications especially for biomedical applications. To achieve better performance of the transducer, along with the quality of the excitation signal, the characteristics of the high power ultrasound transducer should be taken into consideration as well. In this regard, several simulation and experimental tests are carried out in this research to model high power ultrasound transducers and systems. During these experiments, high power ultrasound transducers are excited by several excitation signals with different amplitudes and frequencies, using a network analyser, a signal generator, a high power amplifier and a multilevel converter. Also, to analyse the behaviour of the ultrasound system, the voltage ratio of the system is measured in different tests. The voltage across transmitter is measured as an input voltage then divided by the output voltage which is measured across receiver. The results of the transducer characteristics and the ultrasound system behaviour are discussed in chapter 4 and 5 of this thesis. Each piezoelectric transducer has several resonance frequencies in which its impedance has lower magnitude as compared to non-resonance frequencies. Among these resonance frequencies, just at one of those frequencies, the magnitude of the impedance is minimum. This resonance frequency is known as the main resonance frequency of the transducer. To attain higher efficiency and deliver more power to the ultrasound system, the transducer is usually excited at the main resonance frequency. Therefore, it is important to find out this frequency and other resonance frequencies. Hereof, a frequency detection method is proposed in this research which is discussed in chapter 2. An extended electrical model of the ultrasound transducer with multiple resonance frequencies consists of several RLC legs in parallel with a capacitor. Each RLC leg represents one of the resonance frequencies of the ultrasound transducer. At resonance frequency the inductor reactance and capacitor reactance cancel out each other and the resistor of this leg represents power conversion of the system at that frequency. This concept is shown in simulation and test results presented in chapter 4. To excite a high power ultrasound transducer, a high power signal is required. Multilevel converters are usually applied to generate a high power signal but the drawback of this signal is low quality in comparison with a sinusoidal signal. In some applications like ultrasound, it is extensively important to generate a high quality signal. Several control and modulation techniques are introduced in different papers to control the output voltage of the multilevel converters. One of those techniques is harmonic elimination technique. In this technique, switching angles are chosen in such way to reduce harmonic contents in the output side. It is undeniable that increasing the number of the switching angles results in more harmonic reduction. But to have more switching angles, more output voltage levels are required which increase the number of components and cost of the converter. To improve the quality of the output voltage signal with no more components, a new harmonic elimination technique is proposed in this research. Based on this new technique, more variables (DC voltage levels and switching angles) are chosen to eliminate more low order harmonics compared to conventional harmonic elimination techniques. In conventional harmonic elimination method, DC voltage levels are same and only switching angles are calculated to eliminate harmonics. Therefore, the number of eliminated harmonic is limited by the number of switching cycles. In the proposed modulation technique, the switching angles and the DC voltage levels are calculated off-line to eliminate more harmonics. Therefore, the DC voltage levels are not equal and should be regulated. To achieve this aim, a DC/DC converter is applied to adjust the DC link voltages with several capacitors. The effect of the new harmonic elimination technique on the output quality of several single phase multilevel converters is explained in chapter 3 and 6 of this thesis. According to the electrical model of high power ultrasound transducer, this device can be modelled as parallel combinations of RLC legs with a main capacitor. The impedance diagram of the transducer in frequency domain shows it has capacitive characteristics in almost all frequencies. Therefore, using a voltage source converter to drive a high power ultrasound transducer can create significant leakage current through the transducer. It happens due to significant voltage stress (dv/dt) across the transducer. To remedy this problem, LC filters are applied in some applications. For some applications such as ultrasound, using a LC filter can deteriorate the performance of the transducer by changing its characteristics and displacing the resonance frequency of the transducer. For such a case a current source converter could be a suitable choice to overcome this problem. In this regard, a current source converter is implemented and applied to excite the high power ultrasound transducer. To control the output current and voltage, a hysteresis control and unipolar modulation are used respectively. The results of this test are explained in chapter 7.

Dissertação de Mestrado Integrado em Engenharia Electrotécnica e de Computadores apresentada à Faculdade de Ciências e Tecnologia da Universidade de Coimbra.<br>Nos últimos anos, o mundo tem assistido a um grande desenvolvimento tecnológico marcado sobretudo pela proliferação de sistemas informáticos e de accionamentos eléctricos. No entanto, a utilização massiva deste tipo de cargas, ditas não-lineares, acarreta grandes problemas no que toca à qualidade da energia eléctrica, criando uma elevada poluição harmónica. Na tentativa de minimizar estes efeitos nocivos surgiram os filtros activos de potência, tradicionalmente compostos por um conversor de 2 níveis. Porém, devido aos recentes desenvolvimentos nas topologias multinível, estas começaram a integrar os sistemas de filtragem, conferindo-lhes um melhor desempenho. Contudo, uma vez que é usado um maior número de semicondutores, a probabilidade de ocorrência de uma falha de circuito aberto ou de curto-circuito num deles aumenta consideravelmente. Deste modo, surge a necessidade de desenvolver estratégias que permitam identificar estas avarias e actuar imediatamente de forma a que o sistema possa permanecer em funcionamento. No seguimento desta problemática, na presente dissertação irão ser propostos métodos de diagnóstico e de tolerância a falhas para filtros activos de potência paralelos de 3 e 4 fios, baseados num conversor NPC de 3 níveis. A validade das técnicas apresentadas irá ser comprovada através de simulações computacionais e de ensaios experimentais.<br>In the past few years, the world has witnessed a great technological development, where the computer systems and the electric drives play an important role. However, the massive widespread of this so called non-linear loads brings many problems regarding the electric power quality, creating a high harmonic pollution. In order to mitigate this harmful effect, the active power filters have appeared, traditionally composed by a 2 level converter. Nevertheless, due to recent development of multilevel topologies, they are becoming to integrate these filtering systems, improving their performance. However, since it is needed a greater number of switching devices, the probability of an open circuit or a short-circuit failure in one of them is significantly higher. Thus, it is important to develop strategies to identify these faults and act immediately in order to keep the system operational. Then, in this dissertation will be proposed fault diagnosis and fault tolerance methods for 3 and 4 wire shunt active power filters, based on a 3 level NPC converter. The effectiveness of these techniques will be demonstrated by simulation and experimental results.

碩士<br>國立臺北科技大學<br>電機工程系碩士班<br>91<br>The main research of the thesis is based on Cell-based digital IC design flow, and use the TSMC 0.35um 1P4M cell library, to develop Space Vector Pulse Width Modulation（SVPWM）Control IC, and manufactured at S35_92C of the CIC’s advance chip. First , use the Hardware Description Language（VHDL）to encoding the system function, then use the compiler to make sure the syntax of the HDL is correct , after the Synthesis tool and auto place & routed tool and function simulation tool, make sure that every step is right, the design flow of the space vector modulation is complete. Not only can simulate the IC’s function expect software, but also can use Filed Programmable Gate Array（FPGA）as well. After complete the SVPWM control IC made use of Cell-based design flow, use the simulation tools, Modelsim and time-mill and power-mill, to simulate the RT level simulation and gate-level simulation and post-layout simulation of the control IC. We can find the conclusion in every level simulation, under the Cell-based IC Design flow, every function of the SVPWM control IC in this thesis, Sample rate control, Dead time control, Fundamental frequency control, Modulation control, and System Clock all correct. Then, use the FPGA to replace the design of SVPWM control IC , add the input signal control board made by myself , cooperated with the power driver and the induction motor of the three phase AC power, we can build a space vector modulation testing system. In the testing system, FPGA generates the control signal to drive the power driver successfully, and the power driver also makes the motor to rotate correctly. Under such multilevel simulation of the software and hardware simulation reality, all the design of the space vector pulse width modulation control IC in this thesis can movement correctly. So, this thesis make a motor control IC design flow successfully. In the future, the research will make the motor close-loop control system into IC under the same design flow, and combine the analog circuit, then the motor control IC of mixed signal is done, and also complete the final objective of this thesis.

碩士<br>中華大學<br>電機工程學系<br>107<br>This study is use the Space Vector Pulse Width Modulation Method for the Matrix Converter, the relationship between the input current and the output voltage at each output frequency and amplitude modulation is analyzed in detail under the space vector pulse width modulation method. Compare the output efficiency and total harmonic distortion (THD) of the input current and the output voltage, on the matrix converter at 120∘switching mode and 180∘switching mode.

Induction motors are thee starting point to design an electrical drivee system which is widely used in many industrial applications. Inn modern control theory, different mathematical models describe induction motor according to thee employed control methods. Vector control strategy can bee applied to this electrical motor type inn symmetrical three phase version or in unsymmetrical two phase version. The operation of the induction motor can be analyzed similar to a DC motor through this control method. With the Joint progress of thee power electronics and numerical electronics it is possible today to deal with thee axis control with variable speed inn low power applications. With these technological projections, various command approaches have been developed by the scientific community to master inn real time, thee flux and thee torque of thee electrical machines, thee indirect vector control (IVC) scheme being one of the most recent steps in this direction. This scheme provides excellent properties of regulation without rotational speed feedback. Inn this control scheme thee electromagnetic torque and stator flux magnitude are estimated with only stator voltages and currents and this estimation does not depend on motor parameters except for thee stator resistance. Inn this dissertation report conventional IVC scheme has been described. Induction motor has been simulated inn stationary d-q reference frame and its free acceleration characteristics are drawn. Conventional IVC scheme has been simulated with a 50 HP, 460V, 50Hz induction motor. Literature review has been done to study the recent improvements inn IVC scheme which somehow is abe to overcome the drawbacks of conventional one. Thee space vector modulation technique (SVPWM) is applied to 2 level inverter control inn thee vector control based induction motor drivee system, thereby dramatically reducing thee torque ripple. Later inn this project space vector PWM technique will be applied to IVC drivee system to reduce thee torque ripple.

碩士<br>國立雲林科技大學<br>電機工程技術研究所<br>87<br>This thesis discusses the design and implementation of the three phase induction motor drive system using a space-vector pulse-width-modulation (SVPWM) strategy based on a voltage-source inverter(VSI). A variable frequency, variable voltage converter is applied for the system control in induction motors. This thesis is separated in two sections. First section introduces the implementation of IGBT protection circuit. A gate voltage controlled protection circuit is proposed to cut off the high fault current within short-circuit withstand time(nearly 10 us). The proposed protection circuit features a simple circuit and no extra DC power supply, and provides good protection characteristics. A digital control inverter for a three-phase induction motor is discussed in the second section. The inverter with voltage/frequency (V/F) control was developed and implemented on a TMS320F240 DSP-based platform. The SVPWM strategy is applied for the control of inverter to reduce the voltage and current harmonics in the inverter output and consequently provide a smooth operation of the induction motor. The proposed SVPWM algorithm is discussed. Results of analytical and experimental investigation provide a guideline for the design and improvement of V/F control method used in induction motor drives.

碩士<br>國立雲林科技大學<br>電機工程技術研究所<br>86<br>The synchronous reluctance motor(SRM) has the simple structure, easy controllability, no slip, and rotor without permanent magnets which has the advantages both of induction motor and brushless motor. Under the rising growth of power electron and powerful calculation of microprocessors, the AC motors have increasingly disentangled from the conventional analog controller, and develop toward the half-digital or full-digital controller. This thesis proposes a DSP based, variable speed system of synchronous reluctance motor. First, the construction, characteristics, mathematical model, and the nowaday control strategies of synchronous reluctance motor are studied. Second, a three phase inverter and their peripheral control circuit are finished. The space vector pulse width modulation method was applied. For improving the SRM low torque flaw, the maximum torque strategies was adopted. Finally, a quasilinear fuzzy control strategy is introdud to investigate the try and error spot of conventional speed controller and to improve transient response performance of whole closed system.

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

碩士<br>國立臺北科技大學<br>電機工程系碩士班<br>92<br>In this thesis, the research of the Space Vector Pulse Width Modulation Control IC embedded with V/F Control Curves is presented. This research is implemented by Cell-based IC design flow with TSMC .35um 2P4M process. First, the function of the system is programming in VHDL. Then, we use the compiler to confirm the syntax of the VHDL code. After that, the synthesis tool, auto place & routed and function simulation tool are used to implement the Space Vector Pulse Width Modulation Control IC. After the Space Vector Pulse Width Modulation Control IC with V/F Control Curves is implemented, we use the software ModelSim, Time Mill and Power Mill to simulate the RT Level, Gate Level, and Post Layout Simulation. In conclusion, the research of the Space Vector Pulse Width Modulation Control IC embedded with V/F Control Curves in this paper includes many functions. It consists of Direct control, Speed control, V/F control, Sample rate control, Dead time control, and System Clock. And all functions work.

碩士<br>國立彰化師範大學<br>電機工程學系<br>100<br>Space vector pulse width modulation(SVPWM) is widely used in recent permanent magnet synchronous motor drive strategies because of the advantages of high dc-link utilization and low harmonic distortion. However, the required calculation capability of microcontroller is much higher due to the complex calculation of SVPWM. Therefore, in the practical application, a 16-bit or 32-bit micro controller is usually adopted. However, when PMSM drives are used for applications where high dynamic performance is not a demand, a 8-bit micro controller can support the calculation of SVPWM. In this thesis, a 8-bit micro controller is adapted as the central control unit of the permanent magnet synchronous motor drive. The calculation of SVPWM is carried out with look up table. Also, hall sensors are used to feed back the rotor position for driving the permanent magnet synchronous motor. Finally, a prototype drive with 24V/100W and 3000 rpm rated speed is constructed. Corresponding experiments are carried out validity of the proposed drive system.

碩士<br>國立中正大學<br>電機工程研究所<br>107<br>The main objective of this thesis is to develop Takagi-Sugeno (T-S) fuzzy controls of the permanent-magnet synchronous generator (PMSG) based on space- vector pulse width modulation (SVPWM). T-S fuzzy control is suitable for nonlinear system control. A nonlinear system is represented by several linear sub-systems. And the controller is designed based on parallel distributed compensation (PDC). In system configuration, a permanent-magnet synchronous motor (PMSM) is established as the prime mover to drive the PMSG. Encoder signals are utilized to calculate the rotor position and rotor speed. The winding currents of the PMSG are feedback through analog-to-digital converter (ADC) into the microcontroller. The corresponding duty ratios of power switches are calculated via the designed T-S fuzzy controller and used to drive six switches through driving circuits. The AC power of the PMSG is converted to DC power by three-phase three-wire inverter. First, SVPWM is utilized to derive state equations of the PMSG in each section. Traditional d-q frame transformation is unnecessary. Then the T-S fuzzy controller is designed and its stability is analyzed. Next, the controller gain is obtained from linear matrix inequality (LMI) and implemented to determine the corresponding duty ratios. Finally, the feasibility of the proposed T-S fuzzy control is verified by experimental results.

碩士<br>國立中正大學<br>電機工程研究所<br>107<br>The main purpose of this thesis is to design and implement Takagi-Sugeno (T-S) fuzzy controls of the three-phase bidirectional inverter based on space-vector pulse width modulation (SVPWM). The developed three-phase bidirectional inverter can be applied to micro-grid systems. Its operation modes include grid-connected mode and rectification mode. The switching type is based on SVPWM. Three-phase currents are divided into six sections. First, state equations are derived from equivalent circuits of inverter according to six sections. The current tracking capability is achieved by adding error integral terms. T-S fuzzy controller is designed on the concept of parallel distributed compensation (PDC). Stability of the T-S fuzzy control system is also analyzed. Next, the controller gain is obtained by Linear Matrix Inequality (LMI) to determine duty ratios of power switches in the inverter. Therefore, the objective of current control can be achieved. The control unit of three-phase bidirectional inverter is the microcontroller Renesas RX62T. Voltage and current signals are captured as feedback into the microcontroller. The duty ratios of switches are calculated via T-S fuzzy controller and utilized to drive six switches. Finally, the inverter performance in grid-connected mode and rectification mode is verified by experimental results.

Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives.<br>Power Engineering and Power Electronics

Experimental research on high-power converters, particularly in an academic environment, faces severe infrastructural constraints. Usually, power source and loads of required ratings are not available. Further, more importantly, the energy consumption is huge. One possibility is to establish an experimental research platform, comprising of a network of high-power converters, through which power is circulated and which draws only the losses from the mains. This work deals with the establishment of a circulating power test set-up, comprising of two line-side PWM converters, inclusive of control and modulation methods for the two converters. Two types of circulating power test setups are developed. In the first setup, the converters are connected in parallel, on ac as well as dc sides, such that real and/or reactive power is circulated between them. In the second test setup, the dc buses of the converters are separated; hence, only reactive power circulation is possible. These setups are used to conduct heat-run tests with low energy expenditure on the PWM converters at various operating conditions up to power levels of 150 kVA. Further, these are used to validate analytically-evaluated thermal characteristics of high-power PWM converters. A safe thermal limit is derived for such converters in terms of apparent power (kVA) handled, power factor and switching frequency. The effects of voltage sag and of unequal current sharing between parallel IGBT modules on the safe thermal limit are studied. While the power drawn by the circulating-power setup from the grid is much lower than the ratings of the individual converters, the harmonic injection into the mains by the setup could be significant since the harmonics drawn by both converters tend to add up. This thesis investigates carrier interleaving to improve the waveform quality of grid current, drawn by the circulating-power test setup. The study of carrier interleaving is quite general and covers various applications of parallel-connected converters such as unity power factor rectification, static reactive power compensation and grid-connected renewable energy systems. In literature, carrier interleaving has been employed mainly for unity power factor rectifiers, sharing a common dc load equally. In such case, the fundamental components of the terminal voltages of the parallel converters are equal. However, when the power sharing between the two converters is unequal, or when power is circulated between the two converters, the terminal voltages of the two converters are not equal. A method to estimate rms grid current ripple, drawn by parallel-connected converters with equal and/or unequal terminal voltages, in a synchronous reference frame is presented. Further, the influence of carrier interleaving on the rms grid current ripple is studied. The optimum interleaving angle, which minimizes the rms grid current ripple under various applications, is investigated. This angle is found to be a function of modulation index of the converters in the equal terminal voltages case. In the unequal terminal voltages case, the optimum interleaving angle is shown to be a function of the average modulation index of the two parallel converters. The effect of carrier interleaving is experimentally studied on the reactive power circulation setup at different values of kVA and different dc bus voltages. The grid current ripple is measured for different values of interleaving angle. It is found experimentally that the optimum interleaving angle reduces the rms grid current ripple by between 37% and 48%, as compared without interleaving, at various operating conditions. Further, the reactive power circulation test set-up is used to evaluate and compare power conversion losses corresponding to different PWM techniques such as conventional space-vector PWM (CSVPWM), bus-clamping PWM (BCPWM) and advanced bus-clamping PWM methods for static reactive power compensator (STATCOM) application at high power levels. It is demonstrated theoretically as well as experimentally that an advanced bus-clamping PWM method, termed minimum switching loss PWM (MSLPWM), leads to significantly lower power conversion loss than CSVPWM and BCPWM techniques at a given average switching frequency.

Experimental research on high-power converters, particularly in an academic environment, faces severe infrastructural constraints. Usually, power source and loads of required ratings are not available. Further, more importantly, the energy consumption is huge. One possibility is to establish an experimental research platform, comprising of a network of high-power converters, through which power is circulated and which draws only the losses from the mains. This work deals with the establishment of a circulating power test set-up, comprising of two line-side PWM converters, inclusive of control and modulation methods for the two converters. Two types of circulating power test setups are developed. In the first setup, the converters are connected in parallel, on ac as well as dc sides, such that real and/or reactive power is circulated between them. In the second test setup, the dc buses of the converters are separated; hence, only reactive power circulation is possible. These setups are used to conduct heat-run tests with low energy expenditure on the PWM converters at various operating conditions up to power levels of 150 kVA. Further, these are used to validate analytically-evaluated thermal characteristics of high-power PWM converters. A safe thermal limit is derived for such converters in terms of apparent power (kVA) handled, power factor and switching frequency. The effects of voltage sag and of unequal current sharing between parallel IGBT modules on the safe thermal limit are studied. While the power drawn by the circulating-power setup from the grid is much lower than the ratings of the individual converters, the harmonic injection into the mains by the setup could be significant since the harmonics drawn by both converters tend to add up. This thesis investigates carrier interleaving to improve the waveform quality of grid current, drawn by the circulating-power test setup. The study of carrier interleaving is quite general and covers various applications of parallel-connected converters such as unity power factor rectification, static reactive power compensation and grid-connected renewable energy systems. In literature, carrier interleaving has been employed mainly for unity power factor rectifiers, sharing a common dc load equally. In such case, the fundamental components of the terminal voltages of the parallel converters are equal. However, when the power sharing between the two converters is unequal, or when power is circulated between the two converters, the terminal voltages of the two converters are not equal. A method to estimate rms grid current ripple, drawn by parallel-connected converters with equal and/or unequal terminal voltages, in a synchronous reference frame is presented. Further, the influence of carrier interleaving on the rms grid current ripple is studied. The optimum interleaving angle, which minimizes the rms grid current ripple under various applications, is investigated. This angle is found to be a function of modulation index of the converters in the equal terminal voltages case. In the unequal terminal voltages case, the optimum interleaving angle is shown to be a function of the average modulation index of the two parallel converters. The effect of carrier interleaving is experimentally studied on the reactive power circulation setup at different values of kVA and different dc bus voltages. The grid current ripple is measured for different values of interleaving angle. It is found experimentally that the optimum interleaving angle reduces the rms grid current ripple by between 37% and 48%, as compared without interleaving, at various operating conditions. Further, the reactive power circulation test set-up is used to evaluate and compare power conversion losses corresponding to different PWM techniques such as conventional space-vector PWM (CSVPWM), bus-clamping PWM (BCPWM) and advanced bus-clamping PWM methods for static reactive power compensator (STATCOM) application at high power levels. It is demonstrated theoretically as well as experimentally that an advanced bus-clamping PWM method, termed minimum switching loss PWM (MSLPWM), leads to significantly lower power conversion loss than CSVPWM and BCPWM techniques at a given average switching frequency.

Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor. The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss. Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination. Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures. A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents. Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter. A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions. Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.