Dissertations / Theses on the topic 'Space vector PWM'

In recent years, research in the area of multiphase drives has increased significantly. Having higher number of machine phases allows the current to be shared between the phases, thus reducing the current rating of power semiconductors used in the power converter. Additionally, if a multilevel inverter is used to drive the machine, the output voltage waveforms are going to be approximated closer toward sinusoidal waveforms, thus resulting in lower total harmonic distortion. Therefore, the combination of multiphase and multilevel technologies gives considerable benefits compared to conventional two-level three-phase drives. Unlike a carrier-based approach, which can be easily expanded to any number of converter voltage levels and any number of machine phases, the development of space vector algorithms is also reliant on the machine’s configuration. In other words, different drive topologies require their own unique space vector algorithms. In fact, the complexity of developing a space vector algorithm will dramatically increase with the increase of number of levels and/or number of phases. This thesis presents pulse width modulation techniques for two- and three-level asymmetrical and symmetrical six-phase drives with a single or two isolated neutral points configuration. However, since the modulation techniques for the drives with two isolated neutral points are based on the well-established modulation techniques for three-phase drives, more emphasis is given towards the development of modulation techniques for single neutral point case, particularly those that are based on space vector algorithm principles. In order to realise sinusoidal output phase voltage waveforms, several requirements and conditions have to be met. The requirements revolve around ensuring that the low order harmonics, which contribute to the machine losses, will not exist. Meanwhile, the conditions are more towards minimising the switching losses. All modulation techniques are verified through simulation, while those for three-level case are validated experimentally as well. Comparison and discussion of obtained simulation and experimental results, performance and complexity in terms of execution time of the developed modulation techniques, are presented. The equivalence between corresponding modulation techniques, which are based on the space vector algorithm and carrier-based approach are also established.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

The dissertation documents research work carried out on Pulse Width Modulation (PWM) strategies for hard switched Voltage Source Inverters (VSI) for variable speed electric drives. This research is aimed at Hybrid Electric Vehicles (HEV). PWM is at the heart of all variable speed electric drives; they have a huge influence on the overall performance of the system and may also help eventually give us an extra degree of freedom in the possibility to rethink the inverter design including the re-dimensioning of the inverter components.HEVs tend to cost more than conventional internal combustion engine (ICE) vehicles as they have to incorporate two traction systems, which is the major discouraging factor for consumers and in turn for manufacturers. The two traction system increases the maintenance cost of the car as well. In addition the electric drives not only cost extra money but space too, which is already scarce with an ICE under the hood. An all-electric car is not yet a viable idea as the batteries have very low energy density compared with petrol or diesel and take considerable time to charge. One solution could be to use bigger battery packs but these add substantially to the price and weight of the vehicle and are not economically viable. To avoid raising the cost of such vehicles to unreasonably high amounts, autonomy has to be compromised. However hybrid vehicles are an important step forward in the transition toward all-electric cars while research on better batteries evolves. The objective of this research is to make electric drives suitable for HEVs i.e. lighter, more compact and more efficient -- requiring less maintenance and eventually at lower cost so that the advantages, such as low emissions and better fuel efficiency, would out-weigh a little extra cost for these cars. The electrical energy source in a vehicle is a battery, a DC Voltage source, and the traction motor is generally an AC motor owing to the various advantages it offers over a DC motor. Hence the need for a VSI, which is used to transform the DC voltage into AC voltage of desired amplitude and frequency. Pulse width modulation techniques are used to control VSI to ensure that the required/calculated voltage is fed to the machine, to produce the desired torque/speed. PWM techniques are essentially open loop systems where no feedback is used and the instantaneous values differ from the required voltage, however the same average values are obtained. Pulse width modulated techniques produce a low frequency signal (desired average value of the switched voltage) also called the fundamental component, along with unwanted high frequency harmonics linked to the carrier signal frequency or the PWM period. In modern cars we see more and more mechanical loads driven by electricity through digital processors. It is very important to eliminate the risk of electromagnetic interference between these systems to avoid failure or malfunction. Hence these unwanted harmonics have to be filtered so that they do not affect the electronic control unit or other susceptible components placed in the vicinity. Randomised modulation techniques (RPWM) are used to dither these harmonics at the switching frequency and its multiple. In this thesis a random modulator based on space vector modulation is presented which has additional advantages of SVM. Another EMI problem linked to PWM techniques is that they produce common mode voltages in the load. For electric machines, common mode voltage produces shaft voltage which in turn provokes dielectric stress on the motor bearings, its lubricant and hence the possibility of generating bearing currents in the machine that can be fatal for the machine. To reduce the common mode voltage a space vector modulation strategy is developed based on intelligent placement of zero vectors. (...)

Variable speed drive technology has advanced dramatically in the last 10 years with the advent of new power devices. In this study, a three phase induction motor drive using Insulated Gate Bipolar Transistors (IGBT) at the inverter power stage is introduced to implement speed and position control for the revolving stage in the Frederic Wood Theatre This thesis presents a solution to control a 3-phase induction motor using the Texas Instruments (TI) Digital Signal Processor (DSP) TMS320F2407A. The use of this DSP yields enhanced operations, fewer system components, lower system cost and increased efficiency. The control algorithm is based on the constant volts-per-hertz principle because the exact speed control is not needed. Reflective object sensors which are mounted on concrete frame are used to detect accurate edge position of revolving stage. The sinusoidal voltage waveforms are generated by the DSP using the space vector modulation technique. In order to satisfy some operating conditions for safe and agreeable operation, a look-up table, which is used to give command voltage and speed signals in software, is applied to limit the maximum speed and acceleration of the revolving stage. Meanwhile, a boost voltage signal is added at the low frequency areas to make the motor produce maximum output torque when starting. A test prototype is then built to validate the performance. Several tests are implemented into the IGBT drive to explore the reason for unacceptable oscillations in IGBT’s gate control signals. Improvement methods in hardware layout are suggested for the final design.

La present tesi doctoral estudia els inversors trifàsics multinivell del tipus denominat de díodes de fixació (diode-clamped converters). Aquests convertidors poden generar tres o més nivells de tensió a cada fase de sortida, i normalment s'apliquen a sistemes de gran potència ja que poden treballar amb tensions majors que els inversors clàssics. L'anàlisi es centra fonamentalment en la topologia de tres nivells, tot i que també es realitzen contribucions per a convertidors de més nivells. Els principals objectius són la proposta de nous algorismes de modulació vectorial PWM de processat ràpid, l'estudi i la compensació dels efectes dels desequilibris de les tensions dels condensadors del bus de continua, i l'anàlisi de llaços de control avançat.
S'han desenvolupat diversos models que han permès obtenir resultats de simulació de les tècniques de modulació i control proposades. A més, gràcies a l'estada d'un any de l'autor al Center for Power Electronics Systems (CPES) a Virginia Tech, USA, la tesi també inclou resultats experimentals que consoliden les conclusions i metodologies presentades. Les principals contribucions es resumeixen a continuació.
Es presenta un nou algorisme de modulació vectorial PWM que aprofita simetries del diagrama vectorial per a reduir el temps de processat. S'analitzen i es quantifiquen les oscil·lacions de tensió de baixa freqüència que apareixen en el punt central dels condensadors del convertidor de tres nivells. Aquesta informació permet dimensionar els condensadors donades les especificacions d'una determinada aplicació.
L'algorisme de modulació també s'aplica a convertidors de més nivells. Pel cas concret del convertidor de quatre nivells, es comprova l'existència de corrents continus en els punts mitjos dels condensadors que fan que els sistema sigui inestable. Es determinen gràficament les zones d'inestabilitat.
Es presenta un nou i eficient algorisme de modulació vectorial feedforward en el convertidor de tres nivells que és capaç de generar tensions trifàsiques de sortida equilibrades, malgrat l'existència de desequilibris en les tensions dels condensadors.
S'estudien els efectes negatius de càrregues lineals desequilibrades i càrregues no lineals en el control de les tensions dels condensadors. Es justifica que l'existència d'un quart harmònic en els corrents de càrrega pot inestabilitzar el sistema. És determina la màxima amplitud tolerable d'aquest harmònic.
S'estudia la millora en l'equilibrat de les tensions d'una connexió de dos convertidors de tres nivells al mateix bus de continua (back-to-back connection). Un exemple d'aplicació pràctica és la conversió AC/DC/AC per a l'accionament de motors d'alterna treballant amb factor de potència unitari.
Finalment s'aplica un controlador òptim al convertidor de tres nivells treballant com a rectificador elevador (boost). El llaç de control LQR (Linear Quadratic Regulator) es simplifica donat que la tasca d'equilibrat de les tensions dels condensadors es dur a terme en el mateix modulador.

The study designs and constructs a three-phase to three-phase direct AC&ndash
AC matrix converter based surface mounted permanent magnet synchronous motor (PMSM) drive system. First, the matrix converter topologies are analyzed and the state-space equations describing the system have been derived in terms of the input and output variables. After that, matrix converter commutation and modulation methods are investigated. A four-step commutation technique based on output current direction provides safe commutation between the matrix converter switches. Then, the matrix converter is simulated for both the open-loop and the closed-loop control. For the closed-loop control, a current regulator (PI controller) controls the output currents and their phase angles. Advanced pulse width modulation and control techniques, such as space vector pulse width modulation and field oriented control, have been used for the closed-loop control of the system. Next, a model of diode-rectified two-level voltage source inverter is developed for simulations. A comparative study of indirect space vector modulated direct matrix converter and space vector modulated diode-rectified two-level voltage source inverter is given in terms of input/output waveforms to verify that the matrix converter fulfills the two-level voltage source inverter operation. Following the verification of matrix converter operation comparing with the diode-rectified two-level voltage source inverter, the simulation model of permanent magnet motor drive system is implemented. Also, a direct matrix converter prototype is constructed for experimental verifications of the results. As a first step in experimental works, filter types are investigated and a three-phase input filter is constructed to reduce the harmonic pollution. Then, direct matrix converter power circuitry and gate-driver circuitry are designed and constructed. To control the matrix switches, the control algorithm is implemented using a DSP and a FPGA. This digital control system measures the output currents and the input voltages with the aid of sensors and controls the matrix converter switches to produce the required PWM pattern to synthesize the reference input current and output voltage vectors, as well. Finally, the simulation results are tested and supported by laboratory experiments involving both an R-L load and a permanent magnet synchronous motor load. During the tests, the line-to-line supply voltage is set to 26 V peak value and a 400 V/3.5 kW surface mounted permanent magnet motor is used.

Orientador: Dionizio Paschoareli Junior
Banca: Falcondes Jose Mendes de Seixas
Banca: Hari Bruno Mohr
Resumo: A tendência dos sistemas de energia elétrica é uma operação cada vez mais próxima de seus limites operacionais. A presença de equipamentos que utilizam a eletrônica de potência, no controle e condicionamento da energia, é cada vez mais freqüente. A utilização de conversores como fonte de tensão, associados a elementos armazenadores de energia como, por exemplo, a bateria de sódio-enxofre, com alta densidade de energia, alta eficiência na carga e descarga e ainda um longo ciclo de vida, é a configuração básica de um Compensador Regenerativo de Potência Ativa. Compensação regenerativa de potência é um conceito que permite o armazenamento de energia em períodos favoráveis sob o ponto de vista dos custos da energia elétrica. Este conceito de compensação baseia-se no armazenamento da energia excedente ao longo do dia, nos períodos de menor tarifação, para utilizá-la nos horários de ponta (sobre-tarifa), aproveitando-se as vantagens contratuais de consumo de energia fora de ponta e promovendo-se uma melhor equalização de consumo, permitindo uma redução no contrato de demanda. Portanto, na compensação regenerativa de potência ativa, os períodos de consumo de energia são deslocados, com o objetivo de se obter redução na tarifa. Este conceito mostra-se interessante em sistemas com tarifação do tipo horo-sazonal, como é o caso brasileiro. Com o objetivo de se verificar tal troca de potência ativa, um modelo trifásico foi implementado e simulado. Os controles da potência ativa trocada entre o compensador e o sistema e da tensão na barra na qual o mesmo está instalado são realizados independentes e por controladores do tipo PID. Os sinais de controle dos interruptores semicondutores que compõe o conversor como fonte de tensão são gerados a partir do DSP TMS320F2808 da Texas Instruments, o que está embarcado no módulo didático eZdsp F2808 da Spectrum Digital
Abstract: Nowadays, electric power systems are expected to work closer to their operating limits. Power electronics based controllers, such as voltage sourced converters, are increasingly present in power systems. Electronic devices are often used to energy controlling and conditioning. The use of voltage sourced converters, associated to high-density storage elements, is the basic configuration of a Regenerative Active Power Compensator. Regenerative Active Power Compensator is a concept which proposes the energy storage as a possibility for revaluation of electrical energy cost with demand contracts. This concept is based on storing energy surplus during off peak periods, when the energy cost is cheaper, and injecting it back to the system during the overpriced peak periods. This procedure allows a better equalization of energy consumption and a reduction in electric power demand contracts. Therefore, using regenerative active power compensation, the consumption is dislocated from peak periods, resulting in a reduction of energy costs for the consumer. This concept is especially attractive for countries that use hour-seasonal fees police, as in the Brazilian case. This work proposes a three-phase model simulation with digital signal processor controller to investigate the active power flow control between the power system and the compensator, using a proportional-integral-derivative control strategy. The control signals are generate using the Texas Instruments DSP TMS320F2808, witch is embedded into the eZdsp F2808 didactic module, from Spectrum Digital
Mestre

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

Distributed generation (DG) with a converter interface to the power grid is found in many of the green power resources applications. This dissertation describes a multi-objective control technique of voltage source converter (VSC) based on multilevel converter topologies, for integration of DG resources based on renewable energy (and non-renewable energy)to the power grid. The aims have been set to maintain a stable operation of the power grid, in case of di erent types of grid-connected loads. The proposed method provides compensation for active, reactive, and harmonic load current components. A proportional-integral (PI) control law is derived through linearization of the inherently non-linear DG system model, so that the tasks of current control dynamics and dc capacitor voltage dynamics become decoupled. This decoupling allows us to control the DG output currents and the dc bus voltage independently of each other, thereby providing either one of these decoupled subsystems a dynamic response that signi cantly slower than that of the other. To overcome the drawbacks of the conventional method, a computational control delay compensation method, which delaylessly and accurately generates the DG reference currents, is proposed. The rst step is to extract the DG reference currents from the sensed load currents by applying the stationary reference frame and then transferred into synchronous reference frame method, and then, the reference currents are modi ed, so that the delay will be compensated. The transformed variables are used in control of the multilevel voltage source converter as the heart of the interfacing system between DG resources and power grid. By setting appropriate compensation current references from the sensed load currents in control circuit loop of DG link, the active, reactive, and harmonic load current components will be compensated with fast dynamic response, thereby achieving sinusoidal grid currents in phase with load voltages while required power of loads is more than the maximum injected power of the DG resources. The converter, which is controlled by the described control strategy, guarantees maximum injection of active power to the grid continuously, unity displacement power factor of power grid, and reduced harmonic load currents in the common coupling point. In addition, high current overshoot does not exist during connection of DG link to the power grid, and the proposed integration strategy is insensitive to grid overload.
La Generació Distribuïda (DG) injectada a la xarxa amb un convertidor estàtic és una solució molt freqüent en l'ús de molts dels recursos renovables. Aquesta tesis descriu una técnica de control multi-objectiu del convertidor en font de tensió (VSC), basat en les topologies de convertidor multinivell, per a la integració de les fonts distribuïdes basades en energies renovables i també de no renovables.Els objectius fixats van encaminats a mantenir un funcionament estable de la xarxa elèctrica en el cas de la connexió de diferents tipus de càrregues. El mètode de control proposat ofereix la possibilitat de compensació de les components actives i reactives de la potencia, i les components harmòniques del corrent consumit per les càrregues.La llei de control proporcional-Integral (PI) s’obté de la linearització del model inherentment no lineal del sistema, de forma que el problema de control del corrent injectat i de la tensió d’entrada del convertidor queden desacoblats. Aquest desacoblament permet el control dels corrents de sortida i la tensió del bus de forma independent, però amb un d’ells amb una dinàmica inferior.Per superar els inconvenients del mètode convencional, s’usa un retard computacional, que genera les senyals de referència de forma acurada i sense retard. El primer pas es calcular els corrents de referència a partir de les mesures de corrent. Aquest càlcul es fa primer transformant les mesures a la referència estacionaria per després transformar aquests valors a la referència síncrona. En aquest punt es on es poden compensar els retards.Les variables transformades son usades en els llaços de control del convertidor multinivell. Mitjançant aquests llaços de control i les referències adequades, el convertidor és capaç de compensar la potencia activa, reactiva i els corrents harmònics de la càrrega amb una elevada resposta dinàmica, obtenint uns corrents de la xarxa de forma completament sinusoïdal, i en fase amb les tensions.El convertidor, controlat amb el mètode descrit, garanteix la màxima injecció de la potencia activa, la injecció de la potencia reactiva per compensar el factor de potencia de la càrrega, i la reducció de les components harmòniques dels corrents consumits per la càrrega. A més, garanteix una connexió suau entre la font d’energia i la xarxa. El sistema proposat es insensible en front de la sobrecarrega de la xarxa

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
A tendência dos sistemas de energia elétrica é uma operação cada vez mais próxima de seus limites operacionais. A presença de equipamentos que utilizam a eletrônica de potência, no controle e condicionamento da energia, é cada vez mais freqüente. A utilização de conversores como fonte de tensão, associados a elementos armazenadores de energia como, por exemplo, a bateria de sódio-enxofre, com alta densidade de energia, alta eficiência na carga e descarga e ainda um longo ciclo de vida, é a configuração básica de um Compensador Regenerativo de Potência Ativa. Compensação regenerativa de potência é um conceito que permite o armazenamento de energia em períodos favoráveis sob o ponto de vista dos custos da energia elétrica. Este conceito de compensação baseia-se no armazenamento da energia excedente ao longo do dia, nos períodos de menor tarifação, para utilizá-la nos horários de ponta (sobre-tarifa), aproveitando-se as vantagens contratuais de consumo de energia fora de ponta e promovendo-se uma melhor equalização de consumo, permitindo uma redução no contrato de demanda. Portanto, na compensação regenerativa de potência ativa, os períodos de consumo de energia são deslocados, com o objetivo de se obter redução na tarifa. Este conceito mostra-se interessante em sistemas com tarifação do tipo horo-sazonal, como é o caso brasileiro. Com o objetivo de se verificar tal troca de potência ativa, um modelo trifásico foi implementado e simulado. Os controles da potência ativa trocada entre o compensador e o sistema e da tensão na barra na qual o mesmo está instalado são realizados independentes e por controladores do tipo PID. Os sinais de controle dos interruptores semicondutores que compõe o conversor como fonte de tensão são gerados a partir do DSP TMS320F2808 da Texas Instruments, o que está embarcado no módulo didático eZdsp F2808 da Spectrum Digital
Nowadays, electric power systems are expected to work closer to their operating limits. Power electronics based controllers, such as voltage sourced converters, are increasingly present in power systems. Electronic devices are often used to energy controlling and conditioning. The use of voltage sourced converters, associated to high-density storage elements, is the basic configuration of a Regenerative Active Power Compensator. Regenerative Active Power Compensator is a concept which proposes the energy storage as a possibility for revaluation of electrical energy cost with demand contracts. This concept is based on storing energy surplus during off peak periods, when the energy cost is cheaper, and injecting it back to the system during the overpriced peak periods. This procedure allows a better equalization of energy consumption and a reduction in electric power demand contracts. Therefore, using regenerative active power compensation, the consumption is dislocated from peak periods, resulting in a reduction of energy costs for the consumer. This concept is especially attractive for countries that use hour-seasonal fees police, as in the Brazilian case. This work proposes a three-phase model simulation with digital signal processor controller to investigate the active power flow control between the power system and the compensator, using a proportional-integral-derivative control strategy. The control signals are generate using the Texas Instruments DSP TMS320F2808, witch is embedded into the eZdsp F2808 didactic module, from Spectrum Digital

In conventional three-phase PWM (Pulse Width Modulation) current source converter based STATCOM (Static Synchronous Compensator) applications, DC link current is kept constant at a predefined value and the reactive power of STATCOM is controlled by varying modulation index. This control strategy causes unnecessary power losses especially when the reactive power of STATCOM is low. For this purpose, in order to reduce the active power drawn by STATCOM, the modulation index can be maximized by adjusting DC link current. Within the scope of this thesis, an adaptive control of DC link current will be designed and applied to a 0.4kV 50kVAr three phase current source converter based STATCOM so that the power losses can be reduced. The theoretical work will be compared and discussed with the experimental results.

In this thesis, the neutral point potential drift/fluctuation of the three-level neutral point clamped inverter is analyzed and a novel control algorithm, the two-parameter PWM method is proposed to confine the neutral point potential variation to a very small range. The two-parameter PWM method provides superior neutral point potential control performance even with small DC bus capacitors. The method is based on PWM pulse pattern modification and requires no additional hardware. Detailed analytical models of the neutral point current and potential as a function of the modulation parameters are established and the neutral point potential behavior is thoroughly investigated. Based on the study, the deficiency of the known methods is illustrated and the two-parameter PWM method is developed and its superior performance demonstrated. The performance of the two-parameter PWM method is verified by means of computer simulations utilizing both the per-PWM-cycle average model and the detailed model of the inverter. The results are supported by laboratory experiments involving both an R-L load and an induction motor drive.

A systematic and versatile method to derive accurate and efficient Circuit Oriented Large Signal Average Models (COLSAMs) that approximate the slow dynamics manifold of the moving average values of the relevant state variables for Pulse-Width Modulated (PWM) dc to dc and three-phase to dc power converters is developed. These COLSAMs can cover continuous conduction mode (CCM) as well as discontinuous conduction mode (DCM) of operation and they are over one order of magnitude cheaper, computation wise, than the switching models. This method leads primarily to simple and effective input-output oriented models that represent transfer as well as loading characteristics of the converter. Sine these models consist of time invariant continuous functions they can be linearized at an operating point in order to obtain small-signal transfer functions that approximate the dynamics of the original PWM system around an orbit. The models are primarily intended for software circuit simulators (i.e. Spice derived types, Saber, Simplorer, etc), to take advantage of intrinsic features such as transient response, linearization, transfer function, harmonic distortion calculations, without having to change simulation environment. Nevertheless, any mathematics simulator for ordinary differential equations can be used with the set of equations obtained through application of Kirchoff's laws to the COLSAMs. Furthermore, the COLSAMs provide physical insight to help with power stage and control design, and they allow easy interconnection among themselves, as well as with switching models, for complete analysis at different scales (time, signal level, complexity; interconnectivity). A new average model for the Zero-Voltage Switched Full-Bridge (ZVS-FB) PWM Converter is developed with the above method and its high accuracy is verified with simulations from a switching behavioral model for several circuit component values for both CCM and DCM. Intrinsic positive damping effects and special delay characteristics created by an energy holding element in a saturable reactor-based Zero-Voltage Zero-Current Switched Full-Bridge (ZVZCS-FB) PWM converter are explained for the first time by a new average model. Its large signal predictions match very well those from switch model simulations whereas its small-signal predictions are verified with experimental results from 3.5 kW prototype modules. The latter are used in a multi-module converter to supply the DC power bus in and aircraft. The design of control loops for the converter is based on the new model and its linearization. The ZVZCS-FB PWM converter's average model above is extended to deal with interconnection issues and constraints in a Quasi-Single Stage (QSS) Zero-Voltage Zero-Current Switched (ZVZCS) Three-Phase Buck Rectifier. The new model reveals strong nonlinear transfer characteristics for standard Space Vector Modulation (SVM), which lead to high input current distortion and output voltage ripple inadmissible in telecommunications applications. Physical insight provided by this average model led to the development of a combined modified SVM and feed-forward duty-cycle compensation scheme to reliably minimize the output voltage ripple. Experimental results from a 6 kW prototype validate large signal model for standard and modified SVM, with and without duty-cycle compensation scheme.
Ph. D.

L’impact des stratégies Modulation de Largeur d'Impulsion (MLI) sur les sollicitations des condensateurs de découplage en entrée d’un onduleur triphasé est bien connu à l’heure actuelle au même titre que le comportement de la charge alimentée (facteur de puissance). On dispose à l’heure actuelle d’un large panel de techniques de modulation applicables en fonction des diverses contraintes d’environnement (stress des condensateurs mais aussi qualité des courants dans la charge ou pertes par commutation dans les semi-conducteurs). Toutefois, dans de nombreux contextes applicatifs, le bus continu peut être mutualisé entre plusieurs convertisseurs qui vont solliciter individuellement le ou les condensateurs de découplage. L’objectif de cette thèse est d'étudier la mise en œuvre des stratégies MLI coordonnées entre plusieurs onduleurs mutualisant leur bus continu. Plus précisément, une étude du cas des convertisseurs back-to-back dans le cas de MADA a été faite. De plus, cette étude vise à évaluer l'impact de stratégies MLI entrelacées sur le courant efficace traversant le condensateur de découplage associé à deux convertisseurs en parallèle. En effet, cette valeur est généralement le paramètre clé pour le dimensionnement de ce (ou ces) composant(s), bien au-delà de la capacité, notamment pour les condensateurs électrolytiques à l'aluminium. La technique d'entrelacement est appliquée selon deux stratégies différentes : - La stratégie classique SVPWM ; - La stratégie MLI à double porteuse unifié (Uni-DCPWM) qui est dédié à la réduction du courant efficace pour un seul convertisseur. Notre étude vise également à réduire le courant RMS dans le condensateur et à trouver la valeur optimale du temps d'entrelacement de manière dynamique pour tous les points de fonctionnement
The impact of Pulse Width Modulation (PWM) strategies on the stresse of the decoupling capacitors at the input of a three-phase converter is currently well known, as well as the behavior of the supplied load (power factor). A large panel of modulation techniques is currently available and can be applied according to the various environmental constraints (stress on the capacitors but also quality of the currents in the load or switching losses in the semiconductors). However, in many application contexts, the DC bus can be shared between several converters that will individually stress the decoupling capacitor(s). The objective of this thesis is to study the implementation of PWM strategies between several converters sharing their DC bus. More precisely, a study of the case of back-to-back converters connected on Doubly Fed Induction Machine (DFIM) has been done. The aim of this study is to evaluate the impact of interleaved PWM strategies on the RMS current flowing through the DC link capacitor associated to two back-to-back three-phase Full Bridges (FB). Indeed, this value is usually the key-parameter for the sizing of this (or these) component(s), far above the capacitance, especially for aluminum electrolytic capacitors. Interleaving technique is applied on two different strategies: - Classical (single carrier) Space-Vector PWM strategy (SVPWM) ; - Unified Double Carrier PWM (Uni-DCPWM) that is dedicated to the reduction of the RMS current for a single FB. Our study also aims to reduce the RMS current in the capacitor and find the optimal value of the interleaving time dynamically for all operating points

1.1 Objectius de la tesi.
En els últims anys el control del parell i de la velocitat del motor d'inducció ha estat llargament estudiat. Un cop s'ha considerat que les prestacions dinàmiques assolibles eren ja suficientment satisfactòries, els diferents investigadors han reorientat els seus esforços cap a altres enfocs relacionats, ja no únicament amb el MI estrictament parlant, sinó amb tot el sistema que constitueix l'accionament amb si mateix.

L'objectiu principal d'aquesta tesi és posar en evidència, l'existència d'unes idealitzacions i limitacions dels controls tradicionals de parell i velocitat del motor d'inducció (bàsicament del Control Vectorial i del DTC), així com a proposar mètodes i algorismes alternatius que superin a les mateixes.

1.2 Estructura i contingut

El Capítol 1 conté una introducció al treball.

El segon capítol Modelització del motor d'inducció, presenta les principals tècniques i equacions, que porten a descriure d'una forma dinàmica al MI.

El tercer capítol, Control de parell i velocitat del MI, es descriuen els Control Vectorial i el Control Directe de Parell (DTC), ja que són els més estudiats en la literatura.

El quart capítol, Estudi dels bucles de corrent, tracta més en profunditat una de les limitacions que presenta el Control Vectorial, l'estudi de les interaccions que hi ha entre els dos llaços de regulació de les intensitats de l'estator (la seva component directa i en quadratura).

En el cinquè capítol, OSVPWM (Optimized Space Vector PWM), es presenta un estudi detallat dels diferents mètodes d'ondulació (DC/AC) que existeixen. D'entre tots aquests, s'estudia amb molt més deteniment el Space Vector PWM (SVPWM), aportant un nou algorisme d'implementació del mateix (optimitzat per DSP's), així com posant en evidència la negativa influència dels temps morts sobre el mateix.

El sisè capítol presenta l'ODTC (Optimized Direct Torque Control), com a resum de tots els capítols anteriors.
1.3 Aportacions d'aquesta tesi.

En la modelització matemàtica del Motor d'Inducció, s'ha arribat a la formulació d'una equació genèrica, que engloba totes les possibles referències, i totes les definicions d'intensitats magnetitzants.

En l'estudi del DTC s'ha presentat una nova taula de commutació, que permet disminuir l'excessiu arrissat de parell que presenta la taula de commutació tradicional.

En l'estudi del SVPWM s'ha presentat una nova formulació molt més apta per a la seva implementació en DSP (Digital Signal Processor). Igualment, s'ha posat en evidència la important influència dels temps morts dels interruptors, en la THD (Tasa de Distorsió Harmònica) de l'ona de tensió de sortida de l'ondulador proposant un algorisme de compensació (OSVPWM).

S'ha proposat un nou algorisme de control del parell del MI, incorporant les prestacions del DTC en règim transitori (ràpida resposta del parell), i les prestacions del Control Vectorial en règim permanent (petit arrissat de parell), amb la incorporació de l'OSVPWM com a estratègia de modulació.

Finalment destacar, l'aportació d'un equip experimental basat en DSP, de disseny molt versàtil i robust, i que incorpora tota una sèrie d'eines de desenvolupament que el fan molt útil per a l'experimentació de noves lleis de control, referides principalment al motor d'inducció, però que també s'ha demostrat eficient alhora de treballar amb altres plantes com és el cas dels SAI's (Sistemes d'Alimentació Ininterrompuda).

1.4 Futures línies de recerca.

Seguir treballant en l'estudi del OSVPM, però en el cas de la sobremodulació, és a dir, quan la tensió de consigna superi o surti fora dels rangs d'aplicabilitat del mateix.

Amb l'obtenció de l'equació que ens permet estimar l'arrissat màxim de parell, associat al conjunt motor-ondulador, estudiar el disseny de controladors per histèresi de banda d'histèresi variable (funció de l'estat de l'accionament).

Finalment destacar, que amb el constant augment de la potència de càlcul dels DSP, les possibilitats de noves lleis de control del MI ("fuzzy logic" i "passivity control") són cada dia més possibles, i per tant s'han convertit en una línia de treball molt interessant.

A method for high performance output voltage control of a four-leg inverter based three-phase transformerless UPS is proposed. Voltage control loop is employed and the method employs stationary frame resonant filter controllers for the fundamental and harmonic frequency components. A capacitor current feedback loop provides active damping and enhances the output voltage dynamic performance. The controller design and implementation details are given. Linear and nonlinear loads for balanced and unbalanced load operating conditions are considered. The steadystate and dynamic performance of the UPS are investigated in detail. A scalar PWM method with implementation simplicity and high performance is proposed and implemented. The control and PWM methods are proven by means of theory, simulations, and experiments.

A repetitive control method for output voltage control of a three phase uninterruptible power supply (UPS) with isolation transformer is investigated. In the method voltage control loop is employed in the stationary dq frame. The controller eliminates the periodic errors on the output voltages due to inverter voltage nonlinearity and load disturbances. The controller design and implementation details are given. The controller is implemented on a 5-kVA UPS prototype which is constructed in laboratory. Linear and nonlinear loads for balanced and unbalanced load operating conditions are considered. The steady-state and dynamic performance of the control method are investigated in detail. The theory of the control strategy is verified by means of simulations and experiments.

This work deals with three-phase active rectifier control. In first, theoretical part it describes several control strategies with focus on voltage oriented control. For this type of control a design is worked out, and created model and its simulation is described. Second, practical part deals with realisation on microcontroller TMS320F28335, which is main processing unit of device lent by company Elcom. Therefore in this part abilities and settings of the controller along with developped control algorithm are described. Reached results of measurement are then presented and in the conclusion they are evaluated.

Thesis (Ph. D.)--Ohio State University, 2005.
Title from first page of PDF file. Document formatted into pages; contains xvi, 209 p.; also includes graphics. Includes bibliographical references (p. 202-209). Available online via OhioLINK's ETD Center

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

The ability of a piezoelectric transducer in energy conversion is rapidly expanding in several applications. Some of the industrial applications for which a high power ultrasound transducer can be used are surface cleaning, water treatment, plastic welding and food sterilization. Also, a high power ultrasound transducer plays a great role in biomedical applications such as diagnostic and therapeutic applications. An ultrasound transducer is usually applied to convert electrical energy to mechanical energy and vice versa. In some high power ultrasound system, ultrasound transducers are applied as a transmitter, as a receiver or both. As a transmitter, it converts electrical energy to mechanical energy while a receiver converts mechanical energy to electrical energy as a sensor for control system. Once a piezoelectric transducer is excited by electrical signal, piezoelectric material starts to vibrate and generates ultrasound waves. A portion of the ultrasound waves which passes through the medium will be sensed by the receiver and converted to electrical energy. To drive an ultrasound transducer, an excitation signal should be properly designed otherwise undesired signal (low quality) can deteriorate the performance of the transducer (energy conversion) and increase power consumption in the system. For instance, some portion of generated power may be delivered in unwanted frequency which is not acceptable for some applications especially for biomedical applications. To achieve better performance of the transducer, along with the quality of the excitation signal, the characteristics of the high power ultrasound transducer should be taken into consideration as well. In this regard, several simulation and experimental tests are carried out in this research to model high power ultrasound transducers and systems. During these experiments, high power ultrasound transducers are excited by several excitation signals with different amplitudes and frequencies, using a network analyser, a signal generator, a high power amplifier and a multilevel converter. Also, to analyse the behaviour of the ultrasound system, the voltage ratio of the system is measured in different tests. The voltage across transmitter is measured as an input voltage then divided by the output voltage which is measured across receiver. The results of the transducer characteristics and the ultrasound system behaviour are discussed in chapter 4 and 5 of this thesis. Each piezoelectric transducer has several resonance frequencies in which its impedance has lower magnitude as compared to non-resonance frequencies. Among these resonance frequencies, just at one of those frequencies, the magnitude of the impedance is minimum. This resonance frequency is known as the main resonance frequency of the transducer. To attain higher efficiency and deliver more power to the ultrasound system, the transducer is usually excited at the main resonance frequency. Therefore, it is important to find out this frequency and other resonance frequencies. Hereof, a frequency detection method is proposed in this research which is discussed in chapter 2. An extended electrical model of the ultrasound transducer with multiple resonance frequencies consists of several RLC legs in parallel with a capacitor. Each RLC leg represents one of the resonance frequencies of the ultrasound transducer. At resonance frequency the inductor reactance and capacitor reactance cancel out each other and the resistor of this leg represents power conversion of the system at that frequency. This concept is shown in simulation and test results presented in chapter 4. To excite a high power ultrasound transducer, a high power signal is required. Multilevel converters are usually applied to generate a high power signal but the drawback of this signal is low quality in comparison with a sinusoidal signal. In some applications like ultrasound, it is extensively important to generate a high quality signal. Several control and modulation techniques are introduced in different papers to control the output voltage of the multilevel converters. One of those techniques is harmonic elimination technique. In this technique, switching angles are chosen in such way to reduce harmonic contents in the output side. It is undeniable that increasing the number of the switching angles results in more harmonic reduction. But to have more switching angles, more output voltage levels are required which increase the number of components and cost of the converter. To improve the quality of the output voltage signal with no more components, a new harmonic elimination technique is proposed in this research. Based on this new technique, more variables (DC voltage levels and switching angles) are chosen to eliminate more low order harmonics compared to conventional harmonic elimination techniques. In conventional harmonic elimination method, DC voltage levels are same and only switching angles are calculated to eliminate harmonics. Therefore, the number of eliminated harmonic is limited by the number of switching cycles. In the proposed modulation technique, the switching angles and the DC voltage levels are calculated off-line to eliminate more harmonics. Therefore, the DC voltage levels are not equal and should be regulated. To achieve this aim, a DC/DC converter is applied to adjust the DC link voltages with several capacitors. The effect of the new harmonic elimination technique on the output quality of several single phase multilevel converters is explained in chapter 3 and 6 of this thesis. According to the electrical model of high power ultrasound transducer, this device can be modelled as parallel combinations of RLC legs with a main capacitor. The impedance diagram of the transducer in frequency domain shows it has capacitive characteristics in almost all frequencies. Therefore, using a voltage source converter to drive a high power ultrasound transducer can create significant leakage current through the transducer. It happens due to significant voltage stress (dv/dt) across the transducer. To remedy this problem, LC filters are applied in some applications. For some applications such as ultrasound, using a LC filter can deteriorate the performance of the transducer by changing its characteristics and displacing the resonance frequency of the transducer. For such a case a current source converter could be a suitable choice to overcome this problem. In this regard, a current source converter is implemented and applied to excite the high power ultrasound transducer. To control the output current and voltage, a hysteresis control and unipolar modulation are used respectively. The results of this test are explained in chapter 7.

碩士
國立交通大學
電機與控制工程系
87
Soft-switching techniques ( zero current switching or zero voltage switching ) applied to power inverter can substantially improve the performances, allowing high frequency operation and minimization of acoustic noise and EMI, reduction of switching losses, limitation of dv/dt and di/dt stress in the power devices .The quasi-resonant dc link soft switching circuit used in this paper needs additional components such as two switches, a diode, an inductor and a capacitor, the two switches are also soft switching, which produces a minimum losses. The quasi-resonant dc link circuit notching the bus voltage and allowing the switches of the inverter just switching at zero voltage. The modulation technique we adapt is Space-Vector PWM and refuse traditional sinusoidal PWM, because the SPWM can't completely utilize the dc link voltage, current ripple is badly and analogical mode control, which is complex and not easy to maintain. Now the digitalization design has become the standard of the drive- controller, so the superior performance and easy-digitized SV-PWM has become major method in the PWM techniques. The control of the system are processed by the chips FLEX PF10KAL10LC C84-4 of Altera company. Whose hardware description language can scrimp the time in design and makes the system more easily to maintain and modify. The experiment results have shown that our soft-switching circuit works very stable and reliably.

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives.
Power Engineering and Power Electronics

碩士
義守大學
電機工程學系
87
Pulse Width Modulation (PWM) is the most widely used technology for power transition. It is the necessary element in the applications of motor drivers and uninterrupted power suppliers. The disadvantage of large dimensions, lots of elements and affection from temperature exists in the classical analog PWM. To improve it, the digital signal processors are used to implement the digital PWM. However, the complex calculations cause the sampling time increased and enlarge the distortion of output waveform. Now, the new chip of ASIC can focus all functions in one chip. This method will free from change at the temperature outside and affect its parameter values. The object of this paper is to implement the ASIC of Space Vector PWM (SVPWM) by the Complex Programmable Logic Device (CPLD). This designed chip will calculate at high speed to boost the sampling frequency and reduce the burden of DSP. At the same time, the high speed switching operation will decrease the problem of high harmonic distortion. Meanwhile, the function of this chip will maintain the accurate performance within long time operation to against the temperature variation.

碩士
國立交通大學
電控工程研究所
102
The thesis proposed a single shunt register current sensing method of the Space Vector Pulse Width Modulation (SVPWM) Inverters for Permanent Magnet Synchronous Motors (PMSM). It is based on the measurement of the current through the shunt resistor that it puts in the dc bus of the inverter. The sampling timing is provided by the switch electronic signals of the transistors. Then, the three-phase current is used to calculate the rotor position and the velocity and implement the Field Oriented Control (FOC). Some aspects involving the non-ideal behavior of the system and proposed the adjustments strategy are discussed in details. Finally, the proposed method is implemented in a PMSM of the stand fan with STM3210B-MCKIT Development Kit (microcontroller and power boards).

This work provides a control strategy for PWM rectifiers using space vector modulation technique by keeping the switching frequency as constant. Instead of using line currents as control variables here instantaneous active and reactive power are used as signals for modulation of PWM rectifiers. In traditional control methods like VDPC and VFDPC, we are having line voltage estimator and virtual flux estimator. Here virtual flux estimator and line voltage estimator are replaced with Phase Locked Loop for better performance in distorted conditions at source side. The strategy of direct power control using space vector modulation is discussed theoretically. The steady state results are presented for the proposed DPC – SVM system. Compared to other control strategies the DPC-SVM have special features like constant switching frequency, unity power factor by providing distortion less sine wave as current under unbalanced conditions.

碩士
國立臺灣科技大學
工程技術研究所
81
We discuss the simulation and design of the driver system of the induction servo motor in the one of the essay. Induction motor control is by the voltage vector space modulation method. The control system applies the algorithm of synchrous coordinate. The content of the essay include of the voltage vector space modulation ,the simulation of open loop and close loop induction motor control.Specially,the open loop induction motor control adopted the method of the ratio of V/F. Another object of the essay discusses the analysis and design of snubber circuit of the inveter.The switching surge will damage the driver element.The snubber circuit is necessary to the design of inverter.The essay introduce the three types of snubber circuit.Simulation adopt PSPICE tools to demostrate the property of the snubber circuit.

碩士
國立成功大學
工程科學系碩博士班
93
This thesis presents a new direct torque control (DTC) system to control the permanent magnet synchronous motor (PMSM) based on a TMS320F2812 digital signal processor (DSP) experiment board. The digitalized PMSM control system was implemented by using DSP experiment board with advantages such as high precision and reliability and the controlling error caused by the variance of temperature or the interference of noise can be banished. 　The proposed DTC scheme in this thesis uses a flux compensator to eliminate the error in stator flux estimation at low speed operating region of the conventional DTC. Furthermore, to improve the flux linkage tracking, two PI controllers used to be the torque controller and the flux controller. The outputs magnitude of the flux regulator, , is controlled by the outputs of the torque controller and flux controller. The voltage command of the output of the flux regulator will be used to decide the space voltage vector PWM and determine the magnitude of the stator flux linkage. 　The simulation and experimental results for the proposed DTC were compared with a conventional DTC. These show that the proposed DTC has a high control performance than the conventional DTC.

碩士
大葉大學
機械工程研究所碩士班
96
In recent years, owing to the environmental protection concept has risen and global warming, it is important to reduce the environmental pollution. If the merits of both internal combustion engine and permanent magnet synchronous motor (PMSM) can be integrated to become a hybrid electric vehicle, it must have ultra-low pollution and energy-saving but still keeping high performance. For this reason, the central purpose of this thesis is to develop a novel parallel hybrid electric vehicle system driver and controller. Electronic motor control systems used by extremely versatile digital signal processor (DSP). The important space vector pulse-width-modulation (SVPWM) technology is applied to the PMSM control to provide more efficiency of the hybrid electric vehicle. The SVPWM technology is also guarantees the system to be stable with better performance. Subsequently, by way of experiment results have proved the SVPWM technology provides more and more performance of the PMSM and the SVPWM technology have been applied in hybrid electric vehicle with high efficiency. Finally, a prototype of the hybrid electric heavy-duty motorcycle has been established and it has been exhibit on the “Taipei international automobile electronics show” at the Taipei world trade center in 2007.

Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor. The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss. Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination. Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures. A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents. Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter. A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions. Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes.

A split-phase induction motor (SPIM) is obtained by splitting each of the three-phase stator windings of an induction motor into two equal halves. This results in two sets of three-phase windings with a spatial angle difference of 30◦ (electrical) between them. The two sets of windings are fed from two different voltage-source inverters for speed control of the split-phase motor drive. Low dc bus voltage requirement and improved torque profile are some of the advantages of the split-phase motor, compared to the normal three-phase induction motor. A pulse width modulation (PWM) technique is used to produce the gating signals for the power semiconductor devices in the two inverters. The PWM technique can either be a carrier comparison (CC) based method or a space-vector (SV) based scheme. The carrier based PWM methods employ six modulating waves, which are compared against a common triangular carrier to generate the gating pulses. In space-vector based PWM schemes, the voltage reference is specified in terms of a rotating reference vector. In each subcycle, a set of voltage vectors are applied for appropriate durations of time to produce an average vector equal to the reference vector. Unlike three-phase induction motor drives, where the voltage vectors are two dimensional, the voltage vectors in the case of SPIM drive are four dimensional. This thesis presents a detailed survey on carrier-comparison based and space-vector based PWM techniques for the SPIM drive. In this thesis, sine-triangle PWM (STPWM) is analyzed from a space-vector perspective. The set of voltage vectors applied and the sequence of application of the voltage vectors in each half-carrier cycle are studied. The analysis shows that the set of voltage vectors and the switching sequence employed by STPWM are different from those used by the well known SVPWM tech-niques. Two other CC based PWM techniques, based on common mode injection, are considered for the SPIM drive. In one method, the common-mode signal is derived from all the six modulating signals, and is the same for both the inverters. In the second method, the common-mode signal is different for the two inverters; each common-mode signal is derived from the three-phase sinusoidal signals of the respective inverter. The study shows that the latter method has the highest dc bus utilization and results in the lowest total harmonic distortion (THD) among the CC PWM techniques. An experimental comparison of the three carrier-comparison techniques with three well known space-vector PWM techniques is presented. Total harmonic distortion (THD) of the line current is measured at different modulation indices for all six techniques. The experimental results are obtained from a 6kW, 200V, 50Hz split-phase induction motor drive, with constant V /F ratio. The PWM techniques are implemented using an ALTERA cyclone II field programmable gate array (FPGA) digital controller. One of the SV techniques, termed here as 4-dimensional 24-sector (4D24SEC) PWM is found to be the best in terms of line current THD among all the CC and SV based PWM techniques considered. However, compared to any carrier-based technique, implementation of the 4D24SEC PWM based on the space vector approach is found to be resource intensive. Hence, an equivalent carrier-based implementation of 4D24SEC PWM is proposed in this thesis. The feasibility of the proposed approach is verified experimentally, and is found to be consuming much less logical resources than the space-vector implementation (i.e. 4102 logical elements for the CC approach as against 33,655 logical elements for the SV approach). A new space-vector PWM technique is also proposed in the thesis. This technique utilizes a new set of voltage vectors and a new switching sequence, which are motivated by the analyses of the carrier-based methods, presented earlier. The proposed technique is implemented, and is compared with other space-vector and carrier-based methods at different modulation indices and switching frequencies. The proposed PWM technique is found to have the same dc-bus utilization as the existing 4-dimensional SV based PWM techniques. The performance of the proposed method is found to be not better than existing 4-dimensional SV PWM methods. The possibilities for new switching sequence is being explored here.

A split-phase induction motor (SPIM) is obtained by splitting each of the three-phase stator windings of an induction motor into two equal halves. This results in two sets of three-phase windings with a spatial angle difference of 30◦ (electrical) between them. The two sets of windings are fed from two different voltage-source inverters for speed control of the split-phase motor drive. Low dc bus voltage requirement and improved torque profile are some of the advantages of the split-phase motor, compared to the normal three-phase induction motor. A pulse width modulation (PWM) technique is used to produce the gating signals for the power semiconductor devices in the two inverters. The PWM technique can either be a carrier comparison (CC) based method or a space-vector (SV) based scheme. The carrier based PWM methods employ six modulating waves, which are compared against a common triangular carrier to generate the gating pulses. In space-vector based PWM schemes, the voltage reference is specified in terms of a rotating reference vector. In each subcycle, a set of voltage vectors are applied for appropriate durations of time to produce an average vector equal to the reference vector. Unlike three-phase induction motor drives, where the voltage vectors are two dimensional, the voltage vectors in the case of SPIM drive are four dimensional. This thesis presents a detailed survey on carrier-comparison based and space-vector based PWM techniques for the SPIM drive. In this thesis, sine-triangle PWM (STPWM) is analyzed from a space-vector perspective. The set of voltage vectors applied and the sequence of application of the voltage vectors in each half-carrier cycle are studied. The analysis shows that the set of voltage vectors and the switching sequence employed by STPWM are different from those used by the well known SVPWM tech-niques. Two other CC based PWM techniques, based on common mode injection, are considered for the SPIM drive. In one method, the common-mode signal is derived from all the six modulating signals, and is the same for both the inverters. In the second method, the common-mode signal is different for the two inverters; each common-mode signal is derived from the three-phase sinusoidal signals of the respective inverter. The study shows that the latter method has the highest dc bus utilization and results in the lowest total harmonic distortion (THD) among the CC PWM techniques. An experimental comparison of the three carrier-comparison techniques with three well known space-vector PWM techniques is presented. Total harmonic distortion (THD) of the line current is measured at different modulation indices for all six techniques. The experimental results are obtained from a 6kW, 200V, 50Hz split-phase induction motor drive, with constant V /F ratio. The PWM techniques are implemented using an ALTERA cyclone II field programmable gate array (FPGA) digital controller. One of the SV techniques, termed here as 4-dimensional 24-sector (4D24SEC) PWM is found to be the best in terms of line current THD among all the CC and SV based PWM techniques considered. However, compared to any carrier-based technique, implementation of the 4D24SEC PWM based on the space vector approach is found to be resource intensive. Hence, an equivalent carrier-based implementation of 4D24SEC PWM is proposed in this thesis. The feasibility of the proposed approach is verified experimentally, and is found to be consuming much less logical resources than the space-vector implementation (i.e. 4102 logical elements for the CC approach as against 33,655 logical elements for the SV approach). A new space-vector PWM technique is also proposed in the thesis. This technique utilizes a new set of voltage vectors and a new switching sequence, which are motivated by the analyses of the carrier-based methods, presented earlier. The proposed technique is implemented, and is compared with other space-vector and carrier-based methods at different modulation indices and switching frequencies. The proposed PWM technique is found to have the same dc-bus utilization as the existing 4-dimensional SV based PWM techniques. The performance of the proposed method is found to be not better than existing 4-dimensional SV PWM methods. The possibilities for new switching sequence is being explored here.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.