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Journal articles on the topic 'SPARC (Scalable Processor ARChitecture)'

Author: Grafiati

Published: 4 June 2021

Last updated: 9 February 2022

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1

Agrawal, Anant, and Robert B. Garner. "SPARC: A scalable processor architecture." Future Generation Computer Systems 7, no. 2-3 (1992): 303–9. http://dx.doi.org/10.1016/0167-739x(92)90017-6.

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Kongetira, P., K. Aingaran, and K. Olukotun. "Niagara: A 32-Way Multithreaded Sparc Processor." IEEE Micro 25, no. 2 (2005): 21–29. http://dx.doi.org/10.1109/mm.2005.35.

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3

Lee, Roland L., Alex Y. Kwok, and Fayé A. Briggs. "The floating point performance of a superscalar SPARC processor." ACM SIGOPS Operating Systems Review 25, Special Issue (1991): 28–37. http://dx.doi.org/10.1145/106974.106978.

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4

Becker, J., and A. Thomas. "Scalable Processor Instruction Set Extension." IEEE Design and Test of Computers 22, no. 2 (2005): 136–48. http://dx.doi.org/10.1109/mdt.2005.43.

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CHOI, M., and S. MAENG. "An Energy Efficient Instruction Window for Scalable Processor Architecture." IEICE Transactions on Electronics E91-C, no. 9 (2008): 1427–36. http://dx.doi.org/10.1093/ietele/e91-c.9.1427.

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Buchenrieder, K., R. Kress, A. Pyttel, A. Sedlmeier, and C. Veith. "Scalable processor architecture for Java with explicit thread support." Electronics Letters 33, no. 18 (1997): 1532. http://dx.doi.org/10.1049/el:19971049.

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Mao-Yin Wang and Cheng-Wen Wu. "A Mesh-Structured Scalable IPsec Processor." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 5 (2010): 725–31. http://dx.doi.org/10.1109/tvlsi.2009.2016102.

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Ibrahim, Atef. "Scalable digit-serial processor array architecture for finite field division." Microelectronics Journal 85 (March 2019): 83–91. http://dx.doi.org/10.1016/j.mejo.2019.01.011.

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Mandolesi, P. S., P. Julian, and A. G. Andreou. "A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 5 (2004): 988–96. http://dx.doi.org/10.1109/tcsi.2004.827626.

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Feehrer, John, Sumti Jairath, Paul Loewenstein, et al. "The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets." IEEE Micro 33, no. 2 (2013): 48–57. http://dx.doi.org/10.1109/mm.2013.49.

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Arafa, Mohamed, Bahaa Fahim, Sailesh Kottapalli, et al. "Cascade Lake: Next Generation Intel Xeon Scalable Processor." IEEE Micro 39, no. 2 (2019): 29–36. http://dx.doi.org/10.1109/mm.2019.2899330.

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CATANIA, V., and G. ASCIA. "A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT SYSTEMS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 421–47. http://dx.doi.org/10.1142/s0218001495000201.

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In this paper we present a VLSI fuzzy processor whose main features are a scalable parallel architecture, and the computation of fuzzy inferences based on the α-level set theory, both of which are important in the field of intensive fuzzy computing, as in fuzzy expert systems. A specific analysis is made in the paper, of techniques for the representation of fuzzy sets, in relation to the amount of area occupied and the forms they can assume. From this analysis a solution is extracted and then used for the processor presented in the paper. The architecture of the processor is chosen after the a

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Satoh, A., and K. Takano. "A scalable dual-field elliptic curve cryptographic processor." IEEE Transactions on Computers 52, no. 4 (2003): 449–60. http://dx.doi.org/10.1109/tc.2003.1190586.

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MOTLAGH, BAHMAN S., and RONALD F. DeMARA. "PERFORMANCE OF SCALABLE SHARED-MEMORY ARCHITECTURES." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 1–22. http://dx.doi.org/10.1142/s0218126600000068.

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Analytical models were developed and simulations of memory latency were performed for Uniform Memory Access (UMA), Non-Uniform Memory Access (NUMA), Local-Remote-Global (LRG), and RCR architectures for hit rates from 0.1 to 0.9 in steps of 0.1, memory access times of 10 to 100 ns, proportions of read/write access from 0.01 to 0.1, and block sizes of 8 to 64 words. The RCR architecture provides favorable performance over UMA and NUMA architectures for all ranges of application and system parameters. RCR outperforms LRG architectures when the hit rates of the processor cache exceed 80%and replic

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Theelen, B. D., A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, and A. Nuñez. "A scalable single-chip multi-processor architecture with on-chip RTOS kernel." Journal of Systems Architecture 49, no. 12-15 (2003): 619–39. http://dx.doi.org/10.1016/s1383-7621(03)00101-2.

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Massolino, Pedro Maat C., Paulo S. L. M. Barreto, and Wilson V. Ruggiero. "Optimized and Scalable Co-Processor for McEliece with Binary Goppa Codes." ACM Transactions on Embedded Computing Systems 14, no. 3 (2015): 1–32. http://dx.doi.org/10.1145/2736284.

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Loi, K. C. Cinnati, and Seok-Bum Ko. "High performance scalable elliptic curve cryptosystem processor for Koblitz curves." Microprocessors and Microsystems 37, no. 4-5 (2013): 394–406. http://dx.doi.org/10.1016/j.micpro.2013.03.003.

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Guironnet de Massas, P., P. Amblard, and F. Pétrot. "On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration." VLSI Design 2007 (July 10, 2007): 1–10. http://dx.doi.org/10.1155/2007/28686.

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This paper presents the necessary steps to modify the implementation of the SPARCV8 architecture to enhance it with multimedia-oriented instructions. The purpose is improving video compression performance without designing dedicated coprocessors. We investigate the complexity of modifying a standard processor instruction set and show that, although not trivial, this is feasible in a few weeks. We implemented 12 new instructions and use some of them to optimize the computation of a demanding step of the MPEG encoding. The result is a performance increase of 67% in the execution of a part of thi

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DEL CAMPO, INÉS, JAVIER ECHANOBE, KOLDO BASTERRETXEA, and GUILLERMO BOSQUE. "SCALABLE ARCHITECTURE FOR HIGH-SPEED MULTIDIMENSIONAL FUZZY INFERENCE SYSTEMS." Journal of Circuits, Systems and Computers 20, no. 03 (2011): 375–400. http://dx.doi.org/10.1142/s0218126611007359.

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This paper presents a scalable architecture suitable for the implementation of high-speed fuzzy inference systems on reconfigurable hardware. The main features of the proposed architecture, based on the Takagi–Sugeno inference model, are scalability, high performance, and flexibility. A scalable fuzzy inference system (FIS) must be efficient and practical when applied to complex situations, such as multidimensional problems with a large number of membership functions and a large rule base. Several current application areas of fuzzy computation require such enhanced capabilities to deal with re

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Jung, Yongchul, Hohyub Jeon, Seongjoo Lee, and Yunho Jung. "Scalable ESPRIT Processor for Direction-of-Arrival Estimation of Frequency Modulated Continuous Wave Radar." Electronics 10, no. 6 (2021): 695. http://dx.doi.org/10.3390/electronics10060695.

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The estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that uses the shift-invariant properties of the array antenna to estimate the direction-of-arrival (DOA) of signals received in the array antenna. Since the ESPRIT algorithm requires high-complexity operations such as covariance matrix and eigenvalue decomposition, a hardware processor must be implemented such that the DOA is estimated in real time. Additionally, the ESPRIT processor should support a scalable number of antenna configuration for DOA estimation in various applications because the pe

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Kamran, Arezoo, and Zainalabedin Navabi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016 (July 25, 2016): 1–17. http://dx.doi.org/10.1155/2016/9767139.

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More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-

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MINEGISHI, N. "VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation." IEICE Transactions on Electronics E89-C, no. 3 (2006): 230–42. http://dx.doi.org/10.1093/ietele/e89-c.3.230.

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Motupalle, Haritha, and Syed Jahangir Badashah. "A Novel VLSI Architecture for SPHIT Encoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 4 (2013): 1522–30. http://dx.doi.org/10.24297/ijct.v10i4.3252.

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In this Paper we propose a highly scalable image compression scheme based on the set partitioning in hierarchical trees (SPIHT) algorithm. Our algorithm called highly scalable SPIHT (HS-SPIHT), supports spatial and SNR scalability and provides a bit stream that can be easily adapted (reordered) to given bandwidth and resolution requirements by a simple transcoder (parser). The HS-SPIHT algorithm adds the spatial scalability feature without sacrificing the SNR embeddedness property as found in the original SPIHT bit stream. HS-SPIHT finds applications in progressive Web browsing, flexible image

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Honkanen, Risto, and Ville Leppänen. "Routing in Coloured Sparse Optical Tori by Using Balanced WDM and Network Sparseness." International Journal of Distributed Systems and Technologies 3, no. 4 (2012): 52–62. http://dx.doi.org/10.4018/jdst.2012100105.

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The authors present a WDM (Wavelength-Division Multiplexing) based all-optical network architecture, and study scheduled routing on it. Their architecture can be seen as a communication system of parallel multi-core computer or a large-scale high bandwidth routing switch of e.g., telecommunication network. The goal is to construct such a scalable architecture and a supporting routing protocol for it so that no electro-optical conversions are needed on the routing paths, all packets are routed along one of the shortest paths, processor nodes can inject packets constantly into the network, and a

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Ibrahim, Atef, Fayez Gebali, Hamed Elsimary, and Amin Nassar. "Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm." IEEE Transactions on Parallel and Distributed Systems 22, no. 7 (2011): 1142–49. http://dx.doi.org/10.1109/tpds.2010.196.

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Konstadinidis, G. K., M. Tremblay, S. Chaudhry, et al. "Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor." IEEE Journal of Solid-State Circuits 44, no. 1 (2009): 7–17. http://dx.doi.org/10.1109/jssc.2008.2007144.

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Dousti, Mohammad J., Alireza Shafaei, and Massoud Pedram. "Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing." Quantum Information and Computation 16, no. 3&4 (2016): 332–56. http://dx.doi.org/10.26421/qic16.3-4-8.

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We present a multi-core reconfigurable quantum processor architecture, called Requp, which supports a hierarchical approach to mapping a quantum algorithm while sharing physical and logical ancilla qubits. Each core is capable of performing any quantum instruction. Moreover, we introduce a scalable quantum mapper, called Squash 2, which divides a given quantum circuit into a number of quantum modules—each module is divided into k parts such that each part will run on one of k available cores. Experimental results demonstrate that Squash 2 can handle large-scale quantum algorithms while providi

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BAGHERZADEH, NADER, and MASARU MATSUURA. "PERFORMANCE IMPACT OF TASK-TO-TASK COMMUNICATION PROTOCOL IN NETWORK-ON-CHIP." Journal of Circuits, Systems and Computers 18, no. 02 (2009): 283–94. http://dx.doi.org/10.1142/s021812660900506x.

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Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication pro

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Ahmed, O., S. Areibi, and G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm." International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.

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Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art cl

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30

Roka, Sanjay, and Santosh Naik. "SURVEY ON SIGNATURE BASED INTRUCTION DETECTION SYSTEM USING MULTITHREADING." International Journal of Research -GRANTHAALAYAH 5, no. 4RACSIT (2017): 58–62. http://dx.doi.org/10.29121/granthaalayah.v5.i4racsit.2017.3352.

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The traditional way of protecting networks with firewalls and encryption software is no longer sufficient and effective. Many intrusion detection techniques have been developed on fixed wired networks but have been turned to be inapplicable in this new environment. We need to search for new architecture and mechanisms to protect computer networks. Signature-based Intrusion Detection System matches network packets against a pre-configured set of intrusion signatures. Current implementations of IDS employ only a single thread of execution and as a consequence benefit very little from multi-proce

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Qiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.

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In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with stat

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Rutzig, Mateus B., Antonio C. S. Beck, Felipe Madruga, et al. "Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment." International Journal of Reconfigurable Computing 2011 (2011): 1–13. http://dx.doi.org/10.1155/2011/546962.

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Limits of instruction-level parallelism and higher transistor density sustain the increasing need for multiprocessor systems: they are rapidly taking over both general-purpose and embedded processor domains. Current multiprocessing systems are composed either of many homogeneous and simple cores or of complex superscalar, simultaneous multithread processing elements. As parallel applications are becoming increasingly present in embedded and general-purpose domains and multiprocessing systems must handle a wide range of different application classes, there is no consensus over which are the bes

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Gan, Victor M., Yibin Liang, Lianjun Li, Lingjia Liu, and Yang Yi. "A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021): 1–15. http://dx.doi.org/10.1145/3440017.

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The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48

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Chen-Hung Lin, Chun-Yu Chen, and An-Yeu Wu. "Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 2 (2011): 305–18. http://dx.doi.org/10.1109/tvlsi.2009.2032553.

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Ibrahim, Atef, and Fayez Gebali. "Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 11 (2017): 2894–906. http://dx.doi.org/10.1109/tcsi.2017.2691353.

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36

WAN, JIN-YIN, YU-ZHU WANG, and LIANG LIU. "TWO-DIMENSIONAL ARRAY OF ION TRAPS ON A PLANAR CHIP." Modern Physics Letters B 23, no. 01 (2009): 47–61. http://dx.doi.org/10.1142/s0217984909017819.

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We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simp

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Wan, Yong, Daniel Kienzler, Stephen D. Erickson, et al. "Quantum gate teleportation between separated qubits in a trapped-ion processor." Science 364, no. 6443 (2019): 875–78. http://dx.doi.org/10.1126/science.aaw9415.

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Large-scale quantum computers will require quantum gate operations between widely separated qubits. A method for implementing such operations, known as quantum gate teleportation (QGT), requires only local operations, classical communication, and shared entanglement. We demonstrate QGT in a scalable architecture by deterministically teleporting a controlled-NOT (CNOT) gate between two qubits in spatially separated locations in an ion trap. The entanglement fidelity of our teleported CNOT is in the interval (0.845, 0.872) at the 95% confidence level. The implementation combines ion shuttling wi

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38

Ogbodo, Mark, Khanh Dang, Fukuchi Tomohide, and Abderazek Abdallah. "Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor." SHS Web of Conferences 77 (2020): 04003. http://dx.doi.org/10.1051/shsconf/20207704003.

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Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of sy

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AL-ROUSAN, M., O. AL-JARRAH, and M. MOWAFI. "K-PROCESSOR RELIABILITY OF LARGE-SCALE RING-BASED HIERARCHICAL INTERCONNECTIONS." International Journal of Reliability, Quality and Safety Engineering 09, no. 01 (2002): 61–77. http://dx.doi.org/10.1142/s0218539302000664.

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Recently, connecting thousands of processors via interconnection networks based on multiple (hierarchical) rings has an increased interest. This is due to the large acceptance and success of the Scalable Coherent Interface (SCI) technology. The inherently weak behavior of ring architecture has led interconnection designers to consider various choices to improve the overall network reliability. An interesting choice is to use braided rings instead of the single (basic) rings in the hierarchy. In this paper, we present new formulas for computing K-processor reliability of SCI ring-based hierarch

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Kong, Fande, and Xiao-Chuan Cai. "Scalability study of an implicit solver for coupled fluid-structure interaction problems on unstructured meshes in 3D." International Journal of High Performance Computing Applications 32, no. 2 (2016): 207–19. http://dx.doi.org/10.1177/1094342016646437.

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Fluid-structure interaction (FSI) problems are computationally very challenging. In this paper we consider the monolithic approach for solving the fully coupled FSI problem. Most existing techniques, such as multigrid methods, do not work well for the coupled system since the system consists of elliptic, parabolic and hyperbolic components all together. Other approaches based on direct solvers do not scale to large numbers of processors. In this paper, we introduce a multilevel unstructured mesh Schwarz preconditioned Newton–Krylov method for the implicitly discretized, fully coupled system of

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Shahshahani, Seyed Mohamad Reza, and Hamid Reza Mahdiani. "A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher’s Sorting Network." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 6 (2020): 1912–24. http://dx.doi.org/10.1109/tcsi.2020.2973249.

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FABRI, ANDREAS, and OLIVIER DEVILLERS. "SCALABLE ALGORITHMS FOR BICHROMATIC LINE SEGMENT INTERSECTION PROBLEMS ON COARSE GRAINED MULTICOMPUTERS." International Journal of Computational Geometry & Applications 06, no. 04 (1996): 487–506. http://dx.doi.org/10.1142/s0218195996000307.

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We present output-sensitive scalable parallel algorithms for bichromatic line segment intersection problems for the coarse grained multicomputer model. Under the assumption that n≥p2, where n is the number of line segments and p the number of processors, we obtain an intersection counting algorithm with a time complexity of [Formula: see text], where Ts(m, p) is the time used to sort m items on a p processor machine. The first term captures the time spent in sequential computation performed locally by each processor. The second term captures the interprocessor communication time. An additional

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Stillmaker, Aaron, Brent Bohnenstiehl, Lucas Stillmaker, and Bevan Baas. "Scalable energy-efficient parallel sorting on a fine-grained many-core processor array." Journal of Parallel and Distributed Computing 138 (April 2020): 32–47. http://dx.doi.org/10.1016/j.jpdc.2019.12.011.

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Ahmed, O., S. Areibi, R. Collier, and G. Grewal. "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization." International Journal of Reconfigurable Computing 2013 (2013): 1–23. http://dx.doi.org/10.1155/2013/130765.

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Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients. While a pure software implementation can generate powerful results on a server mach

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Cococcioni, Marco, Federico Rossi, Emanuele Ruffaldi, and Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE." Neural Computing and Applications 33, no. 16 (2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.

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AbstractWith the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the

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GHAREHBAGHI, Amir Masoud, and Masahiro FUJITA. "Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model." IEICE Transactions on Information and Systems E97.D, no. 4 (2014): 852–63. http://dx.doi.org/10.1587/transinf.e97.d.852.

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Rauf, Adnan, Muhammad Adeel Pasha, and Shahid Masud. "Towards design and automation of a scalable split-radix FFT processor for high throughput applications." Microprocessors and Microsystems 65 (March 2019): 148–57. http://dx.doi.org/10.1016/j.micpro.2018.12.008.

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Li, Qi, and Yan Dong Zhang. "The Design and Implementation of Core Board of Handheld Device Based on PXA320 and Linux." Applied Mechanics and Materials 65 (June 2011): 394–97. http://dx.doi.org/10.4028/www.scientific.net/amm.65.394.

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Combining with the function and characteristics of the PXA320, In view of the current existing problems of the handheld devices power and demand of high-end hand-held devices market.Design a scalable application platform for embedded general-purpose handheld devices based on PXA320 processor. First, introduces the system's hardware platform, optimizing the external interface circuit, and then discusses the software architecture of Linux operating system, On this basis, testing the data of core board by developed the corresponding application, the results show that: this platform has good relia

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Guan, Xuan, Yunsi Fei, and Hai Lin. "Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 3 (2012): 551–63. http://dx.doi.org/10.1109/tvlsi.2011.2105512.

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Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, and Jinn-Shyan Wang. "A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 5 (2012): 841–54. http://dx.doi.org/10.1109/tvlsi.2011.2119382.

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