Relevant bibliographies by topics / Spartan 3E

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  1. Journal articles
  2. Dissertations / Theses
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  4. Conference papers

Academic literature on the topic 'Spartan 3E'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Spartan 3E"

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Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.

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This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the design of 64 QAM using the Xilinx SPARTAN 6E FPGA device is 0.014W and 15.9 C/W of Effective TJA for the XILINX SPARTAN 3A DSP FPGA. The device utilization of the 64-QAM design using the XILINX SPARTAN 3A DSP is low.
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Koju, Surya Man, and Nikil Thapa. "FPGA Based Vehicle to Vehicle Communication in Spartan 3E." Journal of Science and Engineering 8 (November 12, 2020): 14–21. http://dx.doi.org/10.3126/jsce.v8i0.32858.

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This paper presents economic and reconfigurable RF based wireless communication at 2.4 GHz between two vehicles. It implements digital VLSI using two Spartan 3E FPGAs, where one vehicle receives the information of another vehicle and shares its own information to another vehicle. The information includes vehicle’s speed, location, heading and its operation, such as braking status and turning status. It implements autonomous vehicle technology. In this work, FPGA is used as central signal processing unit which is interfaced with two microcontrollers (ATmega328P). Microcontroller-1 is interfaced with compass module, GPS module, DF Player mini and nRF24L01 module. This microcontroller determines the relative position and the relative heading as seen from one vehicle to another. Microcontroller-2 is used to measure the speed of vehicle digitally. The resulting data from these microcontrollers are transmitted separately and serially through UART interface to FPGA. At FPGA, different signal processing such as speed comparison, turn comparison, distance range measurement and vehicle operation processing, are carried out to generate the voice announcement command, warning signals, event signals, and such outputs are utilized to warn drivers about potential accidents and prevent crashes before event happens.
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Mandalapu, Harinath, and B. Murali Krishna. "FPGA implementation of DS-CDMA Transmitter and Receiver." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (May 28, 2018): 179. http://dx.doi.org/10.11591/ijres.v6.i3.pp179-185.

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Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.
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Salim, Mustafa, and Rafid Ahmed. "Interfacing Force Sensor to on Board ADC of Spartan 3E." International Journal of Computer Applications 91, no. 12 (April 18, 2014): 6–10. http://dx.doi.org/10.5120/15931-5149.

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Singh, Amandeep, and Manu Bansal. "FPGA Implementation of Optimized DES Encryption Algorithm on Spartan 3E." International Journal of Scientific and Engineering Research 1, no. 1 (October 1, 2010): 13–18. http://dx.doi.org/10.14299/ijser.2010.01.003.

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Lei, Dong Ming, Ping Li, and Nian Yu Zou. "4PSK Signal Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2870–73. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2870.

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Based on the traditional demodulation method of four phase shift keying (QPSK), a QPSK demodulation model was proposed. The FPGA-based QPSK modulation and demodulation system and circuit had been achieved. In Xilinx ISE12.3 development environment, using the SPARTAN-3E development board, the simulation results demonstrate the feasibility of this design.
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Babu, D. Vijendra, and Dr N. R. Alamelu. "Implementation of Energy Efficient Integer Wavelet Transform in Spartan 3E FPGA." International Journal of Computer Applications 1, no. 12 (February 25, 2010): 49–53. http://dx.doi.org/10.5120/263-422.

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Salih, Abdulkreem Mohameed, and Ahlam Fadhil Mahmood. "Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E." Tikrit Journal of Engineering Sciences 24, no. 3 (September 30, 2017): 18–25. http://dx.doi.org/10.25130/tjes.24.2017.27.

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Salih, Abdulkreem Mohameed, and Ahlam Fadhil Mahmood. "Design and Implementation of Gray Scale JPEG CODEC on Spartan -3E." Tikrit Journal of Engineering Sciences 24, no. 3 (September 5, 2017): 15–20. http://dx.doi.org/10.25130/tjes.24.3.03.

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Moon, Sang-Ook. "Design of an FPGA-based IP Using SPARTAN-3E Embedded system." Journal of information and communication convergence engineering 9, no. 4 (August 31, 2011): 428–30. http://dx.doi.org/10.6109/jicce.2011.9.4.428.

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Dissertations / Theses on the topic "Spartan 3E"

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Gundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.

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Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, methods 1 and 2 generate a new output for every 5 clock cycles while method 3 generates an output for every 1.5 clock cycles.
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Ρώσση, Μαρία-Ευγενία. "Διερεύνηση επιδόσεων αρχιτεκτονικών υλικού-λογισμικού για εφαρμογές ψηφιακής επεξεργασίας σε FPGA." Thesis, 2012. http://hdl.handle.net/10889/5394.

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Οι συστοιχίες προγραμματιζόμενων πυλών (FPGAs) αποτελούν μια σημαντική τεχνολογία, η οποία επιτρέπει στους σχεδιαστές κυκλωμάτων την παραγωγή συγκεκριμένου σκοπού ολοκληρωμένων κυκλωμάτων σε σύντομο χρόνο. Tα σημαντικότερα των χαρακτηριστικών τους είναι η αρχιτεκτονική τους και η δυνατότητα σχεδιασμού τους μέσω υπολογιστών, η χαμηλή κατανάλωση ισχύος καθώς και το μικρό χρονικό διάστημα που απαιτείται για τον επαναπρογραμματισμό τους. Τα FPGAs είναι κατάλληλα σχεδιασμένα για ψηφιακές εφαρμογές φιλτραρίσματος. Η πυκνότητα των προγραμματιζόμενων αυτών συστημάτων είναι τέτοια ώστε πολύ μεγάλος αριθμός αριθμητικών πράξεων όπως αυτές που προκύπτουν μέσω ψηφιακού φιλτραρίσματος να μπορεί να εφαρμοστεί σε μία μόνο συσκευή. Τα πλεονεκτήματα των FPGA στην υλοποίηση ψηφιακών φίλτρων είναι μεταξύ άλλων οι υψηλότεροι ρυθμοί δειγματοληψίας από παραδοσιακούς DSP chip, το χαμηλότερο κόστος από μια μέτρια ASIC (Application Specific Integrated Circuit, Kύκλωμα οριζόμενο από εφαρμογή) για εφαρμογές μεγάλου όγκου, καθώς και η μεγαλύτερη ευελιξία από όλες τις εναλλακτικές προσεγγίσεις για την υλοποίηση των FIR φίλτρων. Σπουδαιότερο όλων είναι ότι προγραμματίζονται μέσα στο σύστημα και έχουν δυνατότητα επαναπρογραμματισμού για την υλοποίηση διαφόρων εναλλακτικών λειτουργιών φιλτραρίσματος. Στόχος της παρούσας διπλωματικής είναι να συνδυασθούν τεχνικές VLSI και ψηφιακής επεξεργασίας σήματος και μέσω κατανόησης της αρχιτεκτονικής του υπολογιστή να δημιουργηθεί μια χρήσιμη εφαρμογή. Επιλέχθηκε για τον λόγο αυτό: α) η ανάπτυξη ενός FIR φίλτρου σε γλώσσα περιγραφής υλικού, β) υλοποίησή του σε FPGA, γ) εισαγωγή αυτού σε ενσωματωμένο σύστημα και σύνδεση σε διάδρομο δεδομένων επεξεργαστή και δ) έλεγχος του φίλτρου με τη βοήθεια του επεξεργαστή μέσω γλώσσας υψηλού επιπέδου. Η συγγραφή του κώδικα του φίλτρου έγινε σε γλώσσα VHDL, με structural μεθόδους και η προσομοίωση του συστήματος στο Modelsim. Επιπροσθέτως χρησιμοποιήθηκε ο Project Navigator ISE της Xilinx για τον έλεγχο του κώδικα αλλά και τον προγραμματισμό του FPGA Spartan 3E Starter Board. Χρησιμοποιήθηκαν ακόμα τα υποπρογράμματα Plan Ahead και ChipScope Pro του ISE ώστε να ελεγχθεί η λειτουργία του κυκλώματος στο FPGA. To κύκλωμα τελικά εισάγεται σε ενσωματωμένο σύστημα με τη βοήθεια του εργαλείου σχεδίασης EDK της Xilinx και ελέγχεται η λειτουργία του προγραμματίζοντας τον επεξεργαστή Microblaze. Ακόμα ελέγχεται η λειτουργία του φίλτρου για διαφορετικούς συντελεστές FIR φίλτρων που χρησιμοποιούν διαφορετικά παράθυρα και συγκρίνονται οι «ιδανικές» τιμές που παράγονται από το Matlab με αυτές που παράγονται από το φίλτρο. Τέλος μετράται η ενέργεια (δυναμική και στατική) που καταναλώνεται κατά τη λειτουργία του κυκλώματος στο FPGA με τη βοήθεια του XPower Analyzer.
Field-programmable gate arrays (FPGAs) is a technology of great importance that allows the designers to produce specific purpose integrated circuits in a limited amount of time. The most important of their characteristics are their architecture and the ability of their design with the help of computers, the low power dissipation, as well as the need of a short amount of time to be reprogrammed. FPGAs are properly designed for digital filtering applications. The density of these programmable systems is such that a great amount of numerical calculations such as those that result via digital filtering can be applied to one device only. The advantages of FPGAs as for the implementation of digital filters is between others the great rates of sampling compared to traditional DSP chips, their low cost compared to a moderate ASIC (Application Specific Integrated Circuit) for applications that take up a large area, as well as the flexibility compared to alternative approaches for the implementation of FIR filters. Their most important characteristic is that they can be programmed on-chip and that they have the ability of being reprogrammed for the implementation of different filtering purposes. The aim of this thesis is to combine VLSI techniques and digital signal processing techniques and via the understanding of the computer architecture to create a useful application. To fulfill that purpose: a) a FIR filter was designed with the use of a hardware description language b) the filter was implemented by using an FPGA c) the filter was imported to an embedded system and it was connected to the bus of a microprocessor d) the filter was controlled by the microprocessor via a high-level programming language. The filter was designed using the VHDL language, specifically using structural methods, and its simulation was performed with Modelsim. Also the Project Navigator ISE of Xilinx was used to correct unwanted warnings and to program the FPGA Spartan 3E Starter Board. Some other subprograms of ISE were also used, such as Plan Ahead and ChipScope Pro in order to check the performance of the filter. The circuit is finally imported to an embedded system using the Embedded Developer’s Kit (EDK) of Xilinx. Microblaze was the microprocessor that was used to control the filter’s performance. Additionally, the performance of the filter is checked by using different coefficients of FIR filters by different windowing methods. The ideal values that are produced from Matlab are compared to those of the filter. Finally the power dissipation (static and dynamic) of the filter is measured using XPower Analyzer.
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Book chapters on the topic "Spartan 3E"

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Anitha, R., and V. Bagyaveereswaran. "FPGA Implementation of Braun’s Multiplier Using Spartan-3E, Virtex – 4, Virtex-5 and Virtex-6." In Trends in Network and Communications, 486–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22543-7_49.

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Anghelescu, Petre. "Cryptographic Techniques Based on Bio-Inspired Systems." In Advances in Computational Intelligence and Robotics, 59–77. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9474-3.ch003.

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In this chapter, bio-inspired techniques based on the cellular automata (CAs) and programmable cellular automata (PCAs) theory are used to develop information security systems. The proposed cryptosystem is composed from a combination of a CA as a pseudorandom number generator (PRNG) and a PCA that construct the ciphering functions of the designed enciphering scheme. It is presented how simple elements named „cells” interact between each other using certain rules and topologies to form a larger system that can be used to encrypt/decrypt data sent over network communication systems. The proposed security system was implemented in hardware in FPGA devices of type Spartan 3E – XC3S500E and was analyzed and verified, including NIST statistical tests, to assure that the system has good security and high speed. The experimental results proves that the cryptographic techniques based on bio-inspired algorithms provides an alternative to the conventional techniques (computational methods).
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Anghelescu, Petre. "Cryptographic Techniques Based on Bio-Inspired Systems." In Cryptography, 99–119. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1763-5.ch006.

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In this chapter, bio-inspired techniques based on the cellular automata (CAs) and programmable cellular automata (PCAs) theory are used to develop information security systems. The proposed cryptosystem is composed from a combination of a CA as a pseudorandom number generator (PRNG) and a PCA that construct the ciphering functions of the designed enciphering scheme. It is presented how simple elements named „cells” interact between each other using certain rules and topologies to form a larger system that can be used to encrypt/decrypt data sent over network communication systems. The proposed security system was implemented in hardware in FPGA devices of type Spartan 3E – XC3S500E and was analyzed and verified, including NIST statistical tests, to assure that the system has good security and high speed. The experimental results proves that the cryptographic techniques based on bio-inspired algorithms provides an alternative to the conventional techniques (computational methods).
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Yahya, Abid, Farid Ghani, R. Badlishah Ahmad, Mostafijur Rahman, Aini Syuhada, Othman Sidek, and M. F. M. Salleh. "Development of an Efficient and Secure Mobile Communication System with New Future Directions." In Handbook of Research on Computational Science and Engineering, 219–38. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-116-0.ch010.

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This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They are then transformed to a parity-check matrix in order to acquire the desired girth. In this work, matrices are divided into small sub-matrices, which result in improved decoding performance and reduce waiting time of the messages to be updated. Matrix sub-division increases the number of sub-matrices to be managed and memory requirement. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip.
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Conference papers on the topic "Spartan 3E"

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Popescu, S. O., A. S. Gontean, and G. Budura. "BPSK system on Spartan 3E FPGA." In 2012 IEEE 10th International Symposium on Applied Machine Intelligence and Informatics (SAMI). IEEE, 2012. http://dx.doi.org/10.1109/sami.2012.6208977.

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da Silveira, Marcilei A. G., Roberto B. B. Santos, Felipe G. H. Leite, Nicolas E. Araujo, Nilberto H. Medina, Bruno C. Porcher, Vitor A. P. Aguiar, Nemitala Added, and Fabian Vargas. "X-Ray-Induced Upsets in a Xilinx Spartan 3E FPGA." In 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS). IEEE, 2015. http://dx.doi.org/10.1109/radecs.2015.7365696.

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Huynh Viet Thang and Pham Ngoc Nam. "Prototyping of a Network-on-Chip on Spartan 3E FPGA." In 2008 Second International Conference on Communications and Electronics (ICCE). IEEE, 2008. http://dx.doi.org/10.1109/cce.2008.4578927.

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Syahbana, Muhammad A., Dionysius J. H. D. Santjojo, and Setyawan P. Sakti. "High-resolution multiple channel frequency counter using spartan-3E FPGA." In 2016 International Seminar on Sensors, Instrumentation, Measurement and Metrology (ISSIMM). IEEE, 2016. http://dx.doi.org/10.1109/issimm.2016.7803734.

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Gambin, Isabel, Ivan Grech, Owen Casha, Edward Gatt, and Joseph Micallef. "Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGA." In 2010 17th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2010). IEEE, 2010. http://dx.doi.org/10.1109/icecs.2010.5724669.

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Thakral, Shilpa, Amit Mahesh Joshi, and Unnati Mehta. "PWM waveform generation using rotary encoder on Spartan-3E starter kit." In 2017 3rd International Conference on Computational Intelligence & Communication Technology (CICT). IEEE, 2017. http://dx.doi.org/10.1109/ciact.2017.7977372.

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Sulthana, A. K. Thasleem. "Simulation and Implementation of BPSK Modulator and Demodulator System on Spartan-3E FPGA." In 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT). IEEE, 2019. http://dx.doi.org/10.1109/icssit46314.2019.8987788.

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André Luiz Marasca, Fábio Favarim, Emerson Giovani Carati, and Anderson Luiz Fernandes. "Implementação de Filtros Ativos de Potência em Dispositivos FPGA da Família Spartan 3E." In XX Seminário de Iniciação Científica e Tecnológica da UTFPR. Curitiba, PR, Brasil: Universidade Tecnológica Federal do Paraná - UTFPR, 2015. http://dx.doi.org/10.20906/cps/sicite2015-0444.

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Anusudha, K., and Gopi Chand Naguboina. "Design and implementation of PAL and PLA using reversible logic on FPGA SPARTAN 3E." In 2017 Fourth International Conference on Signal Processing,Communication and Networking (ICSCN). IEEE, 2017. http://dx.doi.org/10.1109/icscn.2017.8085646.

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Reddy Jeeru, Dinesh, K. Panduranga Vittal, Anikethan H V U, and Anjana S. Kumar. "Implementation of Enhanced Parallel port interface for Frequency analysis in a configurable Ring Oscillator PUF circuits on Xilinx Spartan 3E architecture." In 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2019. http://dx.doi.org/10.1109/conecct47791.2019.9012874.

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