Relevant bibliographies by topics / Spartan 3E / Journal articles
To see the other types of publications on this topic, follow the link: Spartan 3E.

Journal articles on the topic 'Spartan 3E'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Spartan 3E.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.

Full text
Abstract:
This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the design of 64 QAM using the Xilinx SPARTAN 6E FPGA device is 0.014W and 15.9 C/W of Effective TJA for the XILINX SPARTAN 3A DSP FPGA. The device utilization of the 64-QAM design using the XILINX SPARTAN 3A DSP is low.
APA, Harvard, Vancouver, ISO, and other styles
2

Koju, Surya Man, and Nikil Thapa. "FPGA Based Vehicle to Vehicle Communication in Spartan 3E." Journal of Science and Engineering 8 (November 12, 2020): 14–21. http://dx.doi.org/10.3126/jsce.v8i0.32858.

Full text
Abstract:
This paper presents economic and reconfigurable RF based wireless communication at 2.4 GHz between two vehicles. It implements digital VLSI using two Spartan 3E FPGAs, where one vehicle receives the information of another vehicle and shares its own information to another vehicle. The information includes vehicle’s speed, location, heading and its operation, such as braking status and turning status. It implements autonomous vehicle technology. In this work, FPGA is used as central signal processing unit which is interfaced with two microcontrollers (ATmega328P). Microcontroller-1 is interfaced with compass module, GPS module, DF Player mini and nRF24L01 module. This microcontroller determines the relative position and the relative heading as seen from one vehicle to another. Microcontroller-2 is used to measure the speed of vehicle digitally. The resulting data from these microcontrollers are transmitted separately and serially through UART interface to FPGA. At FPGA, different signal processing such as speed comparison, turn comparison, distance range measurement and vehicle operation processing, are carried out to generate the voice announcement command, warning signals, event signals, and such outputs are utilized to warn drivers about potential accidents and prevent crashes before event happens.
APA, Harvard, Vancouver, ISO, and other styles
3

Mandalapu, Harinath, and B. Murali Krishna. "FPGA implementation of DS-CDMA Transmitter and Receiver." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (May 28, 2018): 179. http://dx.doi.org/10.11591/ijres.v6.i3.pp179-185.

Full text
Abstract:
Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.
APA, Harvard, Vancouver, ISO, and other styles
4

Salim, Mustafa, and Rafid Ahmed. "Interfacing Force Sensor to on Board ADC of Spartan 3E." International Journal of Computer Applications 91, no. 12 (April 18, 2014): 6–10. http://dx.doi.org/10.5120/15931-5149.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Singh, Amandeep, and Manu Bansal. "FPGA Implementation of Optimized DES Encryption Algorithm on Spartan 3E." International Journal of Scientific and Engineering Research 1, no. 1 (October 1, 2010): 13–18. http://dx.doi.org/10.14299/ijser.2010.01.003.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Lei, Dong Ming, Ping Li, and Nian Yu Zou. "4PSK Signal Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2870–73. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2870.

Full text
Abstract:
Based on the traditional demodulation method of four phase shift keying (QPSK), a QPSK demodulation model was proposed. The FPGA-based QPSK modulation and demodulation system and circuit had been achieved. In Xilinx ISE12.3 development environment, using the SPARTAN-3E development board, the simulation results demonstrate the feasibility of this design.
APA, Harvard, Vancouver, ISO, and other styles
7

Babu, D. Vijendra, and Dr N. R. Alamelu. "Implementation of Energy Efficient Integer Wavelet Transform in Spartan 3E FPGA." International Journal of Computer Applications 1, no. 12 (February 25, 2010): 49–53. http://dx.doi.org/10.5120/263-422.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Salih, Abdulkreem Mohameed, and Ahlam Fadhil Mahmood. "Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E." Tikrit Journal of Engineering Sciences 24, no. 3 (September 30, 2017): 18–25. http://dx.doi.org/10.25130/tjes.24.2017.27.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Salih, Abdulkreem Mohameed, and Ahlam Fadhil Mahmood. "Design and Implementation of Gray Scale JPEG CODEC on Spartan -3E." Tikrit Journal of Engineering Sciences 24, no. 3 (September 5, 2017): 15–20. http://dx.doi.org/10.25130/tjes.24.3.03.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Moon, Sang-Ook. "Design of an FPGA-based IP Using SPARTAN-3E Embedded system." Journal of information and communication convergence engineering 9, no. 4 (August 31, 2011): 428–30. http://dx.doi.org/10.6109/jicce.2011.9.4.428.

Full text
APA, Harvard, Vancouver, ISO, and other styles
11

Younis, Dr Basma MohammedKamal, and Dua’a Basman Younis. "Fuzzy Image Processing Based Architecture for Contrast Enhancement in Diabetic Retinopathy Images." International Journal of Computer Engineering and Information Technology 12, no. 4 (April 30, 2020): 26–30. http://dx.doi.org/10.47277/ijceit/12(4)1.

Full text
Abstract:
Diabetic retinopathy” is damage to retina denotes one of the problems of diabetes which is a significant reason for visual infirmity and blindness. A comprehensive and routine eye check is important to early detection and rapid treatment. This study proposes a hardware system that can enhance the contrast in the diabetic retinopathy eye fundus images as a first step in different eye disease diagnoses. The fuzzy histogram equalization technique is proposed to increases the local contrast of Diabetic Retinopathy Images. First, a histogram construction hardware architecture for different image processing purposes has been built then modified with fuzzy techniques to create fuzzy histogram equalization architecture, which is used to enhance the original images. Both architectures are designed using a finite-state machine (FSM) technique and programmed with VHDL programming language. The first one is implemented using two (Spartan 3E-XC3S500 and Xilinx Artix-7 XC7A100T) kits, while the second architecture is implemented using (Spartan 3E-XC3S500) kit. The system consists also of a modified video graphics array (VGA) port to display the input and resulted images with a proper resolution. All the hardware outputs are compared to that results produce from MatLab for verification and the resulted images are tested by PSNR, MSE, ENTROPY ,and AMBE
APA, Harvard, Vancouver, ISO, and other styles
12

Da Silva, Thaísa L., Luis A. S. Cruz, and Luciano V. Agostini. "A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 43–49. http://dx.doi.org/10.29292/jics.v6i1.337.

Full text
Abstract:
The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution.The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.
APA, Harvard, Vancouver, ISO, and other styles
13

Muslim, Imaduddin Amrullah, R. Rizal Isnanto, and Eko Didik Widianto. "Perancangan dan Implementasi Algoritma DES untuk Mikroprosesor Enkripsi dan Dekripsi pada FPGA." Jurnal Teknologi dan Sistem Komputer 3, no. 2 (April 20, 2015): 259. http://dx.doi.org/10.14710/jtsiskom.3.2.2015.259-266.

Full text
Abstract:
Seiring dengan semakin luasnya penerapan teknologi komputasi di sekitar kita, menjadikan informasi menjadi sangat mudah dan cepat untuk disebarkan. Kita dapat mengakses informasi dan data-data yang kita butuhkan dengan mudah. Namun permasalahan yang kita hadapi saat ini kerhasiaan informasi menjadi sangat riskan. Oleh karena itu Sistem keamanan merupakan hal penting yang perlu diperhatikan dalam mengembangkan suatu sistem komputer hal ini lah yang menjadikan enkripsi dan dekripsi data menjadi hal yang penting. Modul rancangan IP Core ini dirancang menggunakan aplikasi Xilinx ISE Design Suite 12.4. Kemudian rancangan IP Core ini diimplementasikan pada papan Xilinx FPGA Spartan-3E XC3S500E-4FG320C dari keluarga Xilinx FPGA Spartan-3E dengan 500K sistem gerbang. Verifikasi fungsional dari IP Core yang dirancang menggunakan testbench dan simulasi diagram pewaktuan menggunakan aplikasi Xilinx ISE Simulator. Tugas akhir ini ditujukan untuk mengembangkan IP Core yang mampu menjalankan fungsi enkripsi DES (Data Encryption Standard) dan ditulis menggunakan bahasa Verilog. Implementasi algoritma enkripsi dan dekripsi algoritma DES telah berhasil dilakukan. Hasil analisis menunjukkan sistem telah dapat melakukan enkripsi dan dekripsi data sesuai dengan spesifikasi algoritma DES. Sebaiknya penelitian ini dikembangkan kembali dengan menguji sistem untuk melakukan transmisi data berupa file ataupun teks. Selain itu juga perlu meningkatkan unjuk kerja sistem dengan optimasi sumber daya dan kecepatan waktu proses pada perancangan rekonstruksi kode verilog.
APA, Harvard, Vancouver, ISO, and other styles
14

Antonio Álvarez, J., and Michael Lindig B. "Diseño de un Coprocesador Matemático de Precisión Simple usando el Spartan 3E." Polibits 38 (December 31, 2008): 81–89. http://dx.doi.org/10.17562/pb-38-10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
15

Becker, Tobias, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, and Tero Rissa. "Power Characterisation for Fine-Grain Reconfigurable Fabrics." International Journal of Reconfigurable Computing 2010 (2010): 1–9. http://dx.doi.org/10.1155/2010/787405.

Full text
Abstract:
This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.
APA, Harvard, Vancouver, ISO, and other styles
16

Rajeswaran, N., T. Madhu, and M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits." Applied Mechanics and Materials 367 (August 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.

Full text
Abstract:
Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.
APA, Harvard, Vancouver, ISO, and other styles
17

León, Danilo, Bryan Quinga, Kathy Salgado, Alexis Vizuete, and Darwin Alulema. "Sistema de gestión de recursos para la tarjeta Spartan 3E 500 con Labview." MASKAY 4, no. 1 (November 1, 2014): 28. http://dx.doi.org/10.24133/maskay.v4i1.137.

Full text
Abstract:
El presente artículo muestra un resumen de las características principales del módulo LabVIEW-FPGA, su utilización y las ventajas de usar LABVIEW como software para la programación de FPGA, también la ejecución y programación de recursos de la tarjeta FPGA Spartan 3E donde se utilizan varios de sus módulos. Para mostrar el uso de los módulos de la FPGA con este software se realizó una aplicación que permite controlar la velocidad y el sentido de giro de un servomotor en base a una señal analógica, además se muestran los resultados tanto en la LCD de la tarjeta como en una pantalla VGA.
APA, Harvard, Vancouver, ISO, and other styles
18

Singh, Ramandeep. "Comparison between Spartan-3E and Virtex-6 Technologies on FPGA for UART Transmission." British Journal of Mathematics & Computer Science 4, no. 9 (January 10, 2014): 1240–45. http://dx.doi.org/10.9734/bjmcs/2014/7539.

Full text
APA, Harvard, Vancouver, ISO, and other styles
19

Babu T, Narendra, Fazal Noorbasha, and Leenendra Chowdary Gunnam. "Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 2 (April 1, 2016): 602. http://dx.doi.org/10.11591/ijece.v6i2.9267.

Full text
Abstract:
In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.
APA, Harvard, Vancouver, ISO, and other styles
20

Babu T, Narendra, Fazal Noorbasha, and Leenendra Chowdary Gunnam. "Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 2 (April 1, 2016): 602. http://dx.doi.org/10.11591/ijece.v6i2.pp602-610.

Full text
Abstract:
In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.
APA, Harvard, Vancouver, ISO, and other styles
21

Kodýtek, Filip, and Róbert Lórencz. "Proposal and Properties of Ring Oscillator-Based PUF on FPGA." Journal of Circuits, Systems and Computers 25, no. 03 (December 28, 2015): 1640016. http://dx.doi.org/10.1142/s0218126616400168.

Full text
Abstract:
This paper deals with design of physical unclonable functions (PUFs) based on field-programmable gate array (FPGA). The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. Therefore, a design of a ring oscillator (RO)-based PUF producing more output bits from each RO pair is presented. 24 Digilent Basys 2 FPGA boards (Spartan-3E) and 6 Digilent Nexys 3 FPGA boards (Spartan-6) were tested and statistically evaluated indicating suitability of the proposed design for device identification. A stable PUF output is required for generating cryptographic keys. As post-processing technique to further improve the efficiency of this PUF design, we used Gray code on the obtained bits from RO pairs. Ultimately, the PUF design is combined with error correction code and together with Gray code is able to generate cryptographic keys of sufficient length.
APA, Harvard, Vancouver, ISO, and other styles
22

Godek, Juliusz, Ryszard Golański, Jacek Kołodziej, and Jacek Stępień. "New Synchronization Method for Transmission Systems with Variable Length of Bits." International Journal of Electronics and Telecommunications 61, no. 1 (March 1, 2015): 31–36. http://dx.doi.org/10.1515/eletel-2015-0004.

Full text
Abstract:
Abstract Based on the Spartan 3E evaluation module, a flexible platform for the implementation of different algorithms for A/D conversion was developed. The aim of presented work was to improve the concept of the sampling rate adaptation to the input signal rate of change in terms of practical issues including synchronization of delta codecs. The new, original synchronization method, useful in systems dedicated for transmission of variable duration of bits was proposed and experimentally verified. Performed measures and observations have shown elimination of the synchronization lose phenomenon
APA, Harvard, Vancouver, ISO, and other styles
23

EL GOURI, Rachid, Wassima Ait Ahmed, Ahmed Lichioui, and Laamari Hlou. "Conception and Implementation of a BCH Code on a FPGA Board." International Journal of Engineering & Technology 2, no. 4 (November 28, 2013): 293. http://dx.doi.org/10.14419/ijet.v2i4.1430.

Full text
Abstract:
In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.
APA, Harvard, Vancouver, ISO, and other styles
24

Petrovic, Miljan, and Milica Jovanovic. "Realization of universal periodic sequence generator on FPGA." Serbian Journal of Electrical Engineering 13, no. 1 (2016): 59–70. http://dx.doi.org/10.2298/sjee1601059p.

Full text
Abstract:
This paper presents mathematical modeling and performance evaluation of different realizations of universal periodic digital signal generator based on infinite impulse response filter. The development kit used was Spartan 3E-Starter Board. Using Xilinx software environment and VHDL, the generator has been described and then synthesized and implemented on FPGA chip on the board. Included realizations are direct form II (canonical form) of the filter, as well as hardware optimized single register structure with different control mechanism. Comparative analysis of these two digital systems points to their differences, advantages and weaknesses.
APA, Harvard, Vancouver, ISO, and other styles
25

Mahmoud, Mohamed Ibrahim, Sayed Mohamed El-Araby, Safey Ahmed Shehata, Refaat Mohamed Fikry AbouZaid, and Fathi Abd El-Samie. "Design and Implementation of a Fast General Purpose Fuzzy Processor." International Journal of System Dynamics Applications 2, no. 4 (October 2013): 1–18. http://dx.doi.org/10.4018/ijsda.2013100101.

Full text
Abstract:
In this paper, a Fast Fuzzy processor (FP) is proposed. This processor, which is implemented using FPGA, has four inputs and one output with 8-bits width for each. The proposed processor is synthesized, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) and is tested using Xilinx Spartan 3E starter kit. A PC Graphical User Interface (GUI) is programmed using C# programming language to select and download the parameters of the processor through the serial port communication. The proposed processor is experimentally tested through water sprinkler system example. The experimental results approve the excellent performance of the proposed processor.
APA, Harvard, Vancouver, ISO, and other styles
26

Wang, Yu Duo. "Study on Mechanical Automation with X-Ray Power Conveyor Belt Nondestructive Detection System Design." Advanced Materials Research 738 (August 2013): 256–59. http://dx.doi.org/10.4028/www.scientific.net/amr.738.256.

Full text
Abstract:
In order to real-time automation detection of conveyor belt running status, found the mechanical fault in time and processing, to ensure mechanical automation reliable and safe operation, to avoid major accidents. This paper designed a kind of X-ray power conveyor belt nondestructive detection system of the detector, Proposed design scheme based on FPGA + ARM detector; Adopts Xilinx companys cost-effective FPGA chip Spartan-3E and Samsung launched using 32-bit RISC microprocessor of ARM chips S3C2440A, Design the hardware circuit of detector; And has carried on the experiment and debugging, has reached the design requirements.
APA, Harvard, Vancouver, ISO, and other styles
27

Raj Narain, B., and Dr T. Sasilatha. "Implementation of reconfigurable galois field multipliers over2m using primitive polynomials." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.12.11356.

Full text
Abstract:
The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.
APA, Harvard, Vancouver, ISO, and other styles
28

Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 213. http://dx.doi.org/10.11591/ijres.v4.i3.pp213-218.

Full text
Abstract:
Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.
APA, Harvard, Vancouver, ISO, and other styles
29

Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

Full text
Abstract:
In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.
APA, Harvard, Vancouver, ISO, and other styles
30

Mohammad, Imran, and Ramananjaneyulu K. "FPGA Implementation of a 64-Bit RISC Processor Using VHDL." International Journal of Reconfigurable and Embedded Systems (IJRES) 1, no. 2 (July 1, 2012): 59. http://dx.doi.org/10.11591/ijres.v1.i2.pp59-66.

Full text
Abstract:
In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.<em> </em>
APA, Harvard, Vancouver, ISO, and other styles
31

Bespalov, Nikolay, and Yury Goryachkin. "Device for Current Test Pulse Development Through a Diode in a Direct Direction." International Journal of Engineering & Technology 7, no. 3.19 (September 7, 2018): 81. http://dx.doi.org/10.14419/ijet.v7i3.19.16991.

Full text
Abstract:
The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.
APA, Harvard, Vancouver, ISO, and other styles
32

Zeebaree, Subhi R. M. "DES encryption and decryption algorithm implementation based on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (May 1, 2020): 774. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp774-781.

Full text
Abstract:
Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.
APA, Harvard, Vancouver, ISO, and other styles
33

Ali, Fakhrulddin, Mohammed Hussein, and Sinan Ismael. "LabVIEW FPGA Implementation Of a PID Controller For D.C. Motor Speed Control." Iraqi Journal for Electrical and Electronic Engineering 6, no. 2 (December 1, 2010): 139–44. http://dx.doi.org/10.37917/ijeee.6.2.9.

Full text
Abstract:
This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.
APA, Harvard, Vancouver, ISO, and other styles
34

Gopal, P. Bala, and K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

Full text
Abstract:
A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
APA, Harvard, Vancouver, ISO, and other styles
35

Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic." Journal of Communications Software and Systems 11, no. 2 (June 23, 2015): 104. http://dx.doi.org/10.24138/jcomss.v11i2.109.

Full text
Abstract:
Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.
APA, Harvard, Vancouver, ISO, and other styles
36

Vashishtha, Shalini, and Rekha K. R. "Modified digital space vector pulse width modulation realization on low-cost FPGA platform with optimization for 3-phase voltage source inverter." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 4 (August 1, 2021): 3629. http://dx.doi.org/10.11591/ijece.v11i4.pp3629-3638.

Full text
Abstract:
The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, modified digital space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The modified digital space vector pulse width modulation (DSVPWM) uses a phase-locked loop (PLL) to generate clocks using the digital clock manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the three-phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The modified DSVPWM is synthesized and implemented on Spartan-3E FPGA. The modified DSVPWM utilizes 17% slices, works at 102.45 MHz, and consumes 0.070 W total power. The simulation results and the resource utilization of modified DSVPWM are represented in detail. The modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvement
APA, Harvard, Vancouver, ISO, and other styles
37

Agarwal, Charul, Ashutosh Gupta, and Haneet Rana. "Performance Analysis and FPGA Implementation of Digital PID Controller for Speed Control of DC Motor." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (June 10, 2013): 638–45. http://dx.doi.org/10.24297/ijct.v7i3.3443.

Full text
Abstract:
This paper deals with the performance analysis and implementation of PID(Proportional-Integral-Derivative) Controller on FPGA platform.The hardware implementation has been done on Xilinx Spartan 3E FPGA board.The software implementation has been done using Xilinx ISE 8.1i as a tool and simulation is performed using ModelSim 5.4a as a simulator.The PWM signal is generated by FPGA board,which further given to dc motor for its speed control. A new technique has been introduced for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has been presented in this paper. Performance analysis of PID controller using MATLAB software shows the effectiveness of the proposed method.
APA, Harvard, Vancouver, ISO, and other styles
38

Palanidoss, Sriramalakshmi, and Sreedevi V.T. "Experimental Verification of Three phase quasi Switched Boost Inverter with an Improved PWM Control." International Journal of Power Electronics and Drive Systems (IJPEDS) 10, no. 3 (September 1, 2019): 1500. http://dx.doi.org/10.11591/ijpeds.v10.i3.pp1500-1509.

Full text
Abstract:
<p>In this paper, an experimental investigation of a three phase quasi Switched Boost Inverter (qSBI) topology is proposed and analysed with an improved Pulse Width Modulation strategy. The qSBI is capable of providing both boost and inversion actions in a single stage. The improved PWM control technique can provide a higher boost with the reduced duty ratio. The theoretical analysis presented in this work is validated using an experimental set up of 100W qSBI topology and hardware results are shown for verification. The improved PWM strategy is implemented and firing pulses are generated in FPGA SPARTAN 3E kit. With the duty ratio of 0.05, the peak ac load voltage of 80 V is obtained. The performance of three phase qSBI is analysed with both conventional PWM strategy and improved PWM strategy. The observations are presentated in detail.</p>
APA, Harvard, Vancouver, ISO, and other styles
39

Sudha, L. U., J. Baskaran, and S. A. Elankurisil. "FPGA Techniques Based New Hybrid Modulation Strategies for Voltage Source Inverters." Scientific World Journal 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/490151.

Full text
Abstract:
This paper corroborates three different hybrid modulation strategies suitable for single-phase voltage source inverter. The proposed method is formulated using fundamental switching and carrier based pulse width modulation methods. The main tale of this proposed method is to optimize a specific performance criterion, such as minimization of the total harmonic distortion (THD), lower order harmonics, switching losses, and heat losses. The proposed method is articulated using fundamental switching and carrier based pulse width modulation methods. Thus, the harmonic pollution in the power system will be reduced and the power quality will be augmented with better harmonic profile for a target fundamental output voltage. The proposed modulation strategies are simulated in MATLAB r2010a and implemented in a Xilinx spartan 3E-500 FG 320 FPGA processor. The feasibility of these modulation strategies is authenticated through simulation and experimental results.
APA, Harvard, Vancouver, ISO, and other styles
40

T. Gadawe, Nour, and Sahar L. Qaddoori. "Design and implementation of smart traffic light controller using VHDL language." International Journal of Engineering & Technology 8, no. 4 (December 15, 2019): 596. http://dx.doi.org/10.14419/ijet.v8i4.29478.

Full text
Abstract:
The purpose of this paper is to design and implementation of smart traffic light controller system using VHDL language and FPGA. A structure of four road intersection has been selected. The intersection to be controlled is between a busy (main street), and somewhat less busy (side street), with sensor for the side street and walk request button. Also, the system contains switches to control the traffic light manually. The intersection uses four timing parameters with ability to change these parameters manually. The system has been successfully tested with VHDL using Xilinx ISE 14.7i software environment and Chip-Scope, while, it is implemented in hardware using Xilinx Spartan 3E FPGA. It is easy to use and the cost for the same is also less as compared to the others. The designed traffic light control system is presented to work correctly as predictable.
APA, Harvard, Vancouver, ISO, and other styles
41

Guo, Fei, and Xiao Luo. "Research and Realization of Hardware Back-Propagation Neural Network Based on FPGA." Applied Mechanics and Materials 333-335 (July 2013): 2469–74. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.2469.

Full text
Abstract:
In order to meet the requirements of real-time and embedded of industrial field, a reconfigurable Back-Propagation neural network based on FPGA has been implemented on Xilinx's Spartan-3E (XC3S250E) chip which has 250000 gate. First the optimal network structure and weights were gotten by a variable structure of BP neural network algorithm. Then an improved hardware approaching method of excitation function was put forward, and the maximum error was 1.58% by simulation and comparative analysis on the error. Finally hardware co-imitation and timing simulation was token based on a reasonable choice of data accuracy, and then the hardware BP neural network algorithm was been downloaded and implemented on FPGA. This method has better accuracy and speed, it is an effective method of BP neural network modeling based on hardware, and lays the foundation for the hardware realization of other neural network and embedded image processing.
APA, Harvard, Vancouver, ISO, and other styles
42

Rudnicki, Tomasz. "Measurement of the PMSM Current with a Current Transducer with DSP and FPGA." Energies 13, no. 1 (January 2, 2020): 209. http://dx.doi.org/10.3390/en13010209.

Full text
Abstract:
In the present work, two approaches for the phase current measurement of a permanent magnet synchronous motor (PMSM) were compared. The measured phase current was distorted by glitches, and a software method to eliminate these glitches was necessary. An averaging of samples was carried out, and the experimental results indicated that averaging was essential for further calculations. Moreover, the PMSM operated smoothly, and the difference between the set point and the actual speed was reduced for the full range of loads from the free run up to a full load. The increasing popularity of field-programmable gate array (FPGA) devices has encouraged developments in PMSM controllers using a direct hardware approach and the classic software approach utilizing a digital signal processor unit. In this study, the selected performance of TMS320F2812 and Spartan-3E were compared. This paper proposes an original adaptive correction method for a current transducer.
APA, Harvard, Vancouver, ISO, and other styles
43

Singhal, Akarshika, Anjana Goen, and Tanu Trushna Mohapatrara. "Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code." International Journal of Emerging Research in Management and Technology 6, no. 8 (June 25, 2018): 268. http://dx.doi.org/10.23956/ijermt.v6i8.150.

Full text
Abstract:
The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture.
APA, Harvard, Vancouver, ISO, and other styles
44

D, Karthikeyan, Vijayakumar K, and Jagabar M. "Generalized Cascaded Symmetric and Level Doubling Multilevel Converter Topology with Reduced THD for Photovoltaic Applications." Electronics 8, no. 2 (February 1, 2019): 161. http://dx.doi.org/10.3390/electronics8020161.

Full text
Abstract:
In this paper, two different converter topologies for a basic new switched capacitor diode converter with a reduced number of power electronics components, suitable for grid connected photovoltaic applications were proposed. The two different structures of switched diode multilevel converter proposed were: (i) cascaded switched diode and (ii) cascaded switched diode with doubling circuit. The switched-diode multilevel converter was compared with other recent converters. In addition, a new dc offset nearest level modulation technique was proposed. This proposed dc offset technique offers low voltage total harmonic distortion (THD) and high RMS output voltage. The proposed modulation technique was compared with conventional nearest level modulation (NLM) and modified NLM control techniques. The performance of the proposed dc offset modulation technique was implemented using a FPGA Spartan 3E controller and tested with a novel switched capacitor-diode multilevel converter. However, to prove the authenticity of the switched-diode multilevel converter and modulation technique, a laboratory-based prototype model for 7-level and 13-level converters was developed.
APA, Harvard, Vancouver, ISO, and other styles
45

Singh, Rachna, and Arvind Rajawat. "Analytical Model for High–Level Area Estimation of FPGA Design." International Journal of Embedded and Real-Time Communication Systems 7, no. 2 (July 2016): 35–44. http://dx.doi.org/10.4018/ijertcs.2016070103.

Full text
Abstract:
FPGAs have been used as a target platform because they have increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach. A mathematical model has been presented that estimates the maximum number of LUTs consumed by the hardware synthesized for different FPGAs using LLVM.. The motivation behind this research work is to design an area modeling approach for FPGA based implementation at an early stage of design. The equation based area estimation model permits immediate and accurate estimation of resources. Two important criteria used to judge the quality of the results were estimation accuracy and runtime. Experimental results show that estimation error is in the range of 1.33% to 7.26% for Spartan 3E, 1.6% to 5.63% for Virtex-2pro and 2.3% to 6.02% for Virtex-5.
APA, Harvard, Vancouver, ISO, and other styles
46

N, Bharatesh, and Rohith S. "FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 3 (November 1, 2013): 99. http://dx.doi.org/10.11591/ijres.v2.i3.pp99-105.

Full text
Abstract:
There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.
APA, Harvard, Vancouver, ISO, and other styles
47

Oukili, Soufiane, and Seddik Bri. "High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 298. http://dx.doi.org/10.11591/ijece.v6i1.8388.

Full text
Abstract:
<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>
APA, Harvard, Vancouver, ISO, and other styles
48

Oukili, Soufiane, and Seddik Bri. "High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 298. http://dx.doi.org/10.11591/ijece.v6i1.pp298-306.

Full text
Abstract:
<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>
APA, Harvard, Vancouver, ISO, and other styles
49

Thangaraja, M., K. Suresh Manic, and S. Uma. "Industrial Automation Using Wireless Mesh Network." Applied Mechanics and Materials 367 (August 2013): 417–21. http://dx.doi.org/10.4028/www.scientific.net/amm.367.417.

Full text
Abstract:
The use of wireless technology in industrial automation offers a number of potential benefits, from the obvious cost reduction brought about by the elimination of wiring to the availability of better plant information, improved productivity and better asset management. However, its practical implementation faces a number of challenges: lack of a universally agreed standard, security, noisy environment, reliability. Since there is no IEEE standard for using wireless technology in industrial automation it is not possible to use the conventional industrial automation system. We also need better transmission rate for reliable communication. In this paper we proposed an industrial automation system based on wireless multi hop network using FPGA. The multi hop network will provide the reliable communication to central control unit and FPGA will provide the reconfigurable high speed data communication. The design is implemented in Xilinx Spartan 3E FAGA kit and results shows that it will be the solution for future industrial automation problems.
APA, Harvard, Vancouver, ISO, and other styles
50

Bhuyan, Kanhu Charan, Sumit Kumar Sao, and Kamalakanta Mahapatra. "An FPGA Based Controller for a SOFC DC-DC Power System." Advances in Power Electronics 2013 (December 28, 2013): 1–12. http://dx.doi.org/10.1155/2013/345646.

Full text
Abstract:
Fuel cells are an attractive option for alternative power and of use in a variety of applications. This paper proposes a state space model for the solid oxide fuel cell (SOFC) based power system that comprises fuel cell, DC-DC buck converter, and load. In this investigation we have taken up a case study for SOFC feeding a DC load where a DC-DC buck converter acts as the interface between the load and the source. A proportional-integral (PI) controller is used in conjunction with pulse width modulation (PWM) that computes the pulse width and switches the MOSFET at the right instant so that the desired voltage is obtained. The proposed model is validated through extensive simulation using MATLAB/SIMULINK. Controller for the fuel cell power system (FCPS) is prototyped using XC3S500E development board containing a SPARTAN 3E Xilinx FPGA that simplifies the entire control circuit besides providing additional flexibility for further improvement. The results clearly indicate improved performance and validate our proposed model.
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography