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Relevant bibliographies by topics / Square Root Carry Select Adder

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Academic literature on the topic 'Square Root Carry Select Adder'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Square Root Carry Select Adder"

1

K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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4

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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B, S. Premananda, Bajpai Archit, Shakthivel G, and R. Anurag A. "Low power add-one circuit IPGL based high speed square root carry select adder." Indian Journal of Science and Technology 14, no. 9 (2021): 776–86. https://doi.org/10.17485/IJST/v14i9.343.

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Abstract <strong>Background:</strong> An adder is the basic building block of any circuitry. Most ripple carry adders suffer from carry rippling which constrains its performance due to increased delay though they occupy less area. <strong>Objectives:</strong> To design and implement a high speed adder to overcome the carry rippling, which should consume less power and also operate at higher frequency. <strong>Method:</strong> Squareroot CSLA architecture is designed by replacing ripple carry adder with of Add- One Circuit (AOC) to minimize the area and carry rippling d

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You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C

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Kokilavani, V., K. Preethi, and P. Balasubramanian. "FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders." Advances in Electronics 2015 (May 27, 2015): 1–13. http://dx.doi.org/10.1155/2015/713843.

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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work,

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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Sathyanarayan, Pavitha Uppinakere, Mamtha Mohan, Sandeep Kakde, and Annam Karhik. "Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 172–83. https://doi.org/10.11591/ijeecs.v26.i1.pp172-183.

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The adder is the maximum usually used mathematics block in programs inclusive of central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety

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A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del

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Book chapters on the topic "Square Root Carry Select Adder"

1

Ganavi, M. G., and B. S. Premananda. "Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier Using Adiabatic Logic." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5802-9_67.

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Ykuntam, Yamini Devi, and M. Rajan Babu. "A Novel Architecture of High-Speed and Area-Efficient Wallace Tree Multiplier Using Square Root Carry Select Adder with Mirror Adder." In Lecture Notes in Networks and Systems. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3765-9_33.

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Lyn, Poh Yuin, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, and Muhammad Firdaus Akbar. "Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC)." In Proceedings of the 12th International Conference on Robotics, Vision, Signal Processing and Power Applications. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-9005-4_18.

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Jain, Ginni, Keerti Vyas, Vijendra K. Maurya, and Mayank Patel. "Comparative Analysis of Different Architectures of MCML Square Root Carry Select Adders for Low-Power Applications." In Advances in Intelligent Systems and Computing. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0135-2_29.

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Conference papers on the topic "Square Root Carry Select Adder"

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Sankanatti, Suneel, and S. Praveen. "Physical Implementation of Square-Root-Carry-Select-Adder." In 2021 6th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2021. http://dx.doi.org/10.1109/icces51350.2021.9489051.

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Subramanyam, Radha, Venkata Aniruddh Kalyan Talluri, P. Venkata Lavanya, K. Y. Nisheeth Charan Reddy, J. Sunitha Kumari, and P. Nagabushanam. "Carry Select Adder Using Square Root Techniques in Ripple Carry and BCD Adders." In 2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT). IEEE, 2024. http://dx.doi.org/10.1109/csnt60213.2024.10546043.

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Kavipriya, P., S. Lakshmi, T. Vino, M. R. Ebenezar Jebarani, and G. Jegan. "Booth Multiplier Design Using Modified Square Root Carry-Select-Adder." In 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS). IEEE, 2021. http://dx.doi.org/10.1109/icais50930.2021.9396032.

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Akhter, Shamim, Saurabh Chaturvedi, and Kilari Pardhasardi. "CMOS implementation of efficient 16-Bit square root carry-select adder." In 2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2015. http://dx.doi.org/10.1109/spin.2015.7095289.

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Paradhasaradhi, Damarla, M. Prashanthi, and N. Vivek. "Modified wallace tree multiplier using efficient square root carry select adder." In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE). IEEE, 2014. http://dx.doi.org/10.1109/icgccee.2014.6922214.

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Kamble, Chetan, Siddharth R. K., Shivnarayan Patidar, Vasantha M. H., and Nithin Kumar Y. B. "Design of Area-Power-Delay Efficient Square Root Carry Select Adder." In 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). IEEE, 2018. http://dx.doi.org/10.1109/ises.2018.00026.

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Sushmitha, M., K. Jamal, M. Kiran, O. V. P. Kumar Manchalla, and Ch Pratyusha Chowdari. "MDCLCG with Square Root Carry Select Adder Technique for Hardware Security." In 2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS). IEEE, 2022. http://dx.doi.org/10.1109/icaiss55157.2022.10010741.

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Sankanatti, Suneel, and S. Praveen. "Design and synthesis of Karatsuba multiplier using Square root carry select adder (SRCSA)." In 2021 6th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2021. http://dx.doi.org/10.1109/icces51350.2021.9489005.

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Das, Adyasha, Sushanta K. Mandal, and Jitendra K. Das. "High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology." In 2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO). IEEE, 2015. http://dx.doi.org/10.1109/eesco.2015.7253977.

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Gupta, Kirti, Radhika, Neeta Pandey, and Maneesha Gupta. "A novel high speed MCML square root carry select adder for mixed-signal applications." In 2013 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT). IEEE, 2013. http://dx.doi.org/10.1109/mspct.2013.6782117.

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