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Journal articles on the topic 'Square Root Carry Select Adder'

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Published: 2 June 2025

Last updated: 31 July 2025

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1

K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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2

Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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3

Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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4

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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5

B, S. Premananda, Bajpai Archit, Shakthivel G, and R. Anurag A. "Low power add-one circuit IPGL based high speed square root carry select adder." Indian Journal of Science and Technology 14, no. 9 (2021): 776–86. https://doi.org/10.17485/IJST/v14i9.343.

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Abstract <strong>Background:</strong> An adder is the basic building block of any circuitry. Most ripple carry adders suffer from carry rippling which constrains its performance due to increased delay though they occupy less area. <strong>Objectives:</strong> To design and implement a high speed adder to overcome the carry rippling, which should consume less power and also operate at higher frequency. <strong>Method:</strong> Squareroot CSLA architecture is designed by replacing ripple carry adder with of Add- One Circuit (AOC) to minimize the area and carry rippling d

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6

You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C

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7

Kokilavani, V., K. Preethi, and P. Balasubramanian. "FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders." Advances in Electronics 2015 (May 27, 2015): 1–13. http://dx.doi.org/10.1155/2015/713843.

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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work,

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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9

Sathyanarayan, Pavitha Uppinakere, Mamtha Mohan, Sandeep Kakde, and Annam Karhik. "Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 172–83. https://doi.org/10.11591/ijeecs.v26.i1.pp172-183.

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The adder is the maximum usually used mathematics block in programs inclusive of central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety

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10

A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del

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11

Sathyanarayan, Pavitha Uppinakere, Mamtha Mohan, Sandeep Kakde, and Annam Karthik. "Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 172. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp172-183.

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The adder is the maximum usually used mathematics block in programs inclusive of <span lang="EN-US">central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional <a name="_Hlk95894088"></a>carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits

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12

Meenaakshi Sundhari, R. P., and R. Anita. "Modified 16-b Square-root Low Power Area Efficient Carry Select Adder." Research Journal of Applied Sciences, Engineering and Technology 8, no. 21 (2014): 2220–26. http://dx.doi.org/10.19026/rjaset.8.1221.

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13

PRASAD, M., U. B. MAHADEVASWAMY, and DANDAVATIMATH PRASHANT. "SQUARE ROOT CARRY SELECT ADDER USING MTTSPC D-LATCH IN 90nm TECHNOLOGY." i-manager’s Journal on Electronics Engineering 9, no. 3 (2019): 14. http://dx.doi.org/10.26634/jele.9.3.15267.

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14

M, Syed Mustafaa, Sathish M, Nivedha S, Magribatul Noora A K, and Safrin Sifana T. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design 1, no. 3 (2022): 5–9. http://dx.doi.org/10.54105/ijvlsid.c1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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16

PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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17

Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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18

Premananda, B. S., Archit Bajpai, G. Shakthivel, and A. R. Anurag. "Low power add-one circuit IPGL based high speed square root carry select adder." Indian Journal of Science and Technology 14, no. 9 (2021): 776–86. http://dx.doi.org/10.17485/ijst/v14i9.343.

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19

Belegahalli Siddaiah, Premananda, Nikhil Kiran Jayanthi, and Samana Hanumanth Managoli. "Low Power Square Root Carry Select Adder Using AVLS-TSPC-Based D Flip-Flop." Electrica 22, no. 1 (2021): 109–18. http://dx.doi.org/10.5152/electrica.2021.21024.

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20

Kandula, Bala Sindhuri, K. Padma Vasavi, and I. Santi Prabha. "Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic." Procedia Computer Science 89 (2016): 640–50. http://dx.doi.org/10.1016/j.procs.2016.06.028.

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21

Bahadori, Milad, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "An energy and area efficient yet high-speed square-root carry select adder structure." Computers & Electrical Engineering 58 (February 2017): 101–12. http://dx.doi.org/10.1016/j.compeleceng.2017.01.021.

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22

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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23

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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24

G, Dhanasekaran, Parthasarathy N, and Achuthan B. "High Speed, Low power and Area Efficient Processor Design Using Square Root Carry Select Adder." IOSR Journal of Electronics and Communication Engineering 9, no. 2 (2014): 14–18. http://dx.doi.org/10.9790/2834-09271418.

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Uthayakumar, C., and B. Justus Rabi. "Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)." Research Journal of Applied Sciences, Engineering and Technolog 12, no. 1 (2016): 43–51. http://dx.doi.org/10.19026/rjaset.12.2302.

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26

Goyal, Heena, and Shamim Akhter. "VHDL Implementation of Fast Multiplier based on Vedic Mathematic using Modified Square Root Carry Select Adder." International Journal of Computer Applications 127, no. 2 (2015): 24–27. http://dx.doi.org/10.5120/ijca2015906331.

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27

Paradhasaradhi, Damarla. "Performance Analysis of Different Multipliers using Square Root Carry Select Adders." IOSR journal of VLSI and Signal Processing 4, no. 2 (2014): 69–74. http://dx.doi.org/10.9790/4200-04246974.

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28

Agnes, Shiny Rachel, and Rajakumar.G. "Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2019): 407–10. https://doi.org/10.35940/ijeat.B3271.129219.

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result

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Suri, Lakshay, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, and Geetanjali Sharma. "Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic." International Journal of Computer Applications 69, no. 10 (2013): 32–35. http://dx.doi.org/10.5120/11881-7696.

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30

Murugeswari, S., and S. Kaja Mohideen. "Design of Optimized Low Power and Area Efficient Digital FIR Filter using Modified Group Structures based Square Root Carry Select Adder." Research Journal of Applied Sciences, Engineering and Technology 9, no. 2 (2015): 84–90. http://dx.doi.org/10.19026/rjaset.9.1381.

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31

Kumar Gopathoti, Kiran, and Naguri Divya Sruthi. "Implementation of low power N-bit hybrid parallel prefix adder using Xilinx-ISE." International Journal of Scientific Methods in Engineering and Management 01, no. 01 (2023): 36–46. http://dx.doi.org/10.58599/ijsmem.2023.1104.

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Recently, digital circuitry has demanded a decrease in space and power by decreasing time while simultaneously improving performance in speed. This has resulted in a need for more efficient use of the available space. Adders are fundamental components that are used in the construction of digital circuits. As a consequence of this, the performance of adders has to be improved in order to enhance the performance of integrated circuits that are used in the real world. The creation of a novel parallel prefix adder (PPA) architecture known as Hybrid PPA is the primary topic of this article. Hybrid

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32

BASHAGHA, A. E., and M. K. IBRAHIM. "NONRESTORING RADIX-2k SQUARE ROOTING ALGORITHM." Journal of Circuits, Systems and Computers 06, no. 03 (1996): 267–85. http://dx.doi.org/10.1142/s0218126696000200.

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This paper presents a new high radix square rooting algorithm where a number of square root bits (one digit) are generated in one step. Therefore, the proposed algorithm offers a higher speed than that of the conventional bit parallel binary one. This algorithm can be considered as a generalisation of the conventional bit parallel binary algorithm, and therefore it can be implemented using the existing simple binary elements. The proposed algorithm makes use only of the odd values of the square root to generate the possible values of the radicand and therefore, it requires less area than the c

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33

Mukunthan, P., N. C. Sendhilkumar, and R. Pitchai. "Design of New Reconfigurable Architecture for Implementing a Least Mean Square Finite Impulse Response Filter Using Borrow Select Subtraction (BSLS)." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1943–48. http://dx.doi.org/10.1166/jctn.2020.8471.

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A design of reconfigurable architecture of FIR filter has been implemented using a Least Mean Square (LMS) adaptive filter. LMS adaptive filter is mainly sued for reducing the coefficients of the filter. Generally, a LMS filter contains normal adder, subtractor, mixer and a delay part. Most of the concepts deal with an adder namely Full Adder (FA), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), etc., Instead of using CSLA; Borrow Select Subtractor (BSLS) is used in LMS filter architecture. By using BSLA LMS adaptive filter in a reconfigurable FIR filter architecture in the proposed schem

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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Hardware Optimized and Error Reduced Approximate Adder." Electronics 8, no. 11 (2019): 1212. http://dx.doi.org/10.3390/electronics8111212.

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This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% few

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Zhang, Xi, Li Wang, and Muyao Wu. "State of Charge-State of Health Collaborative Estimation of the Lithium-ion Battery Based on an Innovative Hybrid Optimization Network." Journal of Energy and Natural Resources 13, no. 4 (2024): 166–77. https://doi.org/10.11648/j.jenr.20241304.14.

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Lithium-ion battery is one of the core components of electric vehicles, and the state of charge-state of health estimation results of it is the key to restrict the safe and efficient use of it, which then affects the comprehensive performance of electric vehicles. However, SOC and SOH of lithium-ion batteries have a coupling relationship, and have fast and slow time-varying characteristics respectively, with inconsistent time scales. Hence, it is necessary to carry out SOC-SOH collaborative estimation and select a suitable time scale, which can ensure the accuracy and robustness of SOC-SOH col

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Fan, Yaobing, Youxing Chen, Shangrong Wu, et al. "Study on the Automatic Selection of Sensitive Hyperspectral Bands for Rice Nitrogen Retrieval Based on a Maximum Inscribed Rectangle." Agronomy 15, no. 2 (2025): 406. https://doi.org/10.3390/agronomy15020406.

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Most existing studies on the optimal bandwidth selection for plant nitrogen are based on the sensitive band center, and determine the optimal bands by manually adjusting the bandwidth, step by step. However, this method has a high level of manual involvement and is time-consuming. This paper focused on rice as the research subject, based on determining the center of the rice plant nitrogen-sensitive bands and the maximum region Ω of the fitted R2 between the narrow-band vegetation indices (N-VIs) and plant nitrogen, a method was proposed to automatically select the optimal bandwidth by constru

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Zhang, Chunming, Mingjian Gu, Yong Hu, et al. "A Study on the Retrieval of Temperature and Humidity Profiles Based on FY-3D/HIRAS Infrared Hyperspectral Data." Remote Sensing 13, no. 11 (2021): 2157. http://dx.doi.org/10.3390/rs13112157.

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Satellite infrared hyperspectral instruments can obtain a wealth of atmospheric spectrum information. In order to obtain high-precision atmospheric temperature and humidity profiles, we used the traditional One-Dimensional Variational (1D-Var) retrieval algorithm, combined with the information capacity-weight function coverage method to select the spectrum channel. In addition, an Artificial Neural Network (ANN) algorithm was introduced to correct the satellite observation data error and compare it with the conventional error correction method. Finally, to perform the temperature and humidity

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Mr., Vijay V. Gotmare, and Pankaj Agarwal Dr. "Design of High-Speed Hybrid Carry Select Adders using VHDL." Journal of Information, Knowledge and Research in Electronics and Communication, March 1, 2016, 1251–53. https://doi.org/10.5281/zenodo.46809.

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Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this wo

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Priya, Ramesh Meshram. "Implementing Design of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Engineering Applications and Technology, March 21, 2015. https://doi.org/10.5281/zenodo.33089.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In following paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) is proposed. Based on this modification a new architecture has been developed and compared with the regular and modified Square-root CSLA (SQRT CSLA) architecture. The modified architecture has been developed using Binary to Excess-1

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40

Siddaiah, Premananda Belegahalli, Nikhil Kiran Jayanthi, and Samana Hanumanth Managoli. "Low Power Square Root Carry Select Adder Using AVLS-TSPC-Based D Flip-Flop." Electrica, September 9, 2021. http://dx.doi.org/10.5152/electr.2021.21024.

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41

Reddy, Dr P. Bhaskara, S. V. S. Prasad, and K. Ananda Kumar. "An Area and Speed Efficient Square Root Carry Select Adder Using Optimized Logic Units." SSRN Electronic Journal, 2015. http://dx.doi.org/10.2139/ssrn.3536422.

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NAIK, D. KRISHNA, and DR V. VIJAYALAKSHMI. "MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS." International Journal of Electronics Signals and Systems, October 2014, 99–103. http://dx.doi.org/10.47893/ijess.2014.1205.

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In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed d

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"AREA EFFICIENT AND HIGH SPEED ALU USING 64 BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER." International Journal of Advance Engineering and Research Development 4, no. 07 (2017). http://dx.doi.org/10.21090/ijaerd.48875.

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"Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique." International Journal of Innovative Technology and Exploring Engineering 8, no. 12 (2019): 2873–79. http://dx.doi.org/10.35940/ijitee.l3051.1081219.

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Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number

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"Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction." International Journal of Engineering and Advanced Technology 9, no. 2 (2019): 407–10. http://dx.doi.org/10.35940/ijeat.b3271.129219.

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This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result

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AntoBennet, M., S. Sankaranarayanan, V. BanuPriya, PJaya Pretheena, S. Yamini, and S. Supriya. "PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER." International Journal on Smart Sensing and Intelligent Systems 10, no. 4 (2017). https://doi.org/10.21307/ijssis-2017-268.

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Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with t

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Ganna, Raju, Shanky Saxena, and Govind Singh Patel. "Design Of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder." Journal of Circuits, Systems and Computers, June 6, 2022. http://dx.doi.org/10.1142/s0218126622502929.

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Ragunath, G., and R. Sakthivel. "Low - Power and Area - Efficient Square – Root Carry Select Adders using Modified XOR Gate." Indian Journal of Science and Technology 9, no. 5 (2016). http://dx.doi.org/10.17485/ijst/2016/v9i5/87181.

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Bhadavath, Kiran Kumar, and Z. Mary Livinsa. "An Optimized Retiming-based FIR Filter Architecture using Efficient Multipliers and Adders." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 18 (July 10, 2025). https://doi.org/10.2174/0123520965352314250610113648.

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Introduction: An efficient higher-order filter architecture is designed and implemented for ECG signal processing applications. To prune the latency of the architecture, the retiming technique is considered for the design of less memory type Finite Impulse Response (FIR) filter architecture. The optimized multipliers and adders are key blocks in the filter architecture to increase the latency and Power Consumption (PC). Method: In this regard, an optimized Radix-4 Booth Multiplier (RBM) is designed using a modified booth encoder and selector blocks along with the proposed improved version of S

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Penchalaiah, Usthulamuri, and V. G. Siva Kumar. "Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU." Parallel Processing Letters, October 19, 2021. http://dx.doi.org/10.1142/s0129626421500171.

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Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced p

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