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Relevant bibliographies by topics / Square Root CSLA (SQRT CSLA)

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Academic literature on the topic 'Square Root CSLA (SQRT CSLA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Square Root CSLA (SQRT CSLA)"

1

You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C

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2

A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del

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3

Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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4

Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture ha

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5

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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6

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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Abstract:

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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7

Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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8

Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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9

M, Syed Mustafaa, Sathish M, Nivedha S, Magribatul Noora A K, and Safrin Sifana T. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design 1, no. 3 (2022): 5–9. http://dx.doi.org/10.54105/ijvlsid.c1205.031322.

Full text

Abstract:

Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po

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10

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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Abstract:

In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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