Dissertations / Theses on the topic 'SRAM Sense Amplifiers'

Réduire la tension d'alimentation est l'un des moyens les plus efficaces pour diminuer l'énergie consommée des circuits, mais malheureusement au détriment de leurs performances. Cependant, il existe des domaines d'application (les pacemakers, les systèmes auditifs,. . . ) qui ne demandent pas nécessairement de grandes performances et qui peuvent voir leur consommation réduite fortement en travaillant avec des tensions d'alimentation très basses. La partie mémoire des circuits logiques est de plus en plus importante (en 2008, la surface du bloc mémoire occupera 80% de la surface totale d'un circuit). Dans cette thèse, sont proposés les circuits élémentaires d'une mémoire SRAM (cellule mémoire, circuits de lecture et d'écriture) en technologie SOI partiellement désertée (PD) fonctionnant en ultra basse tension (ULV, VDD=0. 5V). Dans ce cas, les transistors opèrent en limite de faible et forte inversion. Les courants de fuite sont alors utilisés comme courants de conduction. Les applications visées sont de type basse et moyenne performances (inférieures à 100MHz). Une nouvelle topologie de cellule mémoire à 4-Transistors avec autorafraîchissement de l'information stockée ainsi qu'un nouveau circuit de lecture en mode courant ont été développés. L'étude de ces circuits a été faite en technologie SOI-PD 130nm. Pour concevoir ces circuits de façon fiable, les méthodes conventionnelles de conception des circuits mémoire ont été adaptées de manière à prendre en compte les effets secondaires dus au substrat flottant des transistors SOI-PD. De plus, pour mieux caractériser le comportement électrique des transistors fonctionnant en en ULV, un modèle analytique simple a été développé
Active power consumption of CMOS logic circuits increases quadratically with supply voltage and leakage power exponentially. Hence minimising the supply voltage is one of the most effective ways to reduce energy usage but unfortunately at the expense of increased delay. Some niche applications such as pacemakers, hearing devices, wearable wrist watches and self powered devices do not necessarily need high-performance, therefore operation in Ultra-Low-Voltage (ULV) is very attractive for achieving a significant energy saving. In this case the transistors are operated in the sub-threshold region where the gate-source voltage is below the threshold (Vt) voltage of the transistor. Leakage current is then used as the operating switching current. In this PhD Thesis we focus mainly on ULV memory cell design using SOI technology. A new 4-T Self-Refresh memory cell without refresh cycle and a new read current sense amplifier are proposed. Furthermore, a simple yet realistic physics based model is introduced to descirbe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage depedencies, including the short channel effects

碩士
國立成功大學
電機工程學系碩博士班
96
In this thesis, two novel tolerant techniques for SRAM self-timing are presented. One of the techniques is self-activated bit-line sensing scheme (SABLS) and the other is NMOS delay chain (NDC). The sense amplifier (SA) can be either triggered by SABLS or NDC with intelligent decisions depending on on-chip variations and performance constraints. A low-swing technique for heavy-loading bit-lines is also proposed herein to support SABLS activation. The SRAM cells are designed to keep the bit-line voltage no less than VSAT spontaneously in low voltages. When in high voltages, the swing voltage of bit-line can be limited by completed signal or turning on NDC instead. Most of recent techniques may only focus on inter-die variation in their self-timing circuits, while intra-die variation is critical in the advanced technologies. Using the proposed schemes, the access failure rate will reduce 20 % compared with conventional schemes in 90nm considering both inter-die and intra-die variations. The novel self-timing activation techniques can also enables SRAM operating in a wide range of supply voltage from 1 V to 0.2V.

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.

Performance and power of sense amplifiers have big implications on the speed of caches used in microprocessors as well as power consumption of IPs in low power system on chips. The speed of voltage sense amplifiers are limited by the differential voltage development time on high capacitance SRAM bit-lines. The dynamic power increases with the differential voltage that needs to be developed on the bit-lines. This report explores multiple sense amplifier techniques - in addition to the conventional voltage sense amplifier, it analyzes current sense amplifier, charge transfer sense amplifier as wells as current latched sense amplifier and compares them in speed, area and power consumption to the voltage sense amplifier. A current sense amplifier operates by sensing the bit cell current directly and shows power and area advantages. A charge transfer sense amplifier makes use of charge redistribution between the high capacitance bit-lines and low capacitance sense amplifier output nodes to provide power benefits. This report also explores the design of a six transistor SRAM bit cell. All circuits are designed and simulated on a 45nm CMOS process.
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碩士
長庚大學
半導體科技研究所
91
As the semiconductor processing technology advances, many VLSI systems including SRAM are requested to work at lower working voltage, lower power consumption and faster speed. Therefore, the main focus of this thesis is on the sense amplifier design of low voltage, low power and high speed SRAM. A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this thesis. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35um CMOS process can work at 100MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3V, the simulations show that this design has 14% and 86% power delay product improvement over the prior art and conventional sense amplifier, respectively. Besides, a solution for the proposed SA to combine with column decoder of SRAM array is demonstrated for low power and high performance applications. Moreover, the proposed SA is applied to the design of a 2k bits SRAM with satisfactory whole chip functions.

碩士
國立清華大學
電機工程學系
93
Abstract The Static Random Access Memory (SRAM) is an important storage element for the embedded system and generally used today. The sense amplifier of SRAM is utilized to speed up the read operation so that it is a critical influence to the output. The input signals of the sense amplifier are very weak and determine if the sense process succeed or not so it is difficult to measure. We need an accurate and valid circuit to reach the goal. With it the measurement process is automatic and only the lower-end test machine is need. Besides, a new fault model IVDF (insufficient voltage difference fault) is proposed to model the behavior of SRAM cell. We can detect the faulty cell and locate it. The proposed circuit is simulated with 1-K-bit SRAM by using the UMC 0.18um 1P6M Mixed-signal CMOS process.

碩士
國立清華大學
電機工程學系
98
In our livelihood, the Static Random Access Memory (SRAM) appears in the almost electronics and it is required more area than other circuits in the SOC chip. That shows the SRAM used up the most power of a chip. So, how to solve the problem of SRAM power consumption and not to cut down the SRAM operating performance is a big challenge. The point about all problems of SRAM for reducing the power consumption is to lower the SRAM operating voltage. But, pulling down the operating voltage that made the static noise margin (SNM) of SRAM cell characteristics be smaller. This phenomenon will to cause the read half-selected disturb problem and write half-selected disturb problem when SRAM macro operating in write mode or read mode in the ultra low voltage. If SRAM macro happens the disturb problem which made the write fail or read fail, that is no meaning for to operate at ultra low voltage. In this work, we proposed a differential read write back sense amplifier (DRWB-SA) to cancel the write half-selected disturb problem of SRAM cell. This DRWB-SA will help the SRAM to operate at the ultra low voltage. And, we analysis the SA layout style about 1 dimension or 2 dimension common-centroid and one-pitch or two-pitch to reduce the SA offset, which is made DRWB-SA can success operating at ultra low voltage by small bit line (BL) swing. To test and verify, we proposed a 64kb SRAM macro with DRWB-SA that is used two-pitch common-centroid layout is fabricated in 90nm CMOS technology. By oscilloscope and CIC 93K tester to get measurement results of the 64kb SRAM macro, that can operate down to 230mV running at 1.3MHz. Benefiting from operation at 230mV, the operating power of SRAM is 15.36uW and 32.47pJ in energy consumption.

碩士
南台科技大學
電子工程系
98
This study discusses the lower power consumption and speed sensing of sense amplifier in SRAM application. Within SRAM design, the sense amplifiers are used to augment the bit-line signal of memory cell. For most SRAM structures, bit-line is usually lengthy and attached several memory cells, this makes quite large capacitance loading on bit-line. With the increasing of memory cell and the lowering of the operating voltage with the process advancement, this results in the operating speed slower. In order to make sure that the circuit can operate at reasonable speed, the input signals to sense amplifier were confined within 50mV to 200mV then begin to do signal sensing, magnifying and output. Therefore, the speed performance of SRAM is dominated by the sensing speed and this is one of key factor in designing sense amplifiers. The simulation environment adopts TSMC 0.18μm 1P6M process with 1.8V supply voltage. The pre-simulation results show that the power consumption is enhanced up to 31.73% with comparing to traditional sense amplifiers. For sensing speed against the modified current latched sense amplifier, the proposed design can be improved up to 34.63 percent on Power Delay Product (PDP).

This paper outlines design considerations and implementation details of full swing and of partial swing SRAM arrays. Comparisons between the two methods based on performance, power, and noise rejection are then presented. Finally, a decision matrix will be provided that selects the better topology based on varying design constraints.
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Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system. In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness. As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.

碩士
義守大學
電子工程學系碩士班
94
Large bit line wire loading is one of the main bottlenecks to the performance of SRAM. We propose a charge-transfer mechanism and a new pre-charge scheme to improve the sensing speed of the traditional current latch sense amplifier. The improvement of sensing speed of the proposed design is about 4% comparing to the traditional current latch sense amplifier. In addition, the proposed design has much better tolerance and faster sensing speed on Vt mismatch of NMOS transistors. The presented circuit simulation result is evaluated in the TSMC 0.18μm Mixed Signal/RF Process Model.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

碩士
國立中正大學
電機工程所
98
In this thesis focuses on low voltage and small signal amplifiers to propose a sensor mechanism to improve the overall stability and its operating voltage is set at sub-threshold voltage, the voltage drop means that the power consumption of the SRAMs, but in the process, voltage, temperature, variation caused by the traditional low-voltage sense amplifier used buffer chain amplifier, resulting in decreased overall performance, but the use of small signal amplifiers as bit line leakage in the relative impact of low voltage caused sensing serious errors , solved by leakage lookahead pre-charge circuit. First, re-design the recent literature Non-Strobed Regenerative Sense Amplifier (NSR-SA) in sub-threshold voltage, and improve both the leakage current, the main thesis is divided into two categories: 1. use stacked effect to improve the NSR-SA internal leakage current, increase their operating bandwidth 2. in the sub-threshold voltage for the serious impact of the bit-line leakage current, use leakage lookahead pre-charge circuit with the NSR-SA to solution, and its mechanism provided Run-Time-Calibrated for different variations of resistance and a higher tolerance for change, at final use the mechanism in different cells.

碩士
國立中山大學
電機工程學系研究所
91
The first topic of this thesis is to propose a novel voltage-to-frequency converter (VFC) to provide high sensitivity. The VFC circuit is composed of one current mirror, one current multiplier, and voltage window comparators. The proposed VFC tracks the variations of the stored charge of a built-in capacitor. The voltage window comparator monitors the voltage of the capacitor to determine whether the output is pulled high or pulled down. The worth-case linear range of the output frequency of the proposed VFC is 0 to 55 MHz provided that the input voltage is 0 to 0.9 V. The error is less than 9% while the power dissipation is 0.218 mW. The second topic is to carry out a novel CMOS current-mode high- speed sense amplifier (SA). The proposed SA is composed by cascading a current-mode sense amplifier and a voltage-mode sense amplifier. The small input impedance of the current-mode amplifier alleviates the loading effect on the bitlines of SRAM cells such that the sensing speed is enhanced. The voltage-mode amplifier is responsible for boosting the logic levels to full swing. The worst access time of the proposed design is found to be less than 1.26 ns with a 1 pF load on outputs. The power dissipation is merely 0.835 mW at 793 MHz.

碩士
國立中山大學
電機工程學系研究所
90
The first topic of this thesis is a cell-based design solution of 4×8 scanning decoder using RC5 protocol for DECT handsets. It is a keypad scanner ASIC without any embedded microprocessor nor internal ROMs. The keypad scanner uses RC5 transfer protocol which is compatible with remote control and wireless handsets. The keypad scanner built in the handsets must meet the requirement of low power consumption and small die size to avoid shortening the battery lift and increasing chip cost. The proposed ASIC design possesses both of the required advantages. The second topic is a high-performance SRAM using current sense amplifier. Current sensing in SRAMs is very promising method to achieve high speed operations in low-voltage applications. This topic present a current sense amplifier circuit as well as its simulation results.