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Journal articles on the topic 'SRAM Sense Amplifiers'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Kumar, Sunil, and Arun Kr Chatterjee. "Comparative study of different Sense Amplifiers in 0.18um technology." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (June 10, 2013): 615–19. http://dx.doi.org/10.24297/ijct.v7i3.3440.

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A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiersÂ are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output of sense amplifier is isolated from the bitline parasitic capacitance then the sensing delay of sense amplifier reduces.

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2

Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

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The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less power than CTSA and SRAM devices

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3

Foziya, Lone, and Er Ritesh Kumar Ojha. "A Novel Design for Low-Power, High Performance and Space Efficient Address Decoder for SRAM." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (April 30, 2022): 1088–95. http://dx.doi.org/10.22214/ijraset.2022.41407.

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Abstract: We discover the optimum decoder structure for fast low-power SRAMS. The results are ideal when the decoder is designed as a binary tree without the precoder. We find that skewed circuits with self-resetting gates work well, and we explore some basic scaling algorithms for minimal delay and power in the SRAM data path. Signal oscillations on high capacitance nodes like bit lines and data lines are decreased, resulting in low power operation. Clocked voltage sense amplifiers are required for low sensing power, and accurate construction of their sense clock is required for high-speed operation. By restricting bit line and NO line swings, we examine tracking circuits to aid in the development of the sense clock and allow timed sense amplifiers. The tracking circuits successfully use a replica memory cell and a replica bit line to track the memory cell's delay throughout a wide variety of manufacturing and operating conditions. The results of two different prototypes' experiments are reported. Finally, we investigate the speed and power development trends of SRAMs as a function of size and technology, discovering that if the connection delay is negligible, the SRAM delay grows as the logarithm of its size. Wire delay becomes increasingly important for SRAMs after the fifth generation. The wire delay worsens as the process shrinks, requiring wire redesign to keep the wire delay proportionate to the gate delay. Hierarchical SRAM topologies provide enough of array space for fat Wires and may be used to control time. Throughout the procedure, the wire delay for 4Mb and smaller designs diminishes. Keywords: SRAMs, High Performance, Delay, Clock, Decoder

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4

Ney, A., P. Girard, S. Pravossoudovitch, A. Virazel, and M. Bastian. "Analysis of Resistive-Open Defects in SRAM Sense Amplifiers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 10 (October 2009): 1556–59. http://dx.doi.org/10.1109/tvlsi.2008.2005194.

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5

Dounavi, Helen-Maria, Yiorgos Sfikas, and Yiorgos Tsiatouhas. "Periodic Monitoring of BTI Induced Aging in SRAM Sense Amplifiers." IEEE Transactions on Device and Materials Reliability 19, no. 1 (March 2019): 64–72. http://dx.doi.org/10.1109/tdmr.2019.2898862.

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6

Anh-Tuan, Do, Kong Zhi-Hui, and Yeo Kiat-Seng. "Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 10 (October 2008): 986–90. http://dx.doi.org/10.1109/tcsii.2008.2001965.

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7

Byung-Do Yang and Lee-Sup Kim. "A low-power SRAM using hierarchical bit line and local sense amplifiers." IEEE Journal of Solid-State Circuits 40, no. 6 (June 2005): 1366–76. http://dx.doi.org/10.1109/jssc.2005.848032.

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8

Wicht, B., S. Paul, and D. Schmitt-Landsiedel. "Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers." IEEE Journal of Solid-State Circuits 36, no. 11 (2001): 1745–55. http://dx.doi.org/10.1109/4.962297.

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9

Lu, Wenjuan, Chunyu Peng, Youwu Tao, and Zhengping Li. "Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers." Electronics Letters 51, no. 10 (May 2015): 742–43. http://dx.doi.org/10.1049/el.2015.0574.

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10

Ishibashi, K., K. Komiyaji, S. Morita, T. Aoto, S. Ikeda, K. Asayama, A. Koike, et al. "A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers." IEEE Journal of Solid-State Circuits 29, no. 4 (April 1994): 411–18. http://dx.doi.org/10.1109/4.280689.

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11

Ishibashi, K., K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, et al. "A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers." IEEE Journal of Solid-State Circuits 30, no. 4 (April 1995): 480–86. http://dx.doi.org/10.1109/4.375969.

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12

Niki, Yusuke, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, and Tomoaki Yabe. "A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers." IEEE Journal of Solid-State Circuits 46, no. 11 (November 2011): 2545–51. http://dx.doi.org/10.1109/jssc.2011.2164294.

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13

Shrivastava, Smarika, and Vinay Kumar Tomar. "Comparative Analysis of Leakage Reduction Techniques in Voltage Mode and Current Latch Sense Amplifiers in Sram Cell." INROADS- An International Journal of Jaipur National University 5, no. 1s (2016): 245. http://dx.doi.org/10.5958/2277-4912.2016.00047.3.

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14

Wu, JianHui, JiaFeng Zhu, YingCheng Xia, and Na Bai. "A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 4 (April 2014): 264–68. http://dx.doi.org/10.1109/tcsii.2014.2304893.

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15

Lin, Zhiting, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, and Junning Chen. "A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process." IEEE Journal of Solid-State Circuits 52, no. 3 (March 2017): 669–77. http://dx.doi.org/10.1109/jssc.2016.2634701.

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16

Cosemans, Stefan, Wim Dehaene, and Francky Catthoor. "A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers." IEEE Journal of Solid-State Circuits 44, no. 7 (July 2009): 2065–77. http://dx.doi.org/10.1109/jssc.2009.2021925.

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17

Priya, G. Lakshmi, Puneet Saran, Shikhar Kumar Padhy, Prateek Agarwal, A. Andrew Roobert, and L. Jerart Julus. "Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits." Micromachines 14, no. 3 (February 28, 2023): 581. http://dx.doi.org/10.3390/mi14030581.

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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18

Sinangil, Mahmut E., and Anantha P. Chandrakasan. "Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access." IEEE Journal of Solid-State Circuits 49, no. 1 (January 2014): 107–17. http://dx.doi.org/10.1109/jssc.2013.2280310.

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19

Kim, Youngbae, Shreyash Patel, Heekyung Kim, Nandakishor Yadav, and Kyuwon Ken Choi. "Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles." Electronics 10, no. 3 (January 22, 2021): 256. http://dx.doi.org/10.3390/electronics10030256.

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Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

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20

K, Komal, and Dr Neelam Rup Prakash. "CMOS and DTMOS Sense Amplifier for SRAM Application." IJIREEICE 5, no. 6 (June 15, 2017): 128–31. http://dx.doi.org/10.17148/ijireeice.2017.5622.

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21

Ali, Luqman Sufer, and Asmaa Salim Mayoof. "Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed." Tikrit Journal of Engineering Sciences 23, no. 2 (May 31, 2016): 96–102. http://dx.doi.org/10.25130/tjes.23.2.11.

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This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

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22

Priya, G. Lakshmi, Namita Rawat, Abhishek Sanagavarapu, M. Venkatesh, and A. Andrew Roobert. "Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell." Micromachines 14, no. 2 (January 17, 2023): 232. http://dx.doi.org/10.3390/mi14020232.

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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23

Kumar Pandey, Neeraj. "IoT Systems with Low-Power SRAM Memory Architecture." Journal of Futuristic Sciences and Applications 4, no. 2 (2021): 9–15. http://dx.doi.org/10.51976/jfsa.422102.

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A quantitative and yield analysis was made and tested on a single-bit cache memory design using a range of resistor values and various sense amplifier types, such as the voltage mode differential sense amplifier (VMDSA). In a single-bit cache memory design, the voltage mode differential sense amplifier uses the least power. The low power consumption and long access times of this SRAM will be very advantageous for the Internet of Things (IoT).

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24

Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (March 30, 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.

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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.

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25

Dutt, Ravi. "High Speed Current Mode Sense Amplifier for SRAM Applications." IOSR Journal of Engineering 02, no. 05 (May 2012): 1124–27. http://dx.doi.org/10.9790/3021-020511241127.

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26

Thakur, Meenakshi, and Rajesh Mehra. "An Energy-Efficient sense amplifier using 180nm for SRAM." IOSR Journal of VLSI and Signal Processing 06, no. 04 (April 2016): 16–19. http://dx.doi.org/10.9790/4200-0604011619.

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27

Thakur, Meenakshi, and Rajesh Mehra. "An Efficient Sense Amplifier for SRAM using Body Biasing." International Journal of Engineering Trends and Technology 37, no. 4 (July 25, 2016): 212–15. http://dx.doi.org/10.14445/22315381/ijett-v37p236.

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28

Lakshmi, T. Venkata, T. Edukondalu, S. Rahul, R. S. P. L. Suvarna, and T. Rohit Chaitanya. "A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (April 30, 2023): 714–21. http://dx.doi.org/10.22214/ijraset.2023.50158.

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Abstract: Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

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29

KONG, ZHI-HUI, KIAT-SENG YEO, and CHIP-HONG CHANG. "AN ULTRA LOW-POWER CURRENT-MODE SENSE AMPLIFIER FOR SRAM APPLICATIONS." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 939–51. http://dx.doi.org/10.1142/s021812660500274x.

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A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

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30

Li, Zhengping, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, and Junning Chen. "Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier." IEICE Electronics Express 13, no. 7 (2016): 20150951. http://dx.doi.org/10.1587/elex.13.20150951.

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31

Fan, Ming-Long, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, and Ching-Te Chuang. "Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications." IEEE Transactions on Circuits and Systems II: Express Briefs 59, no. 12 (December 2012): 878–82. http://dx.doi.org/10.1109/tcsii.2012.2231016.

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32

Bai Na, Zheng Zhongjiu, and Wu Xiulong. "A Leakage Current-Compensation-Mode Sense Amplifier for High-Performance SRAM." International Journal of Advancements in Computing Technology 4, no. 23 (December 31, 2012): 729–35. http://dx.doi.org/10.4156/ijact.vol4.issue23.87.

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33

Seki, T., E. Itoh, C. Furukawa, I. Maeno, T. Ozawa, H. Sano, and N. Suzuki. "A 6-ns 1-Mb CMOS SRAM with latched sense amplifier." IEEE Journal of Solid-State Circuits 28, no. 4 (April 1993): 478–83. http://dx.doi.org/10.1109/4.210031.

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34

HSU, C. L. "New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 2 (February 1, 2006): 377–84. http://dx.doi.org/10.1093/ietfec/e89-a.2.377.

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35

Dounavi, Helen-Maria, Yiorgos Sfikas, and Yiorgos Tsiatouhas. "Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier." Journal of Electronic Testing 37, no. 1 (February 2021): 65–82. http://dx.doi.org/10.1007/s10836-021-05932-6.

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36

Jeong, Hanwool, Taewon Kim, Kyoman Kang, Taejoong Song, Gyuhong Kim, Hyo-sig Won, and Seong-Ook Jung. "Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 6 (June 2015): 1555–63. http://dx.doi.org/10.1109/tcsi.2015.2415171.

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37

Verma, Naveen, and Anantha P. Chandrakasan. "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy." IEEE Journal of Solid-State Circuits 43, no. 1 (January 2008): 141–49. http://dx.doi.org/10.1109/jssc.2007.908005.

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38

Agbo, Innocent, Mottaqiallah Taouil, Daniel Kraak, Said Hamdioui, Halil Kukner, Pieter Weckx, Praveen Raghavan, and Francky Catthoor. "Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (April 2017): 1444–54. http://dx.doi.org/10.1109/tvlsi.2016.2643618.

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39

Reniwal, B. S., and S. K. Vishvakarma. "A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM." International Journal of Electronics and Electrical Engineering 1, no. 1 (2013): 34–38. http://dx.doi.org/10.12720/ijeee.1.1.34-38.

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40

Yu, Qun Ling, Na Bai, Yan Zhou, Rui Xing Li, Jun Ning Chen, and Zheng Ping Li. "An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM." Advanced Materials Research 542-543 (June 2012): 769–74. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.769.

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A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

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41

Sasaki, K., K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N. Hashimoto, H. Toyoshima, F. Kojima, and A. Shimizu. "A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier." IEEE Journal of Solid-State Circuits 27, no. 11 (1992): 1511–18. http://dx.doi.org/10.1109/4.165330.

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42

Seno, K., K. Knorpp, L. L. Shu, N. Teshima, H. Kihara, H. Sato, F. Miyaji, et al. "A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier." IEEE Journal of Solid-State Circuits 28, no. 11 (1993): 1119–24. http://dx.doi.org/10.1109/4.245591.

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43

Lai, Ya-Chun, and Shi-Yu Huang. "A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 10 (October 2008): 1031–35. http://dx.doi.org/10.1109/tcsii.2008.926797.

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44

Reniwal, Bhupendra Singh, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, and Devesh Dwivedi. "An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM." Circuits, Systems, and Signal Processing 38, no. 4 (August 30, 2018): 1482–505. http://dx.doi.org/10.1007/s00034-018-0934-1.

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45

Chee, P. Y., P. C. Liu, and L. Siek. "High-speed hybrid current-mode sense amplifier for CMOS SRAMs." Electronics Letters 28, no. 9 (1992): 871. http://dx.doi.org/10.1049/el:19920550.

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Hu, Vita Pi-Ho. "Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier." IEEE Journal of the Electron Devices Society 5, no. 2 (March 2017): 107–11. http://dx.doi.org/10.1109/jeds.2016.2644724.

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Fragasse, Roman, Ramy Tantawy, Brian Dupaix, Trevor Dean, Daron Disabato, Matthew R. Belz, Dale Smith, Jamin Mccue, and Waleed Khalil. "Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 6 (June 2019): 2037–50. http://dx.doi.org/10.1109/tcsi.2019.2902102.

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Liu, Bingyan, Jiangzheng Cai, Jia Yuan, and Yong Hei. "A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing." IEEE Transactions on Circuits and Systems II: Express Briefs 64, no. 4 (April 2017): 442–46. http://dx.doi.org/10.1109/tcsii.2016.2563660.

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Attarzadeh, H., and M. Sharifkhani. "An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier." Microelectronics Journal 45, no. 6 (June 2014): 781–92. http://dx.doi.org/10.1016/j.mejo.2014.02.015.

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Reniwal, B. S., P. Bhatia, and S. K. Vishvakarma. "Design and investigation of variability aware sense amplifier for low power, high speed SRAM." Microelectronics Journal 59 (January 2017): 22–32. http://dx.doi.org/10.1016/j.mejo.2016.11.009.

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