Relevant bibliographies by topics / Standard digital CMOS technology

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Standard digital CMOS technology'

Author: Grafiati
Published: 10 September 2021
Last updated: 2 February 2022

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Journal articles on the topic "Standard digital CMOS technology"

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Parameswaran, M., Lj Ristic, A. C. Dhaded, H. P. Baltes, W. Allegretto, and A. M. Robinson. "Fabrication of microbridges in standard complementary metal oxide semiconductor technology." Canadian Journal of Physics 67, no. 4 (1989): 184–89. http://dx.doi.org/10.1139/p89-032.

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Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by fir
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Blalock, B. J., P. E. Allen, and G. A. Rincon-Mora. "Designing 1-V op amps using standard digital CMOS technology." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 7 (1998): 769–80. http://dx.doi.org/10.1109/82.700924.

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Pernici, S., F. Stevenazzi, and G. Nicollini. "Fully integrated voiceband codec in a standard digital CMOS technology." IEEE Journal of Solid-State Circuits 39, no. 8 (2004): 1331–34. http://dx.doi.org/10.1109/jssc.2004.831483.

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Jung, Wee-Shin, Seung-Soo Kim, Yong-Guk Park, Kwang-Ho Won та Hyun-Chol Shin. "Indictor Library for RF Integrated Circuits in Standard Digital 0.18 μm CMOS Technology". Journal of Korean Institute of Electromagnetic Engineering and Science 18, № 5 (2007): 530–38. http://dx.doi.org/10.5515/kjkiees.2007.18.5.530.

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Bialko, M., and A. Guzinski. "Comments on "Designing 1-V op-amps using standard digital CMOS technology." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 11 (1999): 1448. http://dx.doi.org/10.1109/tcsii.1999.803488.

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Zhao, Hongliang, and Xinghui Liu. "A low-power cryogenic analog to digital converter in standard CMOS technology." Cryogenics 55-56 (May 2013): 79–83. http://dx.doi.org/10.1016/j.cryogenics.2013.03.005.

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Chiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front." Microscopy Today 7, no. 2 (1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.

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Although the Charge-Coupled Device (CCD) imaging chip is the standard in today's video and digital cameras, things may change during the coming year. The CCD chip is being challenged by a competing device, the CMOS ("C-moss") chip.CMOS is the most widely used type of integrated circuit for memory and digital processing, virtually everything in computers is CMOS based. The economies of scale and production of CMOS devices are the main reasons why computer prices have continued to drop during the past few years. If a device or an instrument has a microprocessor in it, chances are it includes CMO
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Deng, Fang Ming, and Yi Gang He. "A Low-Cost Low-Power Capacitive Humidity Sensor in CMOS Technology." Applied Mechanics and Materials 556-562 (May 2014): 1842–46. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1842.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface is based on a delta-sigma converter and can be easily reconfigured to compensate for process variation of the sensing element. The proposed humidity sensor is fabricated in 0.16μm standard CMOS process and the chip occupies 0.25mm2. The measurement result shows that this humidity sensor acquires a resolution of 0.1%RH in the range of 20%RH to 90%RH. The interfa
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ROSSELLO, JOSEP L., VINCENT CANALS, ANTONI MORRO, and JAUME VERD. "CHAOS-BASED MIXED SIGNAL IMPLEMENTATION OF SPIKING NEURONS." International Journal of Neural Systems 19, no. 06 (2009): 465–71. http://dx.doi.org/10.1142/s0129065709002166.

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A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 μm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.
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Im, Hyungjin, and Ki Hyuk Kim. "Inductive Switching Noise Suppression Technique for Mixed-Signal ICs Using Standard CMOS Digital Technology." Journal of information and communication convergence engineering 14, no. 4 (2016): 268–71. http://dx.doi.org/10.6109/jicce.2016.14.4.268.

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Dissertations / Theses on the topic "Standard digital CMOS technology"

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Lee, Myunghee. "A quasi-monolithic optical receiver using a standard digital CMOS technology." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14720.

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Delaunay, Nicolas. "Linearization of a transmitter using an IC digital/analog cartesian feedback in 65nm CMOS for advanced communication standards." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14716/document.

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Depuis la première génération de téléphone mobile, de nombreuses fonctions et outils ont été intégrés dans nos terminaux. Il y a vingt ans, nous utilisions nos téléphone pour émettre des appels et envoyer/recevoir des messages. Aujourd’hui, l’accès à internet, la radio, l’appareil photo, des jeux et de la musique sont des fonctionnalités que l’on retrouve dans nos téléphones mobiles.Dans un contexte de téléphonie pouvant adresse plusieurs standards, l’objectif de cette thèse est de concevoir et de réaliser l’implémentation d’une architecture capable d’améliorer la linéarité de notre émetteur p
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Fouque, Andrée. "Contribution à la conception d'un récepteur mobile failble coût et faible consommation dans la bande Ku pour le standard DVB-S." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14528/document.

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Cette thèse présente une étude de faisabilité d'un récepteur faible coût et faible consommation pour l'extension du standard DVS-S à la mobilité. L'objectif de ce projet est de proposer de solutions pour lever les verrous technologiques quant à la réalisation d'un tel système en technologie CMOS 65 nm. Ce manuscrit de thèse articulé autour de quatre chapitres décrit toutes les étapes depuis la définition des spécifications du réseau d'antennes et de la chaîne de réception jusqu'à la présentation de leurs performances, en passant par l'étude de leurs architectures et de la conception des différ
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Asgari, Mohammadreza. "FULLY-INTEGRATED CMOS PH, ELECTRICAL CONDUCTIVITY, AND TEMPERATURE SENSING SYSTEM." University of Akron / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1533827604228324.

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Blanksby, Andrew J. "Colour cameras in standard CMOS /." Title page, contents and abstract only, 1998. http://web4.library.adelaide.edu.au/theses/09PH/09phb6419.pdf.

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Beck, Riley D. "High Voltage Analog Design in a Standard Digital CMOS Process." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd1092.pdf.

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Al-Attar, Talal. "A 77GHz monolithic IMPATT transmitter in standard CMOS technology /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Bußmann, Arndt. "Charakterisierung und Optimierung elektrooptischer Bauelemente in Standard-CMOS-Prozessen / Characterization and Optimization of Electrooptical Devices in Standard-CMOS-Technology." Gerhard-Mercator-Universitaet Duisburg, 2006. http://www.ub.uni-duisburg.de/ETD-db/theses/available/duett-01202006-005905/.

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The thesis treats the topic of the characterization and optimization of CMOS compatible photo sensor elements (CPSE). To understand the functionality of a CPSE a pro founded basic knowledge is necessary in the fields of the ray-, wave and quantum optics. Therefore all in this context necessary and principal equations are presented at the beginning of this work. In addition belongs in particular the statistic investigation of the absorption and emission processes in the field of the quantum optics, since these processes are the basis to understand the elementary noise sources within a CPSE. Aft
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Robert, Fabien. "Solution de filtrage reconfigurable en technologie CMOS 65nm pour les architectures d'émission numériques." Thesis, Paris Est, 2011. http://www.theses.fr/2011PEST1046/document.

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Cette thèse porte sur les défis techniques et technologiques dans la conception des architectures mobiles d'émission « tout numérique » reconfigurables fonctionnant dans les bandes cellulaires pour les standards GSM, W-CDMA, HSUPA et LTE. Avec l'évolution constante des besoins en communication, les terminaux mobiles doivent être en mesure de couvrir différents standards à partir d'une même architecture, en fonction des bandes de fréquences libres, du débit et des contraintes spectrales. Dans un but de réduction des coûts, de consommation et d'une plus grande intégration, de nouvelles architect
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Atrash, Amer Hani. "Data Bus Deskewing Systems in Digital CMOS Technology." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4969.

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This dissertation presents a study of signal deskewing systems in standard CMOS technologies. The objective of this work is to understand the limitations of deskewing systems as they are applied to modern systems and present new architectures to overcome past limitations. Traditional methods for signal deskewing are explored and the general limitations of these methods are identified. Several new architectures are proposed to address the limitations of previous techniques. The systems will be investigated with regard to minimum resolution, programming time, delay, maximum data rate, full scale
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Books on the topic "Standard digital CMOS technology"

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Shoji, Masakazu. CMOS digital circuit technology. Prentice-Hall International, 1988.

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CMOS digital circuit technology. Prentice Hall, 1987.

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Shoji, Masakazu. CMOS digital circuit technology. Prentice Hall, 1988.

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Abbas, Karim. Handbook of Digital CMOS Technology, Circuits, and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1.

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Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. Low Power RF Circuit Design in Standard CMOS Technology. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-22987-9.

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Pfister, Andrea. Metastability in digital circuits with emphasis on CMOS technology amplifier. Hartung-Gorre, 1989.

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Anis, Mohab. Multi-threshold CMOS digital circuits: Managing leakage power. Kluwer Academic Publishers, 2004.

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1943-, Elmasry Mohamed I., ed. Multi-threshold CMOS digital circuits: Managing leakage power. Kluwer Academic Publishers, 2003.

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Sun, I.-Shan Michael. Development of a RF BJT in standard 0.35[mu]m CMOS technology. National Library of Canada, 2002.

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Going digital: A musician's guide to technology. Schirmer Books, 1998.

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Book chapters on the topic "Standard digital CMOS technology"

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Bertulessi, Luca. "Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications." In Special Topics in Information Technology. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-62476-7_3.

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AbstractThe fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conventional design approach for the new radio wireless applications. The advantage of the digitally-intensive design style is the possibility to implement low-power and very accurate digital calibration techniques. Most of these algorithms run in the background tracking PVT variations and either relax or, in some cases, completely remove the performance limitations due to analog impairments. Moreover, the digital loop filter area is practically negligible with respect to the one in analog PLLs. These benefits become even more relevant in the scaled CMOS technology nodes. This chapter identifies the design parameters of a standard DPLL architecture and proposes a novel locking scheme to overcome the intrinsic limitations of the digital frequency synthesizers approach. To prove this new scheme a sub-6 GHz fractional-N synthesizer has been implemented in 65 nm CMOS. The synthesizer has an output frequency from 3.59 GHz to 4.05 GHz. The integrated output jitter is 182fs and the power consumption of 5.28 mW from 1.2 V power supply leads to a FoM of −247.5 dB. This topology exploits a novel locking technique that guarantee a locking time of 5.6 s, for a frequency step of 364 MHz, despite the use of a single bit phase detector.
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Abbas, Karim. "CMOS." In Handbook of Digital CMOS Technology, Circuits, and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_3.

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Abbas, Karim. "CMOS Process." In Handbook of Digital CMOS Technology, Circuits, and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_7.

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Hari Prasad, K., Menka Sukhwani, Pooja Saxena, C. K. Pithawa, and V. B. Chandratre. "A CMOS Standard Cell-Based Time-to-Digital Converter." In Lecture Notes in Electrical Engineering. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1524-0_13.

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Garcia-Moreno, E., B. Iñiguez, M. Roca, J. Segura, and E. Isern. "Clocked Dosimeter Compatible with Digital CMOS Technology." In On-Line Testing for VLSI. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-6069-9_10.

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Plassche, Rudy. "Technology and device matching." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_12.

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Ballan, Hussein, and Michel Declercq. "High-Voltage Analog and Digital Output Interfaces." In High Voltage Devices and Circuits in Standard CMOS Technologies. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-5404-9_6.

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Oliveira, João P., and João Goes. "Discrete Time Parametric Amplification in Digital CMOS Technology." In Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-1671-5_3.

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Farazian, Mohammed, Prasad S. Gudem, and Lawrence E. Larson. "Design of Broadband Amplifiers in Digital CMOS Technology." In Fast Hopping Frequency Generation in Digital CMOS. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0490-3_5.

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Fischer, Walter. "Digital Terrestrial TV to North American ATSC Standard." In Digital Video and Audio Broadcasting Technology. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-32185-7_23.

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Conference papers on the topic "Standard digital CMOS technology"

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Pilato, Luca, Sergio Saponara, and Luca Fanucci. "Performance of digital adder architectures in 180nm CMOS standard-cell technology." In 2016 International Conference on Applied Electronics (AE). IEEE, 2016. http://dx.doi.org/10.1109/ae.2016.7577275.

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Craciun, Mihai, and Daniela Bogdan. "Digital fuse circuit based on floating gate technology in a standard CMOS process." In 2009 International Semiconductor Conference (CAS 2009). IEEE, 2009. http://dx.doi.org/10.1109/smicnd.2009.5336654.

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Innocenti, J., F. Julien, J. M. Portal, et al. "Layout optimizations to decrease internal power and area in digital CMOS standard cells." In 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). IEEE, 2015. http://dx.doi.org/10.1109/mipro.2015.7160523.

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Koh, Jeongwook, Hanseung Lee, Jung-eun Lee, et al. "Analog Baseband Chain in a 0.18 ¿m Standard Digital CMOS Technology for IEEE802.15.3a (UWB) Receiver." In TENCON 2005 - 2005 IEEE Region 10 Conference. IEEE, 2005. http://dx.doi.org/10.1109/tencon.2005.300948.

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Jeon, Duhyun, Jong Hak Baek, Dong Kyue Kim, and Byong-Deok Choi. "Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology." In 2015 Euromicro Conference on Digital System Design (DSD). IEEE, 2015. http://dx.doi.org/10.1109/dsd.2015.57.

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Ramezani, Mehrdad, Mohamed Abdalla, Ayal Shoval, et al. "An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology." In 2011 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2011. http://dx.doi.org/10.1109/isscc.2011.5746350.

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Stemmer, Jens, Joerg Ackermann, Dirk Uffmann, and Jochen Aderhold. "Digital standard cells and operational amplifiers for operation up to 250 degrees C using low-cost CMOS technology." In Microelectronic Manufacturing 1996, edited by Ih-Chin Chen, Nobuo Sasaki, Divyesh N. Patel, and Girish A. Dixit. SPIE, 1996. http://dx.doi.org/10.1117/12.250892.

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Koh, Jeongwook, Jung-Eun Lee, Chun-Deok Suh, and Hoon-Tae Kim. "A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology." In 2006 IEEE Asian Solid-State Circuits Conference. IEEE, 2006. http://dx.doi.org/10.1109/asscc.2006.357880.

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Bien, F., S. Chandramouli, H. Kim, E. Gebara, and J. Laskar. "Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology." In 2007 IEEE International Symposium on Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/iscas.2007.378310.

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Creten, Y., P. Merken, R. Mertens, W. Sansen, and C. Van Hoof. "An 8-bit Flash Analog-to-Digital Converter in standard CMOS technology functional in ultra wide temperature range from 4.2 K to 300 K." In ESSCIRC 2008 - 34th European Solid-State Circuits Conference. IEEE, 2008. http://dx.doi.org/10.1109/esscirc.2008.4681845.

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Reports on the topic "Standard digital CMOS technology"

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African Open Science Platform Part 1: Landscape Study. Academy of Science of South Africa (ASSAf), 2019. http://dx.doi.org/10.17159/assaf.2019/0047.

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This report maps the African landscape of Open Science – with a focus on Open Data as a sub-set of Open Science. Data to inform the landscape study were collected through a variety of methods, including surveys, desk research, engagement with a community of practice, networking with stakeholders, participation in conferences, case study presentations, and workshops hosted. Although the majority of African countries (35 of 54) demonstrates commitment to science through its investment in research and development (R&D), academies of science, ministries of science and technology, policies, rec
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