Relevant bibliographies by topics / Static Timing Analysis (STA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Static Timing Analysis (STA)'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Static Timing Analysis (STA)"

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Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

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To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-s
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Wang, Fangzhou, Bo Zhang, Massoud Pedram, and Sandeep Gupta. "Static Timing Analysis (STA) with Timing Bleed: Certifying Much Higher Performance for Rapid Single Flux Quantum (RSFQ) Logic." Journal of Physics: Conference Series 1559 (June 2020): 012003. http://dx.doi.org/10.1088/1742-6596/1559/1/012003.

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Chung, B., and J. B. Kuo. "Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application." Integration 41, no. 1 (2008): 9–16. http://dx.doi.org/10.1016/j.vlsi.2007.03.001.

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B. Escabal, Ingrid, Edzel G. Raffiñan, and Jefferson A. Hora. "Development of Framer/Deframer for 5Gbps JESD204B Soft IP." International Journal of Engineering & Technology 7, no. 2.11 (2018): 21. http://dx.doi.org/10.14419/ijet.v7i2.11.11000.

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This paper aimed to modify and redesign theJESD204B Full System of Lattice Semiconductor, particularly the TX deframer and RX framer modules used for the 3Gbps JESD204B soft IP to support the recently released 5Gbps JESD204B Soft IP. The modified full system instantiating the new 5Gbps JESD204B Soft IP had to be tested for functionality through RTL and gate simulation and tested for timing through Static Timing Analysis. The transaction layer’s RX framer, TX deframer, and the clock generator modules were identified to be the major blocks of the full system affected by the change in the soft IP
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E. Geralla, Leo, Melvin Joey de Guzman, and Jefferson A. Hora. "Optimization of Physically-Aware Synthesis for Digital Implementation Flow." International Journal of Engineering & Technology 7, no. 2.11 (2018): 31. http://dx.doi.org/10.14419/ijet.v7i2.11.11002.

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Synthesis is very important to have a high-quality implementation of every design. However, more accurate results could not be achieved if we will not consider the expected effects of routing delay introduced by placement and routing. This delay causes the poor timing correlation between the logical-only synthesis and Place and Route. . Now, tools with physical aware synthesis allow the user to integrate the physical information much early in the process. While such technique is readily available in the tools itself, there is no established flow to utilize the use of physical aware synthesis t
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Cao, Peng, Wei Bao, and Jingjing Guo. "An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method." Electronics 9, no. 4 (2020): 580. http://dx.doi.org/10.3390/electronics9040580.

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The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low vo
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Savari, M. Amin, and H. Jahanirad. "NN-SSTA: A deep neural network approach for statistical static timing analysis." Expert Systems with Applications 149 (July 2020): 113309. http://dx.doi.org/10.1016/j.eswa.2020.113309.

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Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.

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INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of prov
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Vygen, J. "Slack in static timing analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (2006): 1876–85. http://dx.doi.org/10.1109/tcad.2005.858348.

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Kouroussis, D., R. Ahmadi, and F. N. Najm. "Voltage-Aware Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 10 (2006): 2156–69. http://dx.doi.org/10.1109/tcad.2005.860953.

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Dissertations / Theses on the topic "Static Timing Analysis (STA)"

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Pendela, Venkata Ramanjuneya Suryanarayana. "Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits." University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

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Fu, Jingyi J. Y. "Delay Analysis of Digital Circuits Using Prony's Method." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20125.

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This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles
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Zhou, Shuo. "Static timing analysis in VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3207193.

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Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed May 18, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 110-113).
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Chapman, Roderick. "Static timing analysis and program proof." Thesis, University of York, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.261100.

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Veluswami, Senthilkumar. "Statistical static timing analysis considering process variations and crosstalk." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2545.

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Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending
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Gustavsson, Andreas. "Static Timing Analysis of Parallel Systems Using Abstract Execution." Licentiate thesis, Mälardalens högskola, Inbyggda system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-26125.

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The Power Wall has stopped the past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism.Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level.This is most often done using multiple processing cores situated on a single processor chip.The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g. a bus, to that memory and also all higher levels of memory), and to fully exploit this type of paralle
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Krishnamurthy, Sivasubramaniam T. "STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

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Johansson, Anders. "Investigation of typical 0.13 µm CMOS technology timing effects in a complex digital system on-chip." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2118.

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<p>This master's thesis deals with timing effects in complex on chip systems. It is written in cooperation with the research and development centre of Infineon Technologies. </p><p>One primary goal of all integrated circuit designers is to make the chips as small as possible. In deep sub micron designs timing effects like crosstalk have severe impact on the functionality of the chip. Therefore, accurate timing analyses must be made before the chip is ready for manufacturing. Otherwise the production yield can be reduced drastically. A case study on timing analysis with the 0.13 µm technology i
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Aftabjahani, Seyed-Abdollah. "Compact variation-aware standard cells for statistical static timing analysis." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41129.

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This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact variation-aware timing model for a standard cell in a cell library has been developed. The model incorporates variations in the input waveform and loading, process parameters, and the environment into the cell timing model. Principal component analysis (PCA) has been used to form a compact model of a set of waveforms impacted by these sources of variation. Cell characterization involves determining equations describing how waveforms
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Gebhard, Gernot [Verfasser], and Reinhard [Akademischer Betreuer] Wilhelm. "Static timing analysis tool validation in the presence of timing anomalies / Gernot Gebhard. Betreuer: Reinhard Wilhelm." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2013. http://d-nb.info/1053679947/34.

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Books on the topic "Static Timing Analysis (STA)"

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Chadha, Rakesh. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer-Verlag US, 2009.

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Bhasker, J., and Rakesh Chadha. Static Timing Analysis for Nanometer Designs. Springer, 2009.

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Static Timing Analysis for Nanometer Designs. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-93820-2.

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Bhasker, J., and Rakesh Chadha. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer, 2011.

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Onaissi, Sari. A linear-time approach for static timing analysis covering all process corners. 2007.

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Book chapters on the topic "Static Timing Analysis (STA)"

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Chakravarthi, Veena S. "Static Timing Analysis (STA)." In A Practical Approach to VLSI System on Chip (SoC) Design. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_6.

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Bhasker, J., and Rakesh Chadha. "STA Concepts." In Static Timing Analysis for Nanometer Designs. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-93820-2_2.

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Bhasker, J., and Rakesh Chadha. "Configuring the STA Environment." In Static Timing Analysis for Nanometer Designs. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-93820-2_7.

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Chung, B., and J. B. Kuo. "Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_23.

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Kukimoto, Yuji, Michel Berkelaar, and Karem Sakallah. "Static Timing Analysis." In Logic Synthesis and Verification. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-0817-5_14.

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Taraate, Vaibbhav. "Static Timing Analysis." In Digital Logic Design Using Verilog. Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2791-5_11.

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Bhathagar, Himanshu. "Static Timing Analysis." In Advanced ASIC Chip Synthesis. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4419-8668-9_12.

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Taraate, Vaibbhav. "Static Timing Analysis." In Advanced HDL Synthesis and SOC Prototyping. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8776-9_10.

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Langenbach, Marc, Stephan Thesing, and Reinhold Heckmann. "Pipeline Modeling for Timing Analysis." In Static Analysis. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45789-5_22.

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Harcourt, Ed, Jon Mauney, and Todd Cook. "From processor timing specifications to static instruction scheduling." In Static Analysis. Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/3-540-58485-4_36.

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Conference papers on the topic "Static Timing Analysis (STA)"

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ElBahey, Mohamed N., DiaaEldin S. Khalil, and Hani F. Ragai. "Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)." In 2015 International 3D Systems Integration Conference (3DIC). IEEE, 2015. http://dx.doi.org/10.1109/3dic.2015.7334604.

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Amin, Chirayu S., Noel Menezes, Kip Killpack, et al. "Statistical static timing analysis." In the 42nd annual conference. ACM Press, 2005. http://dx.doi.org/10.1145/1065579.1065751.

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Guo, Zizheng, Tsung-Wei Huang, and Yibo Lin. "GPU-accelerated static timing analysis." In ICCAD '20: IEEE/ACM International Conference on Computer-Aided Design. ACM, 2020. http://dx.doi.org/10.1145/3400302.3415631.

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Lin, Ma, Shen Haihua, and Hu Weiwu. "Simulation Acceleration for Dynamic Timing Analysis with Static Timing Analysis." In TENCON 2006 - 2006 IEEE Region 10 Conference. IEEE, 2006. http://dx.doi.org/10.1109/tencon.2006.343809.

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Hahn, Sebastian, and Daniel Grund. "Relational Cache Analysis for Static Timing Analysis." In 2012 24th Euromicro Conference on Real-Time Systems (ECRTS). IEEE, 2012. http://dx.doi.org/10.1109/ecrts.2012.14.

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Fatemi, H., and P. Tehrani. "Crosstalk timing windows overlap in statistical static timing analysis." In 2013 14th International Symposium on Quality Electronic Design (ISQED 2013). IEEE, 2013. http://dx.doi.org/10.1109/isqed.2013.6523617.

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Moore, David M., Jeffrey A. Fredenburgh, Muhammad Faisal, and David D. Wentzloff. "Static timing analysis for ring oscillators." In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2018. http://dx.doi.org/10.1109/aspdac.2018.8297371.

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Imai, Masanori, Takashi Sato, Noriaki Nakayama, and Kazuya Masu. "Non-parametric statistical static timing analysis." In the 45th annual conference. ACM Press, 2008. http://dx.doi.org/10.1145/1391469.1391649.

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Bing Li, Ning Chen, M. Schmidt, W. Schneider, and U. Schlichtmann. "On hierarchical statistical static timing analysis." In 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090869.

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Lee, Benjamin N., Li-C. Wang, and Magdy S. Abadir. "Refined statistical static timing analysis through." In the 43rd annual conference. ACM Press, 2006. http://dx.doi.org/10.1145/1146909.1146952.

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Reports on the topic "Static Timing Analysis (STA)"

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Mettala Gilla, Swetha. Library Characterization and Static Timing Analysis of Single-Track Circuits in GasP. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.273.

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