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Relevant bibliographies by topics / Static Timing Analysis (STA) / Dissertations / Theses

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Dissertations / Theses on the topic 'Static Timing Analysis (STA)'

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Published: 4 June 2021

Last updated: 1 February 2022

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1

Pendela, Venkata Ramanjuneya Suryanarayana. "Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits." University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

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2

Fu, Jingyi J. Y. "Delay Analysis of Digital Circuits Using Prony's Method." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20125.

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This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in DTA(Dynamic Timing Analysis) and delay look-up table in STA(Static Timing Analysis). Given some equally spaced output values, the traditional Prony's method can be used to extract poles and residues of a linear system, i.e. to characterize a waveform using an exponential function. In this thesis, not only values but also equally spaced derivatives are tested. Still using same idea of the traditional Prony's method, poles

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3

Zhou, Shuo. "Static timing analysis in VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3207193.

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Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed May 18, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 110-113).

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4

Chapman, Roderick. "Static timing analysis and program proof." Thesis, University of York, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.261100.

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5

Veluswami, Senthilkumar. "Statistical static timing analysis considering process variations and crosstalk." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2545.

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Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending

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6

Gustavsson, Andreas. "Static Timing Analysis of Parallel Systems Using Abstract Execution." Licentiate thesis, Mälardalens högskola, Inbyggda system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-26125.

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The Power Wall has stopped the past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism.Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level.This is most often done using multiple processing cores situated on a single processor chip.The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g. a bus, to that memory and also all higher levels of memory), and to fully exploit this type of paralle

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7

Krishnamurthy, Sivasubramaniam T. "STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

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8

Johansson, Anders. "Investigation of typical 0.13 µm CMOS technology timing effects in a complex digital system on-chip." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2118.

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<p>This master's thesis deals with timing effects in complex on chip systems. It is written in cooperation with the research and development centre of Infineon Technologies. </p><p>One primary goal of all integrated circuit designers is to make the chips as small as possible. In deep sub micron designs timing effects like crosstalk have severe impact on the functionality of the chip. Therefore, accurate timing analyses must be made before the chip is ready for manufacturing. Otherwise the production yield can be reduced drastically. A case study on timing analysis with the 0.13 µm technology i

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9

Aftabjahani, Seyed-Abdollah. "Compact variation-aware standard cells for statistical static timing analysis." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41129.

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This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact variation-aware timing model for a standard cell in a cell library has been developed. The model incorporates variations in the input waveform and loading, process parameters, and the environment into the cell timing model. Principal component analysis (PCA) has been used to form a compact model of a set of waveforms impacted by these sources of variation. Cell characterization involves determining equations describing how waveforms

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10

Gebhard, Gernot [Verfasser], and Reinhard [Akademischer Betreuer] Wilhelm. "Static timing analysis tool validation in the presence of timing anomalies / Gernot Gebhard. Betreuer: Reinhard Wilhelm." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2013. http://d-nb.info/1053679947/34.

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11

Chou, Sharon H. "Computationally efficient characterization of standard cells for statistical static timing analysis." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52762.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 44-45).<br>We propose a computationally efficient statistical static timing analysis (SSTA) technique that addresses intra-die variations at near-threshold to sub-threshold supply voltage, simulated on a scaled 32nm CMOS standard cell library. This technique would characterize the propagat

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12

WANG, CHIH-KUAN. "AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

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13

Mettala, Gilla Swetha. "Library Characterization and Static Timing Analysis of Single-Track Circuits in GasP." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/273.

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Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showe

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14

Schlickling, Marc [Verfasser], and Reinhard [Akademischer Betreuer] Wilhelm. "Timing model derivation : static analysis of hardware description languages / Marc Schlickling. Betreuer: Reinhard Wilhelm." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2013. http://d-nb.info/1052779859/34.

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15

Zhang, Michael Longqiang. "A partitioning approach for GPU accelerated level-based on-chip variation static timing analysis." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/fullcit?p1477953.

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Thesis (M.S.)--University of California, San Diego, 2010.<br>Title from first page of PDF file (viewed July 16, 2010). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (leaves 52-53).

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16

Kim, Hyun Sung. "Statistical static timing analysis considering the impact of power supply noise in VLSI circuits." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1902.

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17

Choi, Munkang. "Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14544.

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As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit performance degradation comes from deterministic within-die variation from lithography imperfections and Cu interconnect chemical mechanical polishing (CMP). To determine how these wi

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18

Machado, Lucas. "KL-cut based remapping." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/116138.

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Este trabalho introduz o conceito de cortes k e cortes kl sobre um circuito mapeado, em uma representação netlist. Esta nova abordagem é derivada do conceito de cortes k e cortes kl sobre AIGs (and inverter graphs), respeitando as diferenças entre essas duas formas de representar um circuito. As principais diferenças são: (1) o número de entradas em um nodo do grafo, e (2) a presença de inversores e buffers de forma explícita no circuito mapeado. Um algoritmo para enumerar cortes k e cortes kl é proposto e implementado. A principal motivação de usar cortes kl sobre circuitos mapeados é para re

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19

Neikter, Carl-Fredrik. "Cache Prediction and Execution Time Analysis on Real-Time MPSoC." Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15394.

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<p>Real-time systems do not only require that the logical operations are correct. Equally important is that the specified time constraints always are complied. This has successfully been studied before for mono-processor systems. However, as the hardware in the systems gets more complex, the previous approaches become invalidated. For example, multi-processor systems-on-chip (MPSoC) get more and more common every day, and together with a shared memory, the bus access time is unpredictable in nature. This has recently been resolved, but a safe and not too pessimistic cache analysis approach for

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20

Wang, Hsuan-Wei, and 王鉉崴. "A Fast CUDA-Based Static Timing Analysis (STA) Engine and Its Application." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/67677336397514540440.

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碩士<br>國立交通大學<br>電機工程學系<br>102<br>Graphics processing unit (GPU) enables the possibility of parallel computing for Static Timing Analysis (STA). However, memory access and synchronization between cores has become more difficult in STA and thus its algorithm needs to be re-designed. In this work, we developed a CUDA-based STA engine that incorporates cell levelization and type sorting (CLTS), timing table restructuring (TTR), table indexing by texture (TIT) and hardware-accelerated rendering (HAR) for high-parallelism. Cell levelization and type sorting (CLTS) levelize cells and sort their types

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21

Kuo, Tien-Yu, and 郭天鈺. "On Efficient Static Timing Analysis." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/57471513721466677653.

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碩士<br>國立清華大學<br>資訊工程學系<br>100<br>Since the performance of a circuit is always a key factor to be considered, timing analysis, whose result guides timing optimization, is the most important procedure in the design flow. Timing analysis is the step to evaluates the timing behavior of a circuit and checks whether the design can meet timing constraints or not. Current industrial EDA tools still use Static Timing Analysis (STA) as the mainstream. Due to its importance in the design flow, we need to carefully consider various factors so as to have better efficiency. In this thesis, we study two impo

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22

Liu, Chi-Wei. "Slew-aware statistical static timing analysis." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2008200810051300.

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23

Hsiao-Fen, Wu. "Issues on Coupling-Aware Static Timing Analysis." 2003. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611352098.

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24

Wu, Hsiao-Fen, and 吳曉芬. "Issues on Coupling-Aware Static Timing Analysis." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/60646119659976975284.

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碩士<br>元智大學<br>資訊工程學系<br>91<br>Semiconductor process technology has advanced to the point where wire delay is becoming relatively larger than gate delay such that gate delay no longer dominates the longest path delay. Especially, coupling capacitance becomes a dominant factor in deciding wire delay. Crosstalk-induced delay becomes quite significant and difficult to determine because of dependency on neighboring signals. To more accurately compute coupling delay, an iterative process is used to compute the switching window of a signal in a STA. However, the switching windows are converged to dif

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25

Tsai, Chen-Kuan, and 蔡正寬. "Static Timing Analysis for Threshold Logic Circuits." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/33554396451504851155.

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碩士<br>國立清華大學<br>資訊工程學系<br>100<br>Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. On the other hand, the delay models of threshold logic gates accompanied with their implementation development have also been proposed. However, there has not been a timing analysis algorithm for threshold logic circuits to the best of

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26

Yu, Wen-Yi, and 游汶艗. "Clock Skew Detection Based on Statistical Static Timing Analysis." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/44604011983815912154.

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27

Li, Bing [Verfasser]. "Hierarchical statistical static timing analysis considering process variations / Bing Li." 2010. http://d-nb.info/1005327521/34.

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28

Seth, Kiran R. "Frequency-aware static timing analysis for power-aware embedded architectures." 2003. http://www.lib.ncsu.edu/theses/available/etd-12102003-040743/unrestricted/etd.pdf.

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29

Kuo, Jen-Wei. "Current Source Model for Static Timing Analysis with Sleep Transistor." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2503200800433500.

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30

Kuo, Jen-Wei, and 郭人瑋. "Current Source Model for Static Timing Analysis with Sleep Transistor." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32072878025557450586.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>96<br>Recent research has shown that the increasing leakage power is becoming a critical issue in the design of low power portable IC. To cope with the problem of leakage power, MTCMOS technology such as implementation of a sleep transistor has been proven effect in power reduction. However the existing Static Timing Analysis methods have not focused on this issue. This thesis presents a methodology for synthesizing a new Current Source Model from Spice models. Then with the newly synthesized Current Source Model, a complete procedure for the timing analysis of a ci

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31

Gaspar, Nuno Miguel Pires. "Timing analysis: from predictions to certificates." Master's thesis, 2010. http://hdl.handle.net/10400.6/3764.

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In real-time systems timing properties must be satisfied in order to guarantee that deadlines will be met. In this context, the calculation of theworst-case execution time(WCET) is of paramount importance for schedulability analysis. However, this problem can be difficult if the underlying architecture possesses features like caches and pipelines. This thesis presents all the necessary steps for the safe and preciseWCET calculation. We focus ourselves in the use of static analysis-based methods, and in the ARMarchitecture as target platform. Moreover, in order to ensure the correctness of ou

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32

Heloue, Khaled R. "Circuit Timing and Leakage Analysis in the Presence of Variability." Thesis, 2010. http://hdl.handle.net/1807/26186.

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Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided

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33

Ou, Yu-Hao, and 歐育豪. "Implement Low Power IC Design with Statistical Static Timing Analysis in 90nm CMOS Technology." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/83930962103437109676.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>99<br>As the mobile electronic products development are more and more popular such as mobile phone, digital camera, PDA…etc. Each of company releases variable kind of mobile products, and every portable machine has plenty of functions. A low power consumption design is a significant issue which academics and engineers concern. It would be a major progress if the approach which can drop off the power consumption successfully. The mobile electronic products have more application programs than before and the size of LCD increases continuously, so that the power consum

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34

Ko, Xue-Da, and 柯學達. "Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/38865106492560460069.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>101<br>With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is also becoming an important issue. If we cannot reduce the power consumption effectively such that it will cause the IC overheat and its functional failure. In order to preserving the normal operation and extend the battery life of the chips. Nowadays, the chips are usually saving the power consumption by reducing the supply voltage. However, it will affect the performance of

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35

Das, Bishnu Prasad. "Random Local Delay Variability : On-chip Measurement And Modeling." Thesis, 2009. http://hdl.handle.net/2005/1008.

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This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA). Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random loc

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36

Feng, Zhuo. "Modeling and Analysis of Large-Scale On-Chip Interconnects." 2009. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142.

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As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high dimensional process-voltage-temperature (PVT) variations demand much more modeling and analysis efforts than ever before, while the analysis of large scale on-chip interconnects that requires solving tens of millions of unknowns imposes great challenges in computer aided design areas. This dissertation presents new methodologies for addressing the

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