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Journal articles on the topic 'Static Timing Analysis (STA)'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

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To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-s

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2

Wang, Fangzhou, Bo Zhang, Massoud Pedram, and Sandeep Gupta. "Static Timing Analysis (STA) with Timing Bleed: Certifying Much Higher Performance for Rapid Single Flux Quantum (RSFQ) Logic." Journal of Physics: Conference Series 1559 (June 2020): 012003. http://dx.doi.org/10.1088/1742-6596/1559/1/012003.

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3

Chung, B., and J. B. Kuo. "Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application." Integration 41, no. 1 (2008): 9–16. http://dx.doi.org/10.1016/j.vlsi.2007.03.001.

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4

B. Escabal, Ingrid, Edzel G. Raffiñan, and Jefferson A. Hora. "Development of Framer/Deframer for 5Gbps JESD204B Soft IP." International Journal of Engineering & Technology 7, no. 2.11 (2018): 21. http://dx.doi.org/10.14419/ijet.v7i2.11.11000.

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This paper aimed to modify and redesign theJESD204B Full System of Lattice Semiconductor, particularly the TX deframer and RX framer modules used for the 3Gbps JESD204B soft IP to support the recently released 5Gbps JESD204B Soft IP. The modified full system instantiating the new 5Gbps JESD204B Soft IP had to be tested for functionality through RTL and gate simulation and tested for timing through Static Timing Analysis. The transaction layer’s RX framer, TX deframer, and the clock generator modules were identified to be the major blocks of the full system affected by the change in the soft IP

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5

E. Geralla, Leo, Melvin Joey de Guzman, and Jefferson A. Hora. "Optimization of Physically-Aware Synthesis for Digital Implementation Flow." International Journal of Engineering & Technology 7, no. 2.11 (2018): 31. http://dx.doi.org/10.14419/ijet.v7i2.11.11002.

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Synthesis is very important to have a high-quality implementation of every design. However, more accurate results could not be achieved if we will not consider the expected effects of routing delay introduced by placement and routing. This delay causes the poor timing correlation between the logical-only synthesis and Place and Route. . Now, tools with physical aware synthesis allow the user to integrate the physical information much early in the process. While such technique is readily available in the tools itself, there is no established flow to utilize the use of physical aware synthesis t

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6

Cao, Peng, Wei Bao, and Jingjing Guo. "An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method." Electronics 9, no. 4 (2020): 580. http://dx.doi.org/10.3390/electronics9040580.

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The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low vo

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7

Savari, M. Amin, and H. Jahanirad. "NN-SSTA: A deep neural network approach for statistical static timing analysis." Expert Systems with Applications 149 (July 2020): 113309. http://dx.doi.org/10.1016/j.eswa.2020.113309.

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8

Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.

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INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of prov

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9

Vygen, J. "Slack in static timing analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 9 (2006): 1876–85. http://dx.doi.org/10.1109/tcad.2005.858348.

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10

Kouroussis, D., R. Ahmadi, and F. N. Najm. "Voltage-Aware Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 10 (2006): 2156–69. http://dx.doi.org/10.1109/tcad.2005.860953.

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11

S. R, Ramesh, and R. Jayaparvathy. "Improved Statistical Static Timing Analysis Using Refactored Timing Graphs." Journal of Computational and Theoretical Nanoscience 13, no. 11 (2016): 8879–84. http://dx.doi.org/10.1166/jctn.2016.6057.

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12

Forzan, Cristiano, and Davide Pandini. "Statistical static timing analysis: A survey." Integration 42, no. 3 (2009): 409–35. http://dx.doi.org/10.1016/j.vlsi.2008.10.002.

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13

Blaauw, D., V. Zolotov, and S. Sundareswaran. "Slope propagation in static timing analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 10 (2002): 1180–95. http://dx.doi.org/10.1109/tcad.2002.802274.

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14

Hashimoto, M., Y. Yamada, and H. Onodera. "Equivalent Waveform Propagation for Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 4 (2004): 498–508. http://dx.doi.org/10.1109/tcad.2004.825858.

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15

Chapman, Roderick, Alan Burns, and Andy Wellings. "Static worst-case timing analysis of Ada." ACM SIGAda Ada Letters XIV, no. 5 (1994): 88–91. http://dx.doi.org/10.1145/192867.192873.

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16

Jourdan, M., and F. Maraninchi. "Static timing analysis of real-time systems." ACM SIGPLAN Notices 30, no. 11 (1995): 79–87. http://dx.doi.org/10.1145/216633.216664.

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17

Chang, L. L. "Static timing analysis of high-speed boards." IEEE Spectrum 34, no. 3 (1997): 67–74. http://dx.doi.org/10.1109/6.576012.

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18

Katam, Naveen Kumar, and Massoud Pedram. "Timing Characterization for Static Timing Analysis of Single Flux Quantum Circuits." IEEE Transactions on Applied Superconductivity 29, no. 6 (2019): 1–8. http://dx.doi.org/10.1109/tasc.2019.2891166.

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19

Murray, Kevin E., Andrea Suardi, Vaughn Betz, and George Constantinides. "Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 4 (2019): 719–32. http://dx.doi.org/10.1109/tcad.2018.2821563.

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20

Merrett, Michael, and Mark Zwolinski. "Monte Carlo Static Timing Analysis with statistical sampling." Microelectronics Reliability 54, no. 2 (2014): 464–74. http://dx.doi.org/10.1016/j.microrel.2013.10.016.

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21

Wolf, Fabian, Judita Kruse, and Rolf Ernst. "Timing and power measurement in static software analysis." Microelectronics Journal 33, no. 1-2 (2002): 91–100. http://dx.doi.org/10.1016/s0026-2692(01)00108-2.

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22

Valentian, A., O. Thomas, A. Vladimirescu, and A. Amara. "Modeling subthreshold SOI logic for static timing analysis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 6 (2004): 662–69. http://dx.doi.org/10.1109/tvlsi.2004.827602.

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23

Dasdan, Ali, and Ivan Hom. "Handling inverted temperature dependence in static timing analysis." ACM Transactions on Design Automation of Electronic Systems 11, no. 2 (2006): 306–24. http://dx.doi.org/10.1145/1142155.1142158.

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24

Mondal, A., P. P. Chakrabarti, and P. Dasgupta. "Statistical static timing analysis using symbolic event propagation." IET Circuits, Devices & Systems 1, no. 4 (2007): 283. http://dx.doi.org/10.1049/iet-cds:20060318.

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25

Kasturi Rangan, Jahnavi, Nasim Pour Aryan, Jens Bargfrede, Lantao Wang, Christian Funke, and Helmut Graeb. "Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 2 (2020): 401–14. http://dx.doi.org/10.1109/tcsi.2019.2926149.

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26

Das, Debasish, Kip Killpack, Chandramouli Kashyap, Abhijit Jas, and Hai Zhou. "Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 3 (2010): 466–78. http://dx.doi.org/10.1109/tcad.2009.2035532.

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27

Xiao, Tong, and Malgorzata Marek-Sadowska. "Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis." VLSI Design 15, no. 3 (2002): 647–66. http://dx.doi.org/10.1080/1065514021000012264.

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Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals. In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis. We propose an efficient method to compute a signal's earliest and latest arrival times when timing windows and slew rate ranges are known for its inputs and its coupling neighbors' inputs. We show that iteratively updating timing windows is necessary when signals on the same path are mu

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28

Zhang, Wei, and Jun Yan. "Static Timing Analysis of Shared Caches for Multicore Processors." Journal of Computing Science and Engineering 6, no. 4 (2012): 267–78. http://dx.doi.org/10.5626/jcse.2012.6.4.267.

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29

Salman, E., A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman. "Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 6 (2007): 1114–25. http://dx.doi.org/10.1109/tcad.2006.885834.

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30

Guo Yu, Wei Dong, Zhuo Feng, and Peng Li. "Statistical Static Timing Analysis Considering Process Variation Model Uncertainty." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 10 (2008): 1880–90. http://dx.doi.org/10.1109/tcad.2008.2003302.

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31

Chapman, Roderick, Alan Burns, and Andy Wellings. "Combining static worst-case timing analysis and program proof." Real-Time Systems 11, no. 2 (1996): 145–71. http://dx.doi.org/10.1007/bf00365316.

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32

Veetil, Vineeth, Kaviraj Chopra, David Blaauw, and Dennis Sylvester. "Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 6 (2011): 852–65. http://dx.doi.org/10.1109/tcad.2011.2108030.

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33

Krimer, Evgeni, Isaac Keslassy, Avinoam Kolodny, Isask’har Walter, and Mattan Erez. "Static timing analysis for modeling QoS in networks-on-chip." Journal of Parallel and Distributed Computing 71, no. 5 (2011): 687–99. http://dx.doi.org/10.1016/j.jpdc.2010.10.003.

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34

Ramprasath, S., Madiwalar Vijaykumar, and Vinita Vasudevan. "A Skew-Normal Canonical Model for Statistical Static Timing Analysis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 6 (2016): 2359–68. http://dx.doi.org/10.1109/tvlsi.2015.2501370.

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35

Bhatnagar, Pulkit, and Sachin Garg. "Dynamic Threshold Delay Characterization Model for Improved Static Timing Analysis." Journal of Electronic Testing 30, no. 5 (2014): 495–504. http://dx.doi.org/10.1007/s10836-014-5469-1.

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36

B., Sowmya K., and Thanushree M. "Characterization and hierarchical static timing analysis of mixed-signal design." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 1 (2021): 18. http://dx.doi.org/10.11591/ijres.v10.i1.pp18-24.

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As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.

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37

Lizheng Zhang, W. Chen, Y. Hu, and C. C. Chen. "Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 6 (2006): 1183–91. http://dx.doi.org/10.1109/tcad.2005.855979.

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38

Ramalingam, Anand, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, and David Z. Pan. "An accurate sparse-matrix based framework for statistical static timing analysis." Integration 45, no. 4 (2012): 365–75. http://dx.doi.org/10.1016/j.vlsi.2011.03.002.

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39

Foreman, E. A., P. A. Habitz, M.-C. Cheng, and C. Tamon. "Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 11 (2011): 1758–62. http://dx.doi.org/10.1109/tcad.2011.2162066.

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40

Ciptaning, Karsa, Yuhanis Yunus, and Sofyan M. Saleh. "ANALISIS STABILITAS LERENG DENGAN KONTRUKSI DINDING PENAHAN TANAH TIPE COUNTERFORT." Jurnal Arsip Rekayasa Sipil dan Perencanaan 1, no. 2 (2018): 58–68. http://dx.doi.org/10.24815/jarsp.v1i2.10942.

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The Babahrot - Blangkejeren road of a segment is one of the most frequently affected by a landslide due to its location in the range of hills in Aceh Province. The road is the only one facilities to connect between both cities, and it is the only one to access for crop trading as well other plantation. The impact of landslide causes disconnection from Gayo Lues to South West Aceh or vice versa. Therefore, it is necessary to study the slope reinforcement at the bottom of the road construction with retaining wall counterfort type. This study aims to analyze slope stability by obtaining reasonabl

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41

Yang, Li Ping. "Analysis on Dynamic Fault Tree Based on Fuzzy Set." Applied Mechanics and Materials 110-116 (October 2011): 2416–20. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.2416.

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In case of fault tree analysis of large complex system, the probability of bottom event in dynamic fault tree is uncertain in some cases. To address the problem, the paper presented a dynamic fault tree analysis method based on fuzzy set computation. The method separates logic attributes and timing attributes of dynamic logic gates. It can convert dynamic fault tree into static fault tree not considering timing constraints and obtain minimum cut set of static fuzzy fault tree with set operations, then the concept of minimum cut set is extended to dynamical minimum cut sequence. Thus, the dynam

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42

Terada, Haruhiko, Takayuki Fukuoka, Akira Tsuchiya, and Hidetoshi Onodera. "Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis." IPSJ Transactions on System LSI Design Methodology 1 (2008): 116–25. http://dx.doi.org/10.2197/ipsjtsldm.1.116.

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43

Zhang, Bo, and Massoud Pedram. "qSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits." IEEE Transactions on Applied Superconductivity 30, no. 5 (2020): 1–9. http://dx.doi.org/10.1109/tasc.2020.2970218.

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44

Hassoun, S., C. Cromer, and E. Calvillo-Gamez. "Static timing analysis for level-clocked circuits in the presence of crosstalk." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 9 (2003): 1270–77. http://dx.doi.org/10.1109/tcad.2003.816209.

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45

Onaissi, Sari, and Farid N. Najm. "A Linear-Time Approach for Static Timing Analysis Covering All Process Corners." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 7 (2008): 1291–304. http://dx.doi.org/10.1109/tcad.2008.923635.

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46

Shebaita, Ahmed, Debasish Das, Dusan Petranovic, and Yehea Ismail. "A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 8 (2011): 1258–62. http://dx.doi.org/10.1109/tcad.2011.2121110.

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47

Foreman, Eric A., Peter A. Habitz, Ming-C. Cheng, and Chandu Visweswariah. "A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 8 (2012): 1293–97. http://dx.doi.org/10.1109/tcad.2012.2190068.

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48

Xie, L., and A. Davoodi. "Fast and accurate statistical static timing analysis with skewed process parameter variation." IET Circuits, Devices & Systems 2, no. 2 (2008): 187. http://dx.doi.org/10.1049/iet-cds:20070189.

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49

Altmeyer, Sebastian, Liliana Cucu-Grosjean, and Robert I. Davis. "Static probabilistic timing analysis for real-time systems using random replacement caches." Real-Time Systems 51, no. 1 (2015): 77–123. http://dx.doi.org/10.1007/s11241-014-9218-4.

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50

Pleva, Matúš, Patrick Bours, Stanislav Ondáš, and Jozef Juhár. "Improving static audio keystroke analysis by score fusion of acoustic and timing data." Multimedia Tools and Applications 76, no. 24 (2017): 25749–66. http://dx.doi.org/10.1007/s11042-017-4571-7.

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