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Journal articles on the topic 'Stencil printing processes'

Author: Grafiati
Published: 4 June 2021
Last updated: 10 February 2022

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1

Huang, Chien-Yi. "Applying the Taguchi parametric design to optimize the solder paste printing process and the quality loss function to define the specifications." Soldering & Surface Mount Technology 30, no. 4 (September 3, 2018): 217–26. http://dx.doi.org/10.1108/ssmt-03-2017-0010.

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Purpose This research aims to study the stencil printing process of the quad flat package (QFP) component with a pin pitch of 0.4 mm. After the optimization of the printing process, the desired inspection specification is determined to reduce the expected total process loss. Design/methodology/approach Static Taguchi parametric design is applied while considering the noise factors possibly affecting the printing quality in the production environment. The Taguchi quality loss function model is then proposed to evaluate the two types of inspection strategies. Findings The optimal parameter-level treatment for the solder paste printing process includes a squeegee pressure of 11 kg, a stencil snap-off of 0.14 mm, a cleaning frequency of the stencil once per printing and using an air gun after stencil wiping. The optimal upper and lower specification limits are 119.8 µm and 110.3 µm, respectively. Originality/value Noise factors in the production environment are considered to determine the optimal printing process. For specific components, the specification is established as a basis for subsequent processes or reworks.
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2

Rodriguez, G., and D. F. Baldwin. "Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes." Journal of Electronic Packaging 121, no. 3 (September 1, 1999): 169–78. http://dx.doi.org/10.1115/1.2792680.

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Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.
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3

Al-Ma'aiteh, Tareq Ibrahim, Oliver Krammer, and Balázs Illés. "Transient Numerical Modelling of the Pin-in-Paste Technology." Applied Sciences 11, no. 10 (May 19, 2021): 4670. http://dx.doi.org/10.3390/app11104670.

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The pin-in-paste technology is an advancing soldering technology for assembling complex electronic products, which include both surface-mounted and through-hole components. A computational fluid dynamics model was established to investigate the stencil printing step of this technology, where the hole-filling by the solder pastes is the most critical factor for acquiring reliable solder joints. The geometry of the transient numeric model included the printing squeegee, the stencil, and the through-holes of a printed circuit board with different geometries and arrangements. A two-phase fluid model (solder paste + air) was applied, utilizing the Volume of Fluid method (VoF). The rheological properties of the solder paste were addressed by an exhaustive viscosity model. It was found that the set of through-holes affected the flow-field and yielded a decrease in the hole-filling if they were arranged in parallel with the travelling direction of the printing squeegee. Similar disturbance on the flow-field was found for oblong-shaped through-holes if they were arranged in parallel with the squeegee movement. The findings imply that the arrangement of a set of through-holes and the orientation of oblong-shaped through-holes should be optimized even in the early design phase of electronic products and during the set of assembly processes. The soldering failures in pin-in-paste technology can be reduced by these early design-phase considerations, and the first-pass yield of electronic soldering technologies can be enhanced.
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4

Liang, Hanzhuang, Linh Rolland, Floriana Suriawidjaja, Mani Ahmadi, and Heakyoung Park. "Precise solder dispensing in high-throughput micro-device packaging applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 001284–94. http://dx.doi.org/10.4071/2014dpc-wa21.

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Advanced micro-device packaging sets high and dynamic standard for its supplier industries for speed, precision and flexibility. A high-precision and high-throughput solder paste dispensing process has been developed to fill the gap between novel packaging design and traditional processes of stencil printing and slow dispensing. This process is being used in 25 PCBA production lines to package smart phones, MEMS devices and automobile control panels. These production lines are in full service 24/6 with each dispense system running at 2500unit per hour for simple MEMS patterns, 144uph for complex smart phone patterns and 6uph of full automobile control panels. A well-controlled valve design is applied to achieve high dispensing accuracy at fast speeds. This has removed process design barriers related to dispensing and has matched the high-end platform capability. This process also provides packaging designers with a flexibility superior to the existing solder printing process. The dispense pattern and route can be modified at cost, in minutes and during any step in the design or the assembly stage. Dispensed shapes include dots, lines, rectangle frames and annular rings, with fine edge definition 40um or less. This process can cover a wide range of pattern dimensions between 0.18mm and 100mm. Solder pastes that can be dispensed during this process have 80~90% metal content, type 4 to 6 mesh size. New processes are under development to further push limitations on throughput, dimension, flexibility and material dispensability.
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5

Perrone, R., H. Bartsch de Torres, M. Hoffmann, M. Mach, and J. Müller. "Miniaturized Embossed Low Resistance Fine Line Coils in LTCC." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 42–48. http://dx.doi.org/10.4071/1551-4897-6.1.42.

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Embedded ceramic coils stand out because of their excellent dielectric, thermal, and RF properties. However the relatively high sheet resistance (low thickness) of printed thick-film conductors restricts their functionality for applications where current values of several amps are needed. Using embossed structures it is possible to manufacture conductors with increased thickness and low resistance on LTCC tapes. The manufacturing process for wide conductors with high dimensional accuracy was shown in previous publications. In this work fine line embossed structures with line widths and spaces of 50 and 75 μm respectively were realized. The cross section of the embossed channels was about 50 μm. The fine line screen printing, stencil printing, and the photo definable Fodel® processes were used to fill the small structures with thick-film ink. The whole process was used to manufacture several types of low resistance coils in LTCC that can be used for current values up to approximately 3 A. They were realized as embedded as well as SMD components. Thus, the functionality of LTCC modules and LTCC SMD coils was increased. In this paper, the filling and patterning characteristics of all structuring methods are compared and the results discussed. Furthermore, the advantages of this process are shown by electrical, thermal, and RF measurements.
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6

Torabi, N. Meetra, Janet K. Lumpp, and James E. Lumpp. "Materials Selection and Processing Techniques for Small Spacecraft Solar Cell Arrays." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000789–99. http://dx.doi.org/10.4071/isom-2011-wp4-paper3.

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Body mounted germanium substrate solar cell arrays form the faces of many small satellite designs to provide the primary power source on orbit. High efficiency solar cells are made affordable for University scale satellite programs as triangular devices trimmed from wafer scale solar cells. The smaller cells allow the array designs to pack tightly around antenna mounts and payload instruments, giving the board design more flexibility. We are investigating the reliability of solar cells attached to FR-4 and carbon core laminate printed circuit boards. FR-4 circuit boards have significantly higher thermal expansion coefficients and lower thermal conductivities than germanium. This thermal expansion coefficient mismatch between the FR-4 board and the components used cause major concern for the power system when considering a failure of the solar cells, such as a series of cracked cells or faulty solder joints. These failures are most likely to happen with a longer orbital lifetime and longer exposure to the harsh environment the satellite will experience while in orbit. Carbon core laminates provide an advanced alternative because the core thickness can be selected to more closely match the device substrate, or at least provide a wider thermal expansion coefficient range to match the components on the board. We are also comparing various methods of attaching the solar cells to the printed circuit boards, using solder paste alone and in parallel with a silicone adhesive, considering the application of these adhesives by comparing the solder joints under x-ray when applied by screen printing versus stencil printing, and looking closely at the cleaning processes for array assembly. Storage, vacuum exposure, thermal cycling, functional and vibration testing will be used to compare the survivability and performance of the solar arrays.
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7

Nah, Jae-Woong, Peter A. Gruber, Paul A. Lauro, and Claudius Feger. "Mask and mask-less injection molded solder (IMS) technology for fine pitch substrate bumping." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000348–54. http://dx.doi.org/10.4071/isom-2010-tp5-paper5.

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We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting. In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated. In mask-less IMS, the pure molten solder is directly filled into the opening volume of the SR. After the injection of molten solder, solidification of the solder under low oxygen leads to solder protrusions above the SR surface because 100 % pure solder is filled into the whole SR opening volume. For a 150 μm pitch commercial substrate, we demonstrated minimum bump heights of 15 μm over the 20 μm thick SR. Since there is no need to align mask and substrate, the maskless IMS method lowers process costs and makes the process more reliable. By manipulating the opening in the SR, it is possible to enable variations in the height of the solder bumps. Flux or formic acid is not needed during solder injection of both described processes, but a low oxygen environment must be maintained. In this paper, we will discuss laboratory scale processes and bump inspection data, along with the discussion of manufacturing strategies for IMS solder bumping technology for fine pitch organic substrates.
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8

Thomas, T., S. Voges, T. Braun, S. Raatz, R. Kahle, K. F. Becker, M. Koch, et al. "High viscosity paste dosing for microelectronic applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000345–50. http://dx.doi.org/10.4071/isom-2016-wp45.

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Abstract Today's microelectronics packaging especially for SiPs relies on the processing of a wide variety of materials Such as materials for components, substrates, contact materials (solder & adhesives) and encapsulants. Most materials are processed as bulk material but precision dosing of pastes is key to many assembly processes. Examples are dosing of solder paste, typically done by stencil printing, underfilling for Flip Chip encapsulation, typically done by dispensing or jetting, or glob top encapsulation of Chip on Board assemblies, where also dispensing is the typical process. When working with those paste materials, viscosity is one of the key parameters for processing, and viscosities too high do not allow dosing of the materials, not even to transport the material from a reservoir to the dosing head, which may be a simple needle or a jet valve. [1,2] To overcome this obstacle, i.e. to dose materials of high viscosity precisely and homogeneously from a syringe to the dosing head, a research program has been set up, where Vermes microdispensing as a valve manufacturer and TU Berlin/IZM as a research institute are cooperating. TU Berlin is working on material rheology effects and flow models; Vermes is researching valve modifications and material flow path optimization. Core of the research is to find methods that allow a reduction of paste viscosity without leading to irreversible changes in the material, as would be the case when simply applying heat to the paste. As reference process for material dosing, FO-WLP has been chosen, materials selected for the investigations are glob top dam and fill material and liquid molding compound – using both rheological experiments as well as actual material dosing and processing. Apart from temperature, mechanical and ultrasonic stimulation of the material have been evaluated to achieve optimized dosing of high viscous pastes, As a result, a first description of paste behavior during processing is given, being the basis for future work towards homogeneous precision dosing of high viscous pastes for microelectronic applications.
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9

Ziesche, Steffen, and Martin Ihle. "High current conductors in LTCC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000025–29. http://dx.doi.org/10.4071/cicmt-2012-ta14.

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The publication discusses the possibilities of integrating high cross section - metallization structures within fired LTCC substrates. After comparison of different methods for building such metallization structures it focuses on laser ablation to form channel structures, which will be further filled by stencil printing. Furthermore the variants of firing LTCC substrates with high amounts of metallization are discussed and our chosen solution is presented. Finally the processed LTCC substrates are characterized and their ampacities discussed.
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10

Xi, Yue, Tao Wang, Qi Mu, Congcong Huang, Shuming Duan, Xiaochen Ren, and Wenping Hu. "Stencil mask defined doctor blade printing of organic single crystal arrays for high-performance organic field-effect transistors." Materials Chemistry Frontiers 5, no. 7 (2021): 3236–45. http://dx.doi.org/10.1039/d1qm00097g.

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11

Manikam, Vemal Raja, Abdul Razak Khairunisak, and Kuan Yew Cheong. "Effect of Sintering Time on Silver-Aluminium Nanopaste for High Temperature Die Attach Applications." Advanced Materials Research 576 (October 2012): 199–202. http://dx.doi.org/10.4028/www.scientific.net/amr.576.199.

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Nanoscale materials, primarily metallic elements have been proven as suitable solutions for interconnect technology on power semiconductor devices. Nanoscale materials possess high surface energies thus enabling them to be processed at lower temperatures for high temperature applications of more than 500°C. This literature work aims to present a novel silver-aluminium (Ag-Al) nanoalloy die attach paste solution for power semiconductor devices. Ag and Al nanoparticles were pre-mixed into an organic paste system using binders and a surfactant. Viscosity tests concluded that the Ag-Al nanopaste is suitable for mass manufacturing dispensing and screen printing with an average value of 47,800 cps. Thermogravimetric analysis was used to design the sintering profile at 380°C from 10 to 30 minutes. X-ray diffraction analysis detected the formation of Ag2Al and Ag3Al compounds in the post-sintered nanopaste. Scanning electron microscopy and Energy-dispersive X-ray spectroscopy showcased larger grains in the nanopaste microstructure with the passage of sintering time. The electrical conductivity of the Ag-Al nanopaste decreased as the stencil printed paste thickness increased between 25.4-101.6 microns. This was due to the much larger pore formation in the thicker nanopaste layers during sintering and organics burn off.
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12

Bacquian, Bryan Christian S., Frederick Ray I. Gomez, and Edwin M. Graycochea Jr. "Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package." Journal of Engineering Research and Reports, September 17, 2020, 35–38. http://dx.doi.org/10.9734/jerr/2020/v16i417176.

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One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.
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13

Bacquian, B. C., F. R. Gomez, E. Graycochea Jr., and N. Gomez. "Addressing Off-Centered Ball through Solder Paste Material Evaluation." Journal of Engineering Research and Reports, December 11, 2020, 15–18. http://dx.doi.org/10.9734/jerr/2020/v19i317233.

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Stencil printing using solder paste material is one of the challenging processes in semiconductor assembly manufacturing. During evaluation of a semiconductor device, off-centered ball issue was encountered. The study aimed to mitigate the off-centered ball issue at stencil printing process by exploring the effect of different solder paste materials. Both solder paste materials were cured using the same reflow condition. However, solder paste material 1 (S1) resulted to cold solder joints while material 2 (S2) showed cured solder paste characteristic. With S2 material used in stencil printing, the off-centered ball occurrence was eventually eliminated. For future works, the solder paste material and configuration could be used for devices with similar requirement.
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14

Mannan, S. H., N. N. Ekere, I. Ismail, and M. A. Currie. "Flow processes in solder paste during stencil printing for SMT assembly." Journal of Materials Science: Materials in Electronics 6, no. 1 (February 1995). http://dx.doi.org/10.1007/bf00208132.

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15

Jr., Edwin M. Graycochea, Endalicio D. Manalo, Rennier S. Rodriguez, and Frederick Ray I. Gomez. "Glue Voids Reduction on QFN Device through Material and Process Improvement." Journal of Engineering Research and Reports, February 25, 2021, 15–19. http://dx.doi.org/10.9734/jerr/2021/v20i317275.

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The paper is focused on the glue voids reduction on critical semiconductor quad-flat no-leads (QFN) device processed on a stencil printing type of die attach machine. Process optimization through material preparation improvement was done to mitigate the silver lumps of the sintering glue which is a main contributor on the voids occurrence. Eventually, the glue voids were reduced to less than the allowed 5% limit. For future works, the learnings and configuration could be used on devices with similar requirement.
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