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Journal articles on the topic 'Sub-threshold Field Effect Transistors'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.

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The advancement and challenges of field effect transistors are based on multi-gate transistors from the perspective of structure and material. Multi-gate field-effect transistors (Multi-gate FET) have steeper sub-threshold slopes, which can reduce the short channel effect and improve mobility and drive current. A fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are attractive multi-gate structures most compatible with today’s standard machining technologies. As the future moves towards smaller processes, FinFET and GAAFET processes limit the spacing bet

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2

Abdul-Kadir, Firas Natheer, Yasir Hashim, Muhammad Nazmus Shakib, and Faris Hassan Taha. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 780. http://dx.doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3n

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3

Rosaz, Guillaume, Bassem Salem, Nicolas Pauc, et al. "From planar to vertical nanowires field-effect transistors." MRS Proceedings 1439 (2012): 101–7. http://dx.doi.org/10.1557/opl.2012.1422.

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ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106

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4

Montes, E., and U. Schwingenschlögl. "Transport properties of hydrogen passivated silicon nanotubes and silicon nanotube field effect transistors." Journal of Materials Chemistry C 5, no. 6 (2017): 1409–13. http://dx.doi.org/10.1039/c6tc04429h.

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Kim, Janghyuk, Marko J. Tadjer, Michael A. Mastro та Jihyun Kim. "Controlling the threshold voltage of β-Ga2O3 field-effect transistors via remote fluorine plasma treatment". Journal of Materials Chemistry C 7, № 29 (2019): 8855–60. http://dx.doi.org/10.1039/c9tc02468a.

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The threshold voltage of β-Ga<sub>2</sub>O<sub>3</sub> metal–insulator–semiconductor field-effect transistors is controlled via remote fluorine plasma treatment, enabling an enhancement-mode operation under double gate condition.

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6

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this r

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7

Kohmyakov, A., and V. Vyurkov. "Semi-Analytical Models of Field-Effect Transistors with Low-Dimensional Channels." Advanced Materials Research 276 (July 2011): 51–57. http://dx.doi.org/10.4028/www.scientific.net/amr.276.51.

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A semi-analytical model which is applicable to description of ballistic field-effect transistors with low-dimensional channels is proposed. For instance, such transistors can be manufactured on a “silicon-on-insulator” wafer. The model accounts for single-gate and double-gate structures with one-dimensional and two-dimensional channels. It differently describes the regimes of a transistor above threshold and below threshold. The first implies an essential influence of charge inside the channel on a potential distribution; the second supposes a negligible charge inside the channel. Both approac

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NASTAUSHEV, Yu V., T. A. GAVRILOVA, M. M. KACHANOVA, et al. "FIELD EFFECT NANOTRANSISTOR ON ULTRATHIN SILICON-ON-INSULATOR." International Journal of Nanoscience 03, no. 01n02 (2004): 155–60. http://dx.doi.org/10.1142/s0219581x04001936.

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Peculiarities of the fabrication of field effect transistor (FET) at nanoscaled size on ultrathin silicon-on-insulator (SOI) was studied in details. Two types of FET transistor were successfully realized: in-plane-gate FET (IPGFET) with 40 nm minimum channel size and multichannel top-gate MOSFET on silicon-on-insulator. The deep submicron top-gate of Ti/Au embraces each of the conductive oxidized silicon wires placed with 400 nm pitch. The type and concentration of carries in a conductive channel of the ultrathin SOI was controlled by a bottom gate. The fabricated transistors demonstrated high

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9

Tetzner, Kornelius, Kingsley Egbo, Michael Klupsch та ін. "SnO/β-Ga₂O₃ heterojunction field-effect transistors and vertical p–n diodes". Applied Physics Letters 120, № 11 (2022): 112110. http://dx.doi.org/10.1063/5.0083032.

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In this work, we report on the realization of SnO/β-Ga2O3 heterojunction vertical diodes and lateral field-effect transistors for power electronic applications. The p-type semiconductor SnO is grown by plasma-assisted molecular beam epitaxy on n-type (100) β-Ga2O3 with donor concentrations of 3 × 1017 cm−3 for the diode devices and 8.1 × 1017 cm−3 for the field-effect transistors. The deposited films show a predominant SnO (001) phase featuring a hole concentration and a mobility of 7.2 × 1018 cm−3 and 1.5 cm2/V s, respectively. The subsequent electrical characterization of the heterojunction

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10

Islam, Ahmad E., Nicholas P. Sepelak, Kyle J. Liddy та ін. "500 °C operation of β-Ga₂O₃ field-effect transistors". Applied Physics Letters 121, № 24 (2022): 243501. http://dx.doi.org/10.1063/5.0113744.

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We demonstrated 500 °C operation of field-effect transistors made using ultra-wide bandgap semiconductor β-Ga2O3. Metal–semiconductor field-effect transistors were fabricated using epitaxial conductive films grown on an insulating β-Ga2O3 substrate, TiW refractory metal gates, and Si-implanted source/drain contacts. Devices were characterized in DC mode at different temperatures up to 500 °C in vacuum. These variable-temperature measurements showed a reduction in gate modulation of the drain current due to an increase in gate leakage across the gate/semiconductor Schottky barrier. Devices exhi

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11

Lu, Ming-Yen, Shang-Chi Wu, Hsiang-Chen Wang, and Ming-Pei Lu. "Time-evolution of the electrical characteristics of MoS2 field-effect transistors after electron beam irradiation." Physical Chemistry Chemical Physics 20, no. 14 (2018): 9038–44. http://dx.doi.org/10.1039/c8cp00792f.

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12

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMO

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13

Lan, Yann-Wen, Po-Chun Chen, Yun-Yan Lin, et al. "Scalable fabrication of a complementary logic inverter based on MoS2 fin-shaped field effect transistors." Nanoscale Horizons 4, no. 3 (2019): 683–88. http://dx.doi.org/10.1039/c8nh00419f.

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Integration of both n-type and p-type MoS<sub>2</sub> fin-shaped field effect transistors by using a traditional implantation technique for complementary field effect transistor is demonstrated. The complementary MoS<sub>2</sub> inverter with high DC voltage gain of more than 20 is acquired.

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14

Liu, Rui Chao, Hong Liang Zhang, and Run Yuan Li. "Low-Voltage InGaZnO Thin-Film Transistors Gated by SiO₂ Proton Conducting Films." Advanced Materials Research 1033-1034 (October 2014): 1176–81. http://dx.doi.org/10.4028/www.scientific.net/amr.1033-1034.1176.

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Low-voltage (1.5 V) InGaZnO (IGZO) thin-film transistors (TFTs) gated by the SiO2 proton conducting films were self-assembled by a gradient shadow mask in sputtered self-assembled IGZO channel process. The IGZO TFTs have a high-performance with a large current on/off ratio of ≥1.2×106, a low subthreshold swing of ≤120 mV/decade and a high field-effect mobility of 2.2 ~ 6.9 cm2/V·s. Threshold voltage is tuned by various thicknesses of IGZO channel. Both depletion mode and enhancement mode on the same chip is obtained, which will implement a direct-coupled field-effect transistor logic circuit.

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15

Shang, Liwei, Ming Liu, Zhouyu Ji, et al. "Sub-micrometer Organic Field Effect Transistors." ECS Transactions 18, no. 1 (2019): 895–900. http://dx.doi.org/10.1149/1.3096552.

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16

Zhou, Baozeng, Xiaocha Wang, and Wenbo Mi. "Superior electronic structure of two-dimensional 3d transition metal dicarbides for applications in spintronics." Journal of Materials Chemistry C 6, no. 15 (2018): 4290–99. http://dx.doi.org/10.1039/c7tc05383e.

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The potential application of spin transport in a CrC<sub>2</sub>-based field-effect transistor on a flexible substrate. It is possible to realize electrical control on the SOC-induced insulating state and on carriers’ spin orientation by applying a vertical electric field, which can simulate the back-gate potential (V<sub>G</sub>) in field-effect transistors.

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17

Pelella, Aniello, Alessandro Grillo, Enver Faella, Filippo Giubileo, Francesca Urban, and Antonio Di Bartolomeo. "Molybdenum Disulfide Field Effect Transistors under Electron Beam Irradiation and External Electric Fields." Materials Proceedings 4, no. 1 (2020): 25. http://dx.doi.org/10.3390/iocn2020-07807.

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In this work, monolayer molybdenum disulfide (MoS2) nanosheets, obtained via chemical vapor deposition onto SiO2/Si substrates, are exploited to fabricate field-effect transistors with n-type conduction, high on/off ratio, steep subthreshold slope and good mobility. We study their electric characteristics from 10−6 Torr to atmospheric air pressure. We show that the threshold voltage of the transistor increases with the growing pressure. Moreover, Schottky metal contacts in monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) are investigated under electron beam irradiation con

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18

Lee, Sora, Xiaotian Zhang, Thomas McKnight, et al. "Low-temperature processed beta-phase In₂Se₃ ferroelectric semiconductor thin film transistors." 2D Materials 9, no. 2 (2022): 025023. http://dx.doi.org/10.1088/2053-1583/ac5b17.

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Abstract As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In2Se3, at temperature as low as 400 °C. Top gate n-channel In2Se3 thin film transistors were fabricated with field-eff

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19

Bhadra, Debabrata. "USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE." International Journal of Advanced Research 9, no. 11 (2021): 1095–101. http://dx.doi.org/10.21474/ijar01/13846.

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Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (<1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (Îµr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have bee

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20

Flicker, Jack, David Hughart, Robert Kaplar, Stanley Atcitty, and Matthew Marinella. "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000228–34. http://dx.doi.org/10.4071/hitec-wp16.

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1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV afte

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21

ISOBE, Y., K. HARA, D. NAVARRO, Y. TAKEDA, T. EZAKI, and M. MIURA-MATTAUSCH. "Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition." IEICE Transactions on Electronics E90-C, no. 4 (2007): 885–94. http://dx.doi.org/10.1093/ietele/e90-c.4.885.

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22

Nazir, Ghazanfar, Muhammad Farooq Khan, Volodymyr M. Iermolenko, and Jonghwa Eom. "Two- and four-probe field-effect and Hall mobilities in transition metal dichalcogenide field-effect transistors." RSC Advances 6, no. 65 (2016): 60787–93. http://dx.doi.org/10.1039/c6ra14638d.

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23

Zheng, R., M. Y. Yan, C. Li, et al. "Pyroelectric effect mediated infrared photoresponse in Bi₂Te₃/Pb(Mg_1/3Nb_2/3)O₃–PbTiO₃ optothermal ferroelectric field-effect transistors." Nanoscale 13, no. 48 (2021): 20657–62. http://dx.doi.org/10.1039/d1nr06863f.

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24

Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production.

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25

Yavorskiy, D., K. Karpierz, P. Kopyt, M. Grynberg, and J. Łusakowski. "Sub-Terahertz Emission from Field-Effect Transistors." Acta Physica Polonica A 132, no. 2 (2017): 335–37. http://dx.doi.org/10.12693/aphyspola.132.335.

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26

Kohlert, Dieter. "The sub-threshold behaviour of the MOS field-effect transistor." European Journal of Physics 19, no. 2 (1998): 125–31. http://dx.doi.org/10.1088/0143-0807/19/2/004.

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27

Lai, Shen, Sung Kyu Jang, Jeong Ho Cho, and Sungjoo Lee. "Organic field-effect transistors integrated with Ti2CTx electrodes." Nanoscale 10, no. 11 (2018): 5191–97. http://dx.doi.org/10.1039/c7nr08677f.

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Pentacene organic field-effect transistors integrated with MXene (Ti<sub>2</sub>CT<sub>x</sub>) electrodes are studied. Superior device performance with high mobility, high on/off ratio, and low contact resistance is achieved.

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28

Goswami, Yogesh, Pranav Asthana, Shibir Basak, and Bahniman Ghosh. "Junctionless Tunnel Field Effect Transistor with Nonuniform Doping." International Journal of Nanoscience 14, no. 03 (2015): 1450025. http://dx.doi.org/10.1142/s0219581x14500252.

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In this paper, the dc performance of a double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been further enhanced with the implementation of double sided nonuniform Gaussian doping in the channel. The device has been simulated for different channel materials such as Si and various III-V compounds like Gallium Arsenide, Aluminium Indium Arsenide and Aluminium Indium Antimonide. It is shown that Gaussian doped channel Junctionless Tunnel Field Effect Transistor purveys higher ION/IOFF ratio, lower threshold voltage and sub-threshold slope and also offers better short channel p

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29

Nazari, Atefeh, Rahim Faez, and Hassan Shamloo. "ImprovingION/IOFFand sub-threshold swing in graphene nanoribbon field-effect transistors using single vacancy defects." Superlattices and Microstructures 86 (October 2015): 483–92. http://dx.doi.org/10.1016/j.spmi.2015.08.018.

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30

Ryu, Min-Yeul, Ho-Kyun Jang, Kook Jin Lee, et al. "Triethanolamine doped multilayer MoS2 field effect transistors." Physical Chemistry Chemical Physics 19, no. 20 (2017): 13133–39. http://dx.doi.org/10.1039/c7cp00589j.

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Hernandez-Arriaga, Heber, Jaidah Mohan, Yong Chan Jung, et al. "(Digital Presentation) Evaluation of the O₃ and H₂o Oxidants in Downscaling Eot of Ferroelectric Hf_0.5Zr_0.5O₂ on Silicon." ECS Meeting Abstracts MA2022-01, no. 19 (2022): 1074. http://dx.doi.org/10.1149/ma2022-01191074mtgabs.

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Integrating the HfZrO2 (HZO) on silicon have attracted the attention of researches in the development of ferroelectric field effect transistor (FeFETs) for implementation in high-density memories and neuromorphic devices[1][2]. In this work, it has been investigated the thickness scalability of HZO thin films and the reduction of the equivalent-oxide-thickness (EOT) on Silicon using [(CH3)2N]4Hf and [(CH3)2N]4Zr as precursor and H2O and O3 as oxidants by means of atomic layer deposition. A TiN/HZO/Si structure was fabricated where the Si substrate has been prepared with a HF-last clean to remo

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Hasan, Ghanim Thiab, Ali Hlal Mutlaq, Kamil Jadu Ali, and Mohammed Ayad Saad. "Modeling of magnetic sensitivity of the metal-oxide-semiconductor field-effect transistor with double gates." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 2632. http://dx.doi.org/10.11591/ijece.v13i3.pp2632-2639.

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<span lang="EN-US">In this paper, we investigated the effect of magnetic field on the carrier transport phenomenon in metal-oxide-semiconductor field-effect transistor (MOSFET) with double gates by examining the behavior of the semiconductor under the Lorentz force and a constant magnetic field. Various behaviors within the channel have been simulated including the potential distribution, conduction and valence bands, total current density, total charge density and the magnetic field. The results obtained indicate that this modulation affects the electrical characteristics of the device

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Ghazali, Nor Azlin, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar Jalaludin Khan, and Harold Chong. "Temperature Dependence of Electrical Characteristics of ZnO Nanowire Field-Effect Transistors with AZO and Aluminium Source/Drain Contact." Key Engineering Materials 947 (May 31, 2023): 33–38. http://dx.doi.org/10.4028/p-9v2hoh.

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In this study, ZnO nanowire field-effect transistor (FET) with an aluminium-doped ZnO (AZO) and an aluminium (Al) dual layer source and drain contact are fabricated and temperature dependent characteristics in the range of 200 – 300 K are analyzed through experimental measurements. The effect of temperature on threshold voltage, subthreshold slope, transconductance, and field effect mobility are analysed. The transfer curve exhibits a parallel shift toward a negative gate voltage direction with a negative shift of the threshold voltage, an increase in the subthreshold slope, and a field-effect

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Möller, Peter, Mike Andersson, Anita Lloyd Spetz, Jarkko Puustinen, Jyrki Lappalainen, and Jens Eriksson. "NO_x Sensing with SiC Field Effect Transistors." Materials Science Forum 858 (May 2016): 993–96. http://dx.doi.org/10.4028/www.scientific.net/msf.858.993.

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In this paper, we investigated the nitrogen oxides (NO, NO2) detection capability of strontium titanate (SrTiO3) when used as sensing layer on gas sensitive silicon carbide field effect transistors (SiC-FETs). Sensitivity, selectivity and response times for NO, NO2, and NH3 were characterized, to determine the possibility for diesel exhaust after treatment control applications. It was found that NOx can be detected down to single digit ppm levels at sensor temperatures in the 550°C - 600°C range. In addition, the results indicate that it is possible to suppress sensitivity to ammonia by select

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Kavala, A. K., and A. K. Mukherjee. "Sub-threshold-like charge transport in organic field effect transistor: A study on effective channel thickness." Modern Physics Letters B 29, no. 28 (2015): 1550172. http://dx.doi.org/10.1142/s0217984915501729.

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A short channel organic field effect transistors (OFET) based on Pentacene, having channel length in the range of sub-micrometer, has been numerically modelled for low values of drain voltage. The output characteristics show a nonlinear concave increase of drain current for all values of gate voltages. This anomalous current-voltage behavior, which resembles sub-threshold characteristics of silicon FETs, shows a good match with earlier experimental reports on OFET at low drain voltages. The sub-threshold-like characteristics has been interpreted in light of thermionic-emission model because of

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Saidov, Kamoladdin, Khakimjan Butanov, Jamoliddin Razzokov, Shavkat Mamatkulov, Dong Fang, and Olim Ruzimuradov. "Non-volatile phototransistor based on two dimensional MoTe₂ nanostructures." E3S Web of Conferences 401 (2023): 05093. http://dx.doi.org/10.1051/e3sconf/202340105093.

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We fabricate field-effect transistors (FETs) from low-layer molybdenum ditelluride (MoTe2) in the nanometer range and study its optoelectronic properties. In particular, we investigate the mechanisms of photocurrent generation in MoTe2 FETs using gate and bias-dependent photocurrent measurements. The results obtained show the photocurrent effects and signals generated in the MoTe2-electrode junctions, which identify the effect of amplifying the photoconductor in the off and on modes. This is different from those conventional MoTe2 FETs, which exhibited a continuous increase in photocurrent wit

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Tadjer, Marko J., Karl D. Hobart, Michael A. Mastro, et al. "Effect of Temperature and Al Concentration on the Electrical Performance of GaN and Al_0.2Ga_0.8N Accumulation-Mode FET Devices." Materials Science Forum 645-648 (April 2010): 1215–18. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1215.

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Field-effect transistors were fabricated on GaN and Al0.2Ga0.8N epitaxial layers grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates. The threshold voltage VTH was higher when AlGaN was used as an active layer. VTH also increased with temperature due to the increased positive polarization charge at the GaN/AlN buffer/sapphire interfaces. Drain current increased at high temperatures even with more positive threshold voltage, which makes GaN-based FET devices attractive for high temperature operation.

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XUAN, G., J. KOLODZEY, V. KAPOOR, and G. GONYE. "ELECTRICAL EFFECTS OF DNA MOLECULES ON SILICON FIELD EFFECT TRANSISTOR." International Journal of High Speed Electronics and Systems 14, no. 03 (2004): 684–89. http://dx.doi.org/10.1142/s0129156404002673.

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Much research has been devoted to the field of DNA detection for biotechnology and medical diagnostics. Conventionally, this has involved lab-scale large instruments such as fluorescent microscope, with DNA binding and tagging. Recently, however, the possibility of label-free, rapid, sensitive and miniaturized DNA detection electronically has attracted increasing interest in the field. To investigate the feasibility of DNA detection by the semiconductor field effect without tagging or binding agents, we studied the effects of DNA molecules directly on the gate oxide of field effect transistors

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SIMIN, G., M. ASIF KHAN, M. S. SHUR, and R. GASKA. "INSULATED GATE III-N HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS." International Journal of High Speed Electronics and Systems 14, no. 01 (2004): 197–224. http://dx.doi.org/10.1142/s0129156404002302.

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Unique materials properties of GaN -based semiconductors that make them promising for high-power high-temperature applications are high electron mobility and saturation velocity, high sheet carrier concentration at heterojunction interfaces, high breakdown field, and low thermal impedance (when grown over SiC or bulk AlN substrates). The chemical inertness of nitrides is another key property. An AlGaN / GaN Heterostructure Field Effect Transistor (HFET) has been a topic of intensive investigations since the first report in 1991 [1]. Several groups demonstrated high power operation of AlGaN / G

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Kubozono, Yoshihiro, Keita Hyodo, Hiroki Mori, Shino Hamao, Hidenori Goto, and Yasushi Nishihara. "Transistor application of new picene-type molecules, 2,9-dialkylated phenanthro[1,2-b:8,7-b′]dithiophenes." Journal of Materials Chemistry C 3, no. 10 (2015): 2413–21. http://dx.doi.org/10.1039/c4tc02413c.

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Field-effect transistors have been fabricated that use thin films of 2,9-dialkylated phenanthro[1,2-b:8,7-b′]dithiophenes (C<sub>n</sub>-PDTs), with the transistor based on a thin film of C<sub>12</sub>-PDT showing aμas high as ∼2 cm<sup>2</sup>V<sup>−1</sup>s<sup>−1</sup>, which is promising for future practical electronics.

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Suchet, P., M. Duseaux, J. Maluenda, and G. M. Martin. "Effects of dislocations on threshold voltage of GaAs field‐effect transistors." Journal of Applied Physics 62, no. 3 (1987): 1097–101. http://dx.doi.org/10.1063/1.339715.

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Kessi, Mohamed, and Arezki Benfdila. "Magnetic sensitivity modeling of dual gate MOS transistor." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 2 (2021): 1238. http://dx.doi.org/10.11591/ijeecs.v24.i2.pp1238-1248.

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In this paper, the magnetic field effect on the carrier transport phenomenon in the double gate metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. This is done by exploring the Lorentz force and the behavior of a semiconductor subjected to a constant magnetic field. The magnetic field modulates the electrons position and density as well as the potential distribution in the case of silicon tunnel tunneling field-effects (FETs). This modulation impacts the device electrical characteristics such as ON current (I<sub>ON</sub>), subthreshold leakage curren

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KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal

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Zhong, Kai, Yuan Liu, Shu-Ting Cai, and Xiao-Ming Xiong. "Temperature dependence of conduction and low frequency noise characteristics in hydrogenated amorphous silicon thin film transistors." Modern Physics Letters B 33, no. 02 (2019): 1950009. http://dx.doi.org/10.1142/s021798491950009x.

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The transfer and low frequency noise characteristics of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) were measured in the temperature range of 230–430 K. The variation of threshold voltage, field effect mobility and sub-threshold swing with increasing temperatures were then extracted and analyzed. Moreover, the shifts of low frequency noise in the a-Si:H TFT under various temperatures are reported for the first time. The variation of flatband voltage noise power spectral density with temperature is also calculated and discussed.

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Khandelwal, Vishal, Saravanan Yuvaraja, Glen Isaac Maciel García та ін. "Monolithic β-Ga₂O₃ NMOS IC based on heteroepitaxial E-mode MOSFETs". Applied Physics Letters 122, № 14 (2023): 143502. http://dx.doi.org/10.1063/5.0143315.

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In this Letter, we report on a monolithically integrated β-Ga2O3 NMOS inverter integrated circuit (IC) based on heteroepitaxial enhancement mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistors on low-cost sapphire substrates. A gate recess technique was employed to deplete the channel for E-mode operation. The E-mode devices showed an on-off ratio of ∼105 with a threshold voltage of 3 V. In comparison, control devices without the gate recess exhibited a depletion mode (D-mode) with a threshold voltage of [Formula: see text]3.8 V. Furthermore, depletion-load NMOS inverter IC

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Zhou, Xuanze, Yongjian Ma, Guangwei Xu та ін. "Enhancement-mode β-Ga₂O₃ U-shaped gate trench vertical MOSFET realized by oxygen annealing". Applied Physics Letters 121, № 22 (2022): 223501. http://dx.doi.org/10.1063/5.0130292.

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Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of

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Han, Sha, Cai-Juan Xia, Min Li, et al. "First-principles study on electronic states of In₂Se₃/Au heterostructure controlled by strain engineering." RSC Advances 13, no. 17 (2023): 11385–92. http://dx.doi.org/10.1039/d3ra00134b.

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Yurasik G. A., Kulishov A. A., Givargizov M. E., and Postnikov V. A. "Dedicated to the memory of V.D. Aleksandrov Effect of annealing in an inert atmosphere on the electrical properties of crystalline pentacene films." Technical Physics Letters 48, no. 15 (2022): 30. http://dx.doi.org/10.21883/tpl.2022.15.55278.18983.

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The results of a study of the effect of annealing at 150^oC in an inert atmosphere (Ar + 5% H2) on the electrical properties of organic field-effect transistors based on pentacene are presented. Crystalline pentacene films with a thickness of 95±5 nm were obtained using thermal vacuum deposition. The transfer and output characteristics of field-effect transistors before and after annealing for 15 hours are investigated. It was found that as a result of heat treatment, the hole mobility in the saturation regime increased by an average of 30%, and the threshold voltage decreased approximately tw

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Kevin, Punarja, Mohammad Azad Malik, Paul O'Brien, et al. "Nanoparticles of Cu2ZnSnS4as performance enhancing additives for organic field-effect transistors." Journal of Materials Chemistry C 4, no. 22 (2016): 5109–15. http://dx.doi.org/10.1039/c6tc01650b.

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Narasimhamurthy, K. C., and Roy Paily Palathinkal. "Performance Comparison of Interdigitated Thin-Film Field-Effect Transistors Using Different Purity Semiconducting Carbon Nanotubes." Advanced Materials Research 181-182 (January 2011): 343–48. http://dx.doi.org/10.4028/www.scientific.net/amr.181-182.343.

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In this paper, we present the fabrication and characterization of semiconducting carbon nanotube thin-film field-effect transistors (SN-TFTs). High-k dielectric material, hafnium-oxide (HfOX) is used as the gate-oxide of the device. A Thin-film of semi-conducting single walled carbon nanotube (SWCNT) is deposited on the amino-silane modified HfOX surface. Two types of SN-TFTs with interdigitated source and drain contacts are fabricated using 90% and 95% purity of semiconducting SWCNTs (s-SWCNT), have exhibited a p-type behavior with a distinct linear and saturation region of operation. For 20

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