Relevant bibliographies by topics / Successive approximation

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Successive approximation'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 June 2025

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Journal articles on the topic "Successive approximation"

1

Kovacevic, J., R. J. Safranek, and E. M. Yeh. "Deinterlacing by successive approximation." IEEE Transactions on Image Processing 6, no. 2 (1997): 339–44. http://dx.doi.org/10.1109/83.551707.

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Xin Li. "Demosaicing by successive approximation." IEEE Transactions on Image Processing 14, no. 3 (2005): 370–79. http://dx.doi.org/10.1109/tip.2004.840683.

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3

Yamada, Yoshio, and Saburo Tazaki. "Successive approximation vector quantization." Electronics and Communications in Japan (Part I: Communications) 69, no. 9 (1986): 11–19. http://dx.doi.org/10.1002/ecja.4410690902.

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Schoenberg, Michael A., and Maarten V. de Hoop. "Approximate dispersion relations for qP-qSV-waves in transversely isotropic media." GEOPHYSICS 65, no. 3 (2000): 919–33. http://dx.doi.org/10.1190/1.1444788.

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To decouple qP and qSV sheets of the slowness surface of a transversely isotropic (TI) medium, a sequence of rational approximations to the solution of the dispersion relation of a TI medium is introduced. Originally conceived to allow isotropic P-wave processing schemes to be generalized to encompass the case of qP-waves in transverse isotropy, the sequence of approximations was found to be applicable to qSV-wave processing as well, although a higher order of approximation is necessary for qSV-waves than for qP-waves to yield the same accuracy. The zeroth‐order approximation, about which all other approximations are taken, is that of elliptical TI, which contains the correct values of slowness and its derivative along and perpendicular to the medium’s axis of symmetry. Successive orders of approximation yield the correct values of successive orders of derivatives in these directions, thereby forcing the approximation into increasingly better fit at the intervening oblique angles. Practically, the first‐order approximation for qP-wave propagation and the second‐order approximation for qSV-wave propagation yield sufficiently accurate results for the typical transverse isotropy found in geological settings. After only slight modification to existing programs, the rational approximation allows for ray tracing, (f-k) domain migration, and split‐step Fourier migration in TI media—with little more difficulty than that encountered presently with such algorithms in isotropic media.
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Chowdary, I. Hitha, and G. Anitha Chowdary. "Power Efficient Successive Approximation Registers." IOSR journal of VLSI and Signal Processing 4, no. 3 (2014): 10–16. http://dx.doi.org/10.9790/4200-04331016.

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Alur, R., A. Itai, R. P. Kurshan, and M. Yannakakis. "Timing Verification by Successive Approximation." Information and Computation 118, no. 1 (1995): 142–57. http://dx.doi.org/10.1006/inco.1995.1059.

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Noeiaghdam, S., D. N. Sidorov, and A. I. Dreglea. "Fuzzy Volterra Integral Equations with Piecewise Continuous Kernels: Theory and Numerical Solution." Bulletin of Irkutsk State University. Series Mathematics 50 (2024): 36–50. https://doi.org/10.26516/1997-7670.2024.50.36.

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This research focuses on addressing both linear and nonlinear fuzzy Volterra integral equations that feature piecewise continuous kernels. The problem is tackled using the method of successive approximations. The study discusses the existence and uniqueness of solutions for these fuzzy Volterra integral equations with piecewise kernels. Numerical results are obtained by applying the successive approximations method to examples for both linear and nonlinear scenarios. Error analysis graphs are plotted to illustrate the accuracy of the method. Furthermore, a comparative analysis is presented through graphs of approximate solutions for different fuzzy parameter values. To highlight the effectiveness and significance of the successive approximations method, a comparison is made with the traditional homotopy analysis technique. The results indicate that the successive approximation method outperforms the homotopy analysis method in terms of accuracy and effectiveness.
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Fehér, Áron, Lorinc Márton, and Mihály Pituk. "Approximation of a Linear Autonomous Differential Equation with Small Delay." Symmetry 11, no. 10 (2019): 1299. http://dx.doi.org/10.3390/sym11101299.

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A linear autonomous differential equation with small delay is considered in this paper. It is shown that under a smallness condition the delay differential equation is asymptotically equivalent to a linear ordinary differential equation with constant coefficients. The coefficient matrix of the ordinary differential equation is a solution of an associated matrix equation and it can be written as a limit of a sequence of matrices obtained by successive approximations. The eigenvalues of the approximating matrices converge exponentially to the dominant characteristic roots of the delay differential equation and an explicit estimate for the approximation error is given.
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Petrus, Setyo Prabowo, and Mungkasi Sudi. "A multistage successive approximation method for Riccati differential equations." Bulletin of Electrical Engineering and Informatics 10, no. 3 (2021): pp. 1589~1597. https://doi.org/10.11591/eei.v10i3.3043.

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Riccati differential equations have played important roles in the theory and practice of control systems engineering. Our goal in this paper is to propose a new multistage successive approximation method for solving Riccati differential equations. The multistage successive approximation method is derived from an existing piecewise variational iteration method for solving Riccati differential equations. The multistage successive approximation method is simpler in terms of computing implementation in comparison with the existing piecewise variational iteration method. Computational tests show that the order of accuracy of the multistage successive approximation method can be made higher by simply taking more number of successive iterations in the multistage evolution. Furthermore, taking small size of each subinterval and taking large number of iterations in the multistage evolution lead that our proposed method produces small error and becomes high order accurate.
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C. Mayer, Daniel. "Successive Approximation of p-Class Towers." Advances in Pure Mathematics 07, no. 12 (2017): 660–85. http://dx.doi.org/10.4236/apm.2017.712041.

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Dissertations / Theses on the topic "Successive approximation"

1

MURATORE, DANTE GABRIEL. "A Study of Successive Approximation Register ADC Architectures." Doctoral thesis, Università degli studi di Pavia, 2017. http://hdl.handle.net/11571/1203278.

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In the era of all-mobile devices and the Internet of Things, power efficient solutions are required by new applications. Wearables and battery supplied systems are in high demand, asking designers to come up with new ideas for ultra low- power high-performances data converters. Among all the possible architectures, SAR ADCs stand out because of their high efficiency. Besides, the quasi all-digital nature of this topology greatly adapts to the technological scaling and the simple structure better suits to more complex system-level designs. Apart from being an excellent choice as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited for hybrid solutions that further pushes away the limits of other types of converters, such pipeline or oversampled ADCs. The goal of this thesis is to study the versatility and adaptability of the SAR algorithm for different applications. In order to do so, 3 different projects carried out during the Ph.D. activity are presented. These are 1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS. 2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring. 3. A 200 μW 12-b 8 MS/s SAR ADC for Ultrasound Systems. The presented ADCs highly differ from the performances point of view, but they all share the fact that they use the SAR algorithm to meet the requirements of the given application. The first two projects were fabricated and tested, while the third has been simulated at post-layout level. Project # 1 is a high-speed single-channel ADC for wireline communications. The architecture uses a sub-ranging approach with a flash converter and a multi-bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements of the first stages, and a shift-register free logic is implemented. Thresholds in the multi-bit per cycle SAR converter are produced by a special preamplifier that uses an interpolation-like technique. A novel comparator speeds up the overall operation of the converter, by using a built-in preamplifier that initially unbalances the output of the latch. Project # 2 implements an extended-range ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC for the coarse conversion of the battery cell voltages, and a single SAR ADC for the fine conversion. The high-voltage section is limited to 8 switches and a high- voltage capacitor reducing the cost of the converter. The remaining part of the circuit operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-simultaneous sampling of the battery cells, and the single fine converter limits the mismatch between channels. Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems. The ADC is intended to be used in the acquisition channel of a wearable tran- scranial doppler ultrasound system (TCD) to measure cerebral blood flow velocity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so area and power constraints are the most stringent specifications. An hybrid resistive- capacitive structure is used to reduce the area of the DAC, while an asynchronous logic optimises the timing of the converter and the power consumption. Chapter 1 introduces to the reader the most common data converter architec- tures and provides a discussion on the evolution of data converter during the past years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chap- ters 2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while con- clusions are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to provide a more direct access to the reader.<br>In the era of all-mobile devices and the Internet of Things, power efficient solutions are required by new applications. Wearables and battery supplied systems are in high demand, asking designers to come up with new ideas for ultra low- power high-performances data converters. Among all the possible architectures, SAR ADCs stand out because of their high efficiency. Besides, the quasi all-digital nature of this topology greatly adapts to the technological scaling and the simple structure better suits to more complex system-level designs. Apart from being an excellent choice as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited for hybrid solutions that further pushes away the limits of other types of converters, such pipeline or oversampled ADCs. The goal of this thesis is to study the versatility and adaptability of the SAR algorithm for different applications. In order to do so, 3 different projects carried out during the Ph.D. activity are presented. These are 1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS. 2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring. 3. A 200 μW 12-b 8 MS/s SAR ADC for Ultrasound Systems. The presented ADCs highly differ from the performances point of view, but they all share the fact that they use the SAR algorithm to meet the requirements of the given application. The first two projects were fabricated and tested, while the third has been simulated at post-layout level. Project # 1 is a high-speed single-channel ADC for wireline communications. The architecture uses a sub-ranging approach with a flash converter and a multi-bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements of the first stages, and a shift-register free logic is implemented. Thresholds in the multi-bit per cycle SAR converter are produced by a special preamplifier that uses an interpolation-like technique. A novel comparator speeds up the overall operation of the converter, by using a built-in preamplifier that initially unbalances the output of the latch. Project # 2 implements an extended-range ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC for the coarse conversion of the battery cell voltages, and a single SAR ADC for the fine conversion. The high-voltage section is limited to 8 switches and a high- voltage capacitor reducing the cost of the converter. The remaining part of the circuit operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-simultaneous sampling of the battery cells, and the single fine converter limits the mismatch between channels. Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems. The ADC is intended to be used in the acquisition channel of a wearable tran- scranial doppler ultrasound system (TCD) to measure cerebral blood flow velocity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so area and power constraints are the most stringent specifications. An hybrid resistive- capacitive structure is used to reduce the area of the DAC, while an asynchronous logic optimises the timing of the converter and the power consumption. Chapter 1 introduces to the reader the most common data converter architec- tures and provides a discussion on the evolution of data converter during the past years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chap- ters 2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while con- clusions are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to provide a more direct access to the reader.
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Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.

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Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.
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Radhakrishnan, Ram Harshvardhan. "Accelerated Successive Approximation Technique for Analog to Digital Converter Design." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1630.

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This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
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Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

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<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.</p>
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Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.

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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Yang, Kun. "A 16 Bit 500KSps low power successive approximation analog to digital converter." Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Thesis/Fall2009/k_yang_111809.pdf.

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Thesis (M.S. in electrical engineering)--Washington State University, December 2009.<br>Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
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Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.

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In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
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Guo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.

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An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. A proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215×215 μm². Due to an unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 μW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.
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Barton, Patrick Randal. "A synthesis program for CMOS successive approximation A/D and D/A converters." Thesis, Georgia Institute of Technology, 1986. http://hdl.handle.net/1853/15347.

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Books on the topic "Successive approximation"

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Hung, Chung-Chih, and Shih-Hsing Wang. Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-to-Digital Converter for Biomedical Applications. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-88845-9.

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Yang, Ada. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2015.

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Yang, Ada. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Ferrigan, Kelly. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2020.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Hung, Chung-Chih, and Shih-Hsing Wang. Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-To-Digital Converter for Biomedical Applications. Springer International Publishing AG, 2021.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2015.

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Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-To-Digital Converter for Biomedical Applications. Springer International Publishing AG, 2022.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) FRM. Microchip Technology Incorporated, 2016.

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Book chapters on the topic "Successive approximation"

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Horst, Reiner, and Hoang Tuy. "Successive Approximation Methods." In Global Optimization. Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-662-02598-7_6.

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Pelgrom, Marcel J. M. "Successive Approximation Conversion." In Analog-to-Digital Conversion. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-90808-9_16.

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Horst, Reiner, and Hoang Tuy. "Successive Approximation Methods." In Global Optimization. Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-662-02947-3_6.

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Horst, Reiner, and Hoang Tuy. "Successive Approximation Methods." In Global Optimization. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/978-3-662-03199-5_6.

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Schmid, Helmut. "Parsing by Successive Approximation." In Text, Speech and Language Technology. Springer Netherlands, 2000. http://dx.doi.org/10.1007/978-94-015-9470-7_13.

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Ohnhäuser, Frank. "ADCs Based on Successive Approximation." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_2.

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Alur, R., A. Itai, R. Kurshan, and M. Yannakakis. "Timing verification by successive approximation." In Computer Aided Verification. Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/3-540-56496-9_12.

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Fussell, Donald, and Ramakrishna Thurimella. "Successive approximation in parallel graph algorithms." In STACS 89. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/bfb0028985.

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Carraro, Thomas, and Vladislav Olkhovskiy. "Successive Approximation of Nonlinear Confidence Regions (SANCR)." In IFIP Advances in Information and Communication Technology. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-55795-3_16.

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CĂtinaş, Emil. "Sufficient Convergence Conditions for Certain Accelerated Successive Approximations." In Trends and Applications in Constructive Approximation. Birkhäuser Basel, 2005. http://dx.doi.org/10.1007/3-7643-7356-3_6.

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Conference papers on the topic "Successive approximation"

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Idrees, Basil M., Lavish Arora, and Ketan Rajawat. "Non-Convex Constrained Stochastic Successive Convex Approximation." In 2024 IEEE 34th International Workshop on Machine Learning for Signal Processing (MLSP). IEEE, 2024. http://dx.doi.org/10.1109/mlsp58920.2024.10734740.

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Saboksayr, Seyed Saman, Gonzalo Mateos, and Mariano Tepper. "Block Successive Convex Approximation for Concomitant Linear DAG Estimation." In 2024 IEEE 13th Sensor Array and Multichannel Signal Processing Workshop (SAM). IEEE, 2024. http://dx.doi.org/10.1109/sam60225.2024.10636401.

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Baig, Muhammad Samee, and Aziza I. Hussein. "Cognitive Radio Receiver Design Employing Pipeline Successive Approximation ADC." In 2025 22nd International Learning and Technology Conference (L&T). IEEE, 2025. https://doi.org/10.1109/lt64002.2025.10940955.

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Rocchini, Gabriele. "Analysis of Polarization Curves by the Successive Approximation Method." In CORROSION 1991. NACE International, 1991. https://doi.org/10.5006/c1991-91159.

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Abstract Some theoretical considerations are discussed concerning the geometric shape of polarization curves and the width of the polarization potential intervals over which the asymptotic Tafel law is valid. These mathematical arguments are useful to introduce the treatment of the numerical method of successive approximations, which allows determination of the three electrochemical parameters Ic, Ba and Bc characterizing the kinetics of a corrosion process under the activation energy control. In particular, the technique proposed is shown to be readily obtainable from the analytic expressions of the current-voltage characteristic in the anodic and cathodic regions. The problem of the convergence of the numerical sequences generated by the iterative process is then tackled and it is shown that under suitable hypotheses the problem always has a physical solution, provided the information contained in the experimental polarization curves is not altered by casual or systematic errors and the true kinetics of the corrosion process do not differ markedly from the ideal behaviour. Lastly, two experimental applications are discussed concerning the systems: ARMCO iron + H2SO4 at different pH and 25 °C, and ARMCO iron + 1m HCl at temperatures between 25 °C and 65 °C. The results obtained are very satisfactory. In the first case, the goodness of the method of successive approximations is confirmed by the observation that the information provided by this analysis is practically analogous to the indications obtained by NOLI method which is a well-established numerical technique. In the second case, by using the true corrosion rate as a reference parameter it is possible to describe the actual behaviour of the corrosion process correctly.
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Mitrovic, Jovan, Yiqiao Zhang, and Zeljko Ignjatovic. "Predictive Successive Approximation ADC." In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018. http://dx.doi.org/10.1109/iscas.2018.8351230.

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Dutra, Alessandro J. S., Lisandro Lovisolo, Eduardo A. B. da Silva, and Paulo S. R. Diniz. "Successive approximation FIR filter design." In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5937523.

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Panhuber, Reinhard, and Ludger Prunte. "Complex Successive Concave Sparsity Approximation." In 2020 21st International Radar Symposium (IRS). IEEE, 2020. http://dx.doi.org/10.23919/irs48640.2020.9253770.

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Szyduczynski, Jakub, Dariusz Koscielnik, Konrad Jurasz, and Marek Miskowicz. "Successive Approximation Time-to-Digital Converters." In 2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP). IEEE, 2020. http://dx.doi.org/10.1109/ebccsp51266.2020.9291366.

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Yip, T. Gary, and Elizabeth B. Nadworny. "A Successive Approximation ADC Simulation Project." In ASME 1992 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1992. http://dx.doi.org/10.1115/cie1992-0067.

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Abstract This paper describes a three week long project designed for first year graduate students in mechanical engineering taking a course in Modern Instrumentation. The project entails constructing a successive approximation analog-to-digital converter without a controller, developing a control sequence, and implementing it to produce a digital representation of an analog input voltage. The course is made up of a series of laboratory activities that start with the fundamentals of equipment control and data acquisition, then increase in difficulty by requiring students to develop systems and control sequences on their own. The project teaches computer based data acquisition skills, the fundamental logic of a successive approximation ADC, and provides hands on experience using digital signals to control a system.
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Kiani, Shahrzad, and Stark C. Draper. "Successive Approximation for Coded Matrix Multiplication." In 2022 IEEE International Symposium on Information Theory (ISIT). IEEE, 2022. http://dx.doi.org/10.1109/isit50566.2022.9834389.

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Reports on the topic "Successive approximation"

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Young, Michael J. Successively Approximating Human Performance. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada272186.

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Lane, Scott. An investigation of the consistency of judgments regarding successive approximations of /r/. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.2848.

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González, Pablo, Andrés E. Fernández-Vergara, Gemma Rojas, and Luis Vilugrón. The Political Economy of Regulation: Chile’s Educational Reforms since the Return of Democracy. Research on Improving Systems of Education (RISE), 2023. http://dx.doi.org/10.35489/bsg-rise-2023/pe12.

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This paper analyses three key political economy issues in Chile after the return of democracy in 1990: the prioritisation of learning; teacher's career and evaluation (intimately linked in the case of Chile); and quality assurance. The first issue is divided in turn in two subtopics: the identification of learning as the key educational policy objective and whether educational quality is made a priority by the government. The findings suggest a longstanding and sustained effort of successive approximations to better solutions that address the technical limitations and political restrictions that shaped reforms and policies, in a complicated path dependent process that will be analysed throughout this paper. All three issues are addressed in 26 interviews with key actors, the relevant legislation histories' as well as a national database of written media in the period 2007-2018, with special focus in the time span of legislative discussion of relevant initiatives.
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