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Dissertations / Theses on the topic 'Successive Approximation Register ADC'

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Published: 4 June 2021

Last updated: 16 February 2022

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1

Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.

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Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, whic

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2

Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis p

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3

Guo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.

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An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the ad

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4

Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.

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In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show tha

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5

Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power effici

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6

Brenneman, Cody R. "Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.

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As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-ca

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7

David, Christopher Leonidas. "All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.

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The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architectur

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8

Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is select

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9

Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.

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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, ty

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10

Zeloufi, Mohamed. "Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT115.

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À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présenta

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11

Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.

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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (S

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12

Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

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<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR

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13

Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.

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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achiev

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14

Tirunelveli, Kanthi Saravanan. "Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33884.

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In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to conver

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15

Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.

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This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precis

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16

Kotti, Vivek. "Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087.

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17

Chan, Ka Yan. "Applying the "split-ADC" architecture to a 16 bit, 1 MS/s differential successive approximation analog-to-digital converter." Worcester, Mass. : Worcester Polytechnic Institute, 2008. http://www.wpi.edu/Pubs/ETD/Available/etd-043008-164352/.

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18

Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.

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The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microproc

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Lanot, Alisson Jamie Cruz. "Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/114478.

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Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar fal

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20

Kuntz, Taimur Gibran Rabuske. "TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA." Universidade Federal de Santa Maria, 2012. http://repositorio.ufsm.br/handle/1/5391.

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Conselho Nacional de Desenvolvimento Científico e Tecnológico<br>New trends and emerging technologies motivate the design of analog-to-digital converters (ADCs) which must fit in increasingly constrained environments. Within this context, one design metric which is constantly forced towards reduction is the power consumption, leading the designers to come up with improvements in both the architecture and circuit levels. This work aims to push forward the energy efficiency of the successive approximation charge sharing ADC, which is a relatively new and unexplored architecture. Therefore, three

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21

Lembard, Tomáš. "Speciální aplikace VoIP." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219188.

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The aim of this master's thesis is suggestion and following realization of voice transmission over the local network equipment and a description of used circuits and solutions in terms of hardware and software. This thesis deals with digitization of low-frequency signals, the structure of IP and UDP protocols, implementation of TCP/IP stack cIPS

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22

Hu, Ting-Wei, and 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.

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碩士<br>國立中興大學<br>電機工程學系所<br>104<br>This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added. The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue. With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement

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23

Wang, Po-Tsang, and 王柏蒼. "A Metal Density Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77v7sk.

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碩士<br>國立中興大學<br>電機工程學系所<br>105<br>This thesis presents a high speed successive approximation register (SAR) analog to digital converter (ADC) with input buffer and the study of non-ideal situation. The design purpose of this SAR ADC is to use it as one of sub ADCs for a Time-Interleaved ADC. The sample rate of this SAR ADC is 166MS/s, and the highest input frequency is 1.2GHz. In order to strengthen the driving power, we add a buffer to the front end. Last, but not least, considering the characteristic impedance in the high frequency will affect the input signal, we improved the PCB layout des

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Liang, Shing-Yan, and 梁興彥. "A Self-calibrating 10-bit Single End Successive Approximation Register ADC." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/rszv6d.

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Chang, Chun-Hao, and 張峻豪. "A High Effective Resolution Bandwidth High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/54170690466820934535.

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碩士<br>國立中興大學<br>電機工程學系所<br>103<br>This thesis presents a high effective resolution bandwidth (ERBW) high speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with differential input signals. This ADC is designed as the sub-ADC that constructs a time-interleaved ADC. Therefore, the range of ERBW is much considered. In addition, parallel signal paths are used in the control logic circuit to decrease the delay time of producing triggering signals, which enlarges the room for speeding up the sampling rate of the ADC compared with the conventional design. C

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Gandara, Miguel Francisco. "A 12-bit, 10 Msps two stage SAR-based pipeline ADC." 2012. http://hdl.handle.net/2152/19973.

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The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is present

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Ping-HsunChou and 周秉勳. "Power-Efficient Zero Crossing Based Pipelined Successive-Approximation-Register ADC with Asynchronous Timing Control." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/k4r4tf.

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碩士<br>國立成功大學<br>電機工程學系<br>102<br>In this thesis, a pipelined SAR ADC for wireless communication application is proposed. The proposed ADC is designed in the zero crossing based MDAC topology to achieve the features of high-speed and low-power consumption. In addition, the asynchronous timing control technique is utilized to reduce power consumption and enhance the operation speed. The pseudo differential zero crossing based MDAC with fast pre-charging technique is presented to improve the conversion rate and the amplification accuracy. The proposed pipelined SAR ADC consists of a five-bit and

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Tseng, Shih-Ying, and 曾世穎. "A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/29325643947363123037.

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碩士<br>國立中興大學<br>電機工程學系所<br>102<br>This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency of the analog-to-digital converter. In addition, the design can effectively enhance the sampling frequency by reduce the delay time of the critical path in digital control logic circuit. With TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process, the sampling frequencies a

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Liu, Zhi-Xun, and 劉智勛. "A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/33696364586971597428.

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碩士<br>國立中興大學<br>電機工程學系所<br>99<br>This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a frequency of 90KHz input signal measured ENOB = 8.62bit, INL =- 2.7524LSB ~ 4.5413LSB, DNL =- 1LSB ~ 4.8605LSB. To separate digital and analog power source, the attempt to use deep Nwell for the substrate noise isolation, to reduce the noise impact of the single-ended architecture. In addition, the DAC capaci

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Chang, Chen-Hao, and 張振豪. "A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/x2awww.

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Fontaine, Robert Alexander. "Investigation of 10-bit SAR ADC using flip-flip bypass circuit." Thesis, 2013. http://hdl.handle.net/2152/24011.

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The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion spe

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Fan, Duen-Ting, and 范敦庭. "A Low Voltage 10-bit 100-kS/s to 500kS/s Successive Approximation Register (SAR) ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/14155169596821478862.

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碩士<br>國立中正大學<br>電機工程研究所<br>104<br>In this work, a 10-bit 100-to-500KS/s asynchronous low power SAR ADC is realized. The supply voltage is scaled down appropriately (0.5 to 0.65V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, there are four techniques adopted, enhancing the comparison time, sampling time and reducing unnecessary settling time on whole conversion. The Double-Boosted sample-and-hold (DBS) circuit utilizes low-Vth device, resulting improve 92.25% of the sapling speed. To avoid the Metastability happened at the low-voltage environ

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Chung, Cheng-Yu, and 鍾承諭. "The Layout Study of a 10-bit Single End Successive Approximation Register ADC With Binary-weightedCapacitor Architecture." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/58167848625332115718.

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碩士<br>國立中興大學<br>電機工程學系所<br>100<br>This thesis focuses on the design and the layout of a 10-bit single ended Successive Approximation Register ADC. A complementary switch(sar14) and a bootstrap switch(sar15) are used for the sample and hold circuit, and the rail to rail input range is for the comparator design. Also, a binary-weighted capacitor architecture is used to achieve sub- circuit digital to analog converter. The layout is mainly set to separate the analog power source from the digital power source in order to keep the stability of analog circuit from interference made by digital circui

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Cheng, Yu Wei, and 鄭有惟. "A 0.5-V 10-bit 1.28-MS/s Successive Approximation register ADC for Bio-Medical Signal Acquisition Systems." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/02133786754419380461.

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碩士<br>國立清華大學<br>電機工程學系<br>103<br>In recent years, the design on bio-medical electronics has been getting more emphasized, especially the relative application on mobile device or portable monitors for the on time bio-signal acquitsition system. Low power consumption and high hardware efficiency are the trend of the requirement of portable devices. A 0.5-V 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. A capacitor switching detection circuit mainly constructed by two auxiliary

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Chang, Jia-Heng, and 張家恒. "Design of Successive Approximation Register ADCs for Biomedical and High-Bandwidth Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6rth23.

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碩士<br>國立交通大學<br>電機工程學系<br>106<br>In this thesis, a comprehensive discussion and research on successive approximation register (SAR) analog-to-digital converter (ADC) are presented. The SAR ADC can be used in either low-bandwidth or high-bandwidth system. This thesis presents two applications of the SAR ADC such as cochlear implant system in low-frequency application and the high-bandwidth system of wireless communication. To reduce the switching energy and save the total capacitance, a quarter-level shifting switching capacitor procedure is proposed. For cochlear implant system, the SAR ADC, i

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Fitas, Ricardo Jorge Barros. "Study of a Time Assisted SAR ADC." Master's thesis, 2017. http://hdl.handle.net/10362/30820.

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The demand for low power systems has been increasing in recent years and Analogto- Digital Converters (ADCs) are key blocks of many of these systems as they convert a physical quantity into the digital domain so that this information can be further processed or stored using digital techniques. Data Converters based on Charge Redistribution using of Successive Approximation Registers (SAR) are becoming one of the most popular ADC architectures for moderate speed, medium resolution and low power applications. Due to their low analog complexity SAR ADCs benefit from technology scaling. Howev

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Yang, Jiao. "Design of a low power 8-bit A/D converter for wireless neural recorder applications." Thesis, 2017. https://hdl.handle.net/2144/23685.

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Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/

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Pereira, Nuno Ruben Ferreira. "Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers." Doctoral thesis, 2019. http://hdl.handle.net/10362/91170.

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In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc si

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Chung, Hong-Yi, and 鐘鴻儀. "A 10-bit Successive Approximation ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57183272659084856815.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>98<br>Propose a fully differentially successive approximation ADC with a binary-weighted capacitor array networks. Add bootstrapped switches to accelerate charging to the capacitor networks in front of this architecture, and decrease the settling time of capacitor array. Also keep circuit operate correctly under low supply voltage driving switches. Use asynchronous control logic to generate the necessary clock signals internally, rather then provide clocks by external clock generator. Unit capacitors of the capacitor array are laid out in a common-centroid scheme to

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Yeh, Li-Ken, and 葉力墾. "A Successive Approximation ADC for Accelerometer System." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85409347982202791714.

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碩士<br>國立清華大學<br>電子工程研究所<br>97<br>This work presents a 10Ks/s 10-bit successive approximation analog-to-digital converter which is realized in a 0.35um CMOS process. The design combines an input offset storage latch-comparator, a sample and hold, a resistor-capacitor array DAC, and SAR digital logic while consuming less than 720uW with a 3.0V power supply. The experimental results show that the effective number of 7.61 bits with 10Ks/s and 100Hz signal frequency. Main purpose of the whole circuit is integrating into CMOS MESMS accelerometer and IIC interface circuit.

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Hui-WenChang and 張惠雯. "Adaptive Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/51357130831815732105.

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Liu, Te-Hsiang, and 劉德祥. "A Low-power 10-bit Successive Approximation ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/93018442633893142862.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>101<br>A low-power 10-bit successive approximation ADC for wireless sensor networks is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.7 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multilayered sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption. The low-power 10-bit successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS p

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Liu, Yu-Hsun, and 劉宇珣. "A Low Power Sub-range Successive-Approximation ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/29200334853561401027.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving tot

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Coe, Matthew T. "Digital implementation of a mismatch-shaping successive-approximation ADC." Thesis, 2001. http://hdl.handle.net/1957/31137.

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Utilizing a two-capacitor topology, the digital implementation of an audio-band successive-approximation analog-to-digital converter (ADC) is explored in the context of mismatch-shaping where the mismatch estimates are accurate to the first order. A second-order �� loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio of 10.<br>Graduation date: 2002

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Ting-ZiChen and 陳亭諮. "A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12587977983657161660.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>100<br>This thesis presents a 10-bit 50MS/S successive approximation ADC with low input capacitance that uses an on-chip resistive ladder and capacitor array to arrange a new switching scheme. This analog to digital converter possesses a predictive circuit in order to avoid unnecessary switching in DAC network. In addition, the proposed SAR ADC manipulates the concept of 1.5-bit/stage, which is usually employed in pipelined ADC to ease the design of coarse ADC. Besides, the ADC adopts hybrid capacitive and resistance DAC rather than a pure capacitive one. With thi

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Liao, Bo-Shi, and 廖柏詩. "Power-Efficient Successive-Approximation Register Analog-to-Digital Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/88290005656371369947.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification.

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Yeh, Chen-Kuang, and 葉晨光. "A successive approximation ADC based on a new segmented DAC." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/66685377242348443138.

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碩士<br>南台科技大學<br>電子工程系<br>90<br>A successive approximation analog-to-digital converter (ADC) based on a new segmented digital-to-analog converter (DAC) architecture is presented. A more efficient method which is the bi-direction segmented current-mode approach is proposed to implement the high-resolution and high speed DAC. This DAC has the maximum integral nonlinearity (INL) error of 0.47 LSB, and the maximum differential nonlinearity (DNL) error of 0.154 LSB. Based on this new DAC, a 3-V, 8-bit, 2-MS/s ADC is realized. The whole circuit is implemented by the TSMC 1P4M 0.35μm CMOS process. The

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Yeh, Kun-Ming, and 葉昆明. "Low Power Successive Approximation Register Analog to Digital Converter Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/52219798851756448222.

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碩士<br>國立中興大學<br>電機工程學系所<br>102<br>This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch a

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Lin, Wan-Ting, and 林宛葶. "Low Voltage Successive Approximation ADC with Calibration Technique for Biomedical Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/27223039221762818151.

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碩士<br>長庚大學<br>電子工程研究所<br>95<br>In a biomedical signal detecting system, ADC serves as an important role to translate biomedical signals from analog to digital for the back-end microprocessor to analyze and process. The demand of both resolution and precision of a biomedical signal detecting system is relatively high because the amplitude of biomedical signals is quite small. If the resolution and precision of ADC are too low, we can’t tell the difference of these biomedical signals, which might affect the doctor’s diagnosis. Based on characteristics of biomedical signals, several methods a

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Huang, Chia-Hsuan, and 黃嘉玄. "Low Power 12-bit Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82543200626928576057.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>Generally, the signal bandwidth of biomedical signals ( EEG, ECG, Oxygen Saturation, Heart Rate, Temperature ) is under 10 kHz [29]. For portable biomedical acquisition system, lower power A/D converter is an important component that can determine the performance of whole system. In this paper, a 1.8V 12-bit 200-kS/s successive approximation analog-to-digital converter (SAR ADC) is presented in this work. In order to overcome the biomedical signal’s dc shift and acquire accurately, the proposed ADC receives rail-to-rail input and performs 12-bit resolution (

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