Relevant bibliographies by topics / Successive Approximation Register Analog-to- Digital Converter

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Academic literature on the topic 'Successive Approximation Register Analog-to- Digital Converter'

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Published: 3 June 2025
Last updated: 22 June 2025

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Journal articles on the topic "Successive Approximation Register Analog-to- Digital Converter"

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Cao, Chao, and Haijun Guo. "High-resolution calibrated successive-approximation-register analog-to-digital converter." Integration 87 (November 2022): 205–10. http://dx.doi.org/10.1016/j.vlsi.2022.08.005.

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Cao, Chao, and Haijun Guo. "High-resolution calibrated successive-approximation-register analog-to-digital converter." Integration 87 (November 2022): 205–10. http://dx.doi.org/10.1016/j.vlsi.2022.08.005.

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Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

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In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.
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Du, Ling, Ning Ning, Shuangyi Wu, Qi Yu, and Yang Liu. "A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter." Journal of Computer and Communications 01, no. 06 (2013): 30–36. http://dx.doi.org/10.4236/jcc.2013.16006.

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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.
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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.
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Zhu, Donglin, Maliang Liu, and Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 01 (2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.

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In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.
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Pham, Duy Phong, Thanh Pham Xuan, Nguyen Thi Viet Ha, and Manh Kha Hoang. "Designing and simulation a 15-bit successive approximation register analog-to-digital converter." Journal of Military Science and Technology 87 (May 25, 2023): 1–8. http://dx.doi.org/10.54939/1859-1043.j.mst.87.2023.1-8.

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Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.
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R, Yashaswini, and Kumar N. Krishna Murthy. "Design and Simulation of 16 Bit ADC." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 1017–24. http://dx.doi.org/10.22214/ijraset.2023.54790.

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Abstract: In this study, it was looked into how a 16-bit architecture might be used to develop an Analog-to-Digital Converter (ADC) Successive Approximation Register (SAR). The SAR ADC architecture is widely adopted for high-resolution applications because to its ease of use and minimal power requirements. The design also includes a voltage reference, a comparator, a successive approximation register, a sample-and-hold circuit, an analog-to-digital converter (DAC), and other components. A range of design approaches and circuit topologies are employed to maximize performance and satisfy the required criteria. The comparator is intended to properly detect the analogue input voltage and operate at high speeds. A binary search technique is used by the successive approximation register to find the input voltage's digital representation. The design is implemented using 250nm Gate Diffusion Input [GDI] Technology. Simulation and verification are performed using Tanner EDA tool. The results indicate that the proposed 16-bit SAR ADC achieves the desired resolution and meets the specified performance requirements. The ADC exhibits low power consumption, and satisfactory performance. This architecture its applications span across multiple disciplines, encompassing communication systems, scientific instrumentation, and medical imaging, where there is a requirement for accurate ADC conversion.
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Zghoul, Fadi Nessir, Yousra Hussein Al-Bakrawi, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 3830. http://dx.doi.org/10.11591/ijece.v14i4.pp3830-3854.

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Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.
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Dissertations / Theses on the topic "Successive Approximation Register Analog-to- Digital Converter"

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Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.

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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
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David, Christopher Leonidas. "All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.

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The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
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Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.

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In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Brenneman, Cody R. "Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.

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As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.

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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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Lanot, Alisson Jamie Cruz. "Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/114478.

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Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada.<br>Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.
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Zeloufi, Mohamed. "Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT115.

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À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présentant une résolution de 12bits pour une fréquence d’échantillonnage de 40MS/s, ainsi qu’une résistance aux irradiations. Compte tenu du grand nombre des voies, ce CAN doit remplir des critères sévères sur la consommation et la surface. Le but de cette thèse est de concevoir un CAN innovant qui peut répondre à ces spécifications. Une architecture à approximations successives (SAR) a été choisie pour concevoir notre CAN. Cette architecture bénéficie d’une basse consommation de puissance et d’une grande compatibilité avec les nouvelles technologies CMOS. Cependant, le SAR souffre de certaines limitations liées principalement aux erreurs de décisions et aux erreurs d’appariement des capacités du CNA. Deux prototypes de CAN-SAR 12bits ont été modélisés en Matlab afin d’évaluer leur robustesse. Ensuite les conceptions ont été réalisées dans une technologie CMOS 130nm d’IBM validée par la collaboration ATLAS pour sa tenue aux irradiations. Les deux prototypes intègrent un algorithme d’approximations avec redondance en 14 étapes de conversion, qui permet de tolérer des marges d’erreurs de décisions et d’ajouter une calibration numérique des effets des erreurs d’appariement des capacités. La partie logique de nos CAN est très simplifiée pour minimiser les retards de génération des commandes et la consommation d’énergie. Cette logique exécute un algorithme monotone de commutation des capacités du CNA permettant une économie de 70% de la consommation dynamique par rapport à un algorithme de commutation classique. Grâce à cet algorithme, une réduction de capacité totale est aussi obtenue : 50% en comparant notre premier prototype à un seul segment avec une architecture classique. Pour accentuer encore plus le gain en termes de surface et de consommation, un second prototype a été réalisé en introduisant un CNA à deux segments. Cela a abouti à un gain supplémentaire d’un facteur 7,64 sur la surface occupée, un facteur de 12 en termes de capacité totale, et un facteur de 1,58 en termes de consommation. Les deux CAN consomment respectivement une puissance de ~10,3mW et ~6,5mW, et ils occupent respectivement une surface de ~2,63mm2 et ~0,344mm2.Afin d’améliorer leurs performances, un algorithme de correction numérique des erreurs d’appariement des capacités a été utilisé. Des buffers de tensions de référence ont étés conçus spécialement pour permettre la charge/décharge des capacités du convertisseur en hautes fréquences et avec une grande précision. En simulations électriques, les deux prototypes atteignent un ENOB supérieur à 11bits tout en fonctionnant à la vitesse de 40MS/s. Leurs erreurs d’INL simulés sont respectivement +1,14/-1,1LSB et +1,66/-1,72LSB.Les résultats de tests préliminaires du premier prototype présentent des performances similaires à celles d’un CAN commercial de référence sur notre carte de tests. Après la correction, ce prototype atteint un ENOB de 10,5bits et un INL de +1/-2,18LSB. Cependant suite à une panne de carte de tests, les résultats de mesures du deuxième prototype sont moins précis. Dans ces circonstances, ce dernier atteint un ENOB de 9,77bits et un INL de +7,61/-1,26LSB. En outre la carte de tests actuelle limite la vitesse de fonctionnement à ~9MS/s. Pour cela une autre carte améliorée a été conçue afin d’atteindre un meilleur ENOB, et la vitesse souhaitée. Les nouvelles mesures vont être publiées dans le futur<br>By 2024, the ATLAS experiment plan to operate at luminosities 10 times the current configuration. Therefore, many readout electronics must be upgraded. This upgrade is rendered necessary also by the damage caused by years of total radiations’ effect and devices aging. A new Front-End Board (FEB) will be designed for the LAr calorimeter readout electronics. A key device of this board is a radiation hard Analog-to-Digital Converter (ADC) featuring a resolution of 12bits at 40MS/s sampling rate. Following the large number of readout channels, this ADC device must display low power consumption and also a low area to easy a multichannel design.The goal of this thesis is to design an innovative ADC that can deal with these specifications. A Successive Approximation architecture (SAR) has been selected to design our ADC. This architecture has a low power consumption and many recent works has shown his high compatibility with modern CMOS scaling technologies. However, the SAR has some limitations related to decision errors and mismatches in capacitors array.Using Matlab software, we have created the models for two prototypes of 12bits SAR-ADC which are then used to study carefully their limitations, to evaluate their robustness and how it could be improved in digital domain.Then the designs were made in an IBM 130nm CMOS technology that was validated by the ATLAS collaboration for its radiation hardness. The prototypes use a redundant search algorithm with 14 conversion steps allowing some margins with comparator’s decision errors and opening the way to a digital calibration to compensate the capacitors mismatching effects. The digital part of our ADCs is very simplified to reduce the commands generation delays and saving some dynamic power consumption. This logic follows a monotonic switching algorithm which saves about70% of dynamic power consumption compared to the conventional switching algorithm. Using this algorithm, 50% of the total capacitance reduction is achieved when one compare our first prototype using a one segment capacitive DAC with a classic SAR architecture. To boost even more our results in terms of area and consumption, a second prototype was made by introducing a two segments DAC array. This resulted in many additional benefits: Compared to the first prototype, the area used is reduced in a ratio of 7,6, the total equivalent capacitance is divided by a factor 12, and finally the power consumption in improved by a factor 1,58. The ADCs respectively consume a power of ~10,3mW and ~6,5mW, and they respectively occupy an area of ~2,63mm2 and ~0,344mm2.A foreground digital calibration algorithm has been used to compensate the capacitors mismatching effects. A high frequency open loop reference voltages buffers have been designed to allow the high speed and high accuracy charge/discharge of the DAC capacitors array.Following electrical simulations, both prototypes reach an ENOB better than 11bits while operating at the speed of 40MS/s. The INL from the simulations were respectively +1.14/-1.1LSB and +1.66/-1.72LSB.The preliminary testing results of the first prototype are very close to that of a commercial 12bits ADC on our testing board. After calibration, we measured an ENOB of 10,5bits and an INL of +1/-2,18LSB. However, due to a testing board failure, the testing results of the second prototype are less accurate. In these circumstances, the latter reached an ENOB of 9,77bits and an INL of +7,61/-1,26LSB. Furthermore the current testing board limits the operating speed to ~9MS/s. Another improved board was designed to achieve a better ENOB at the targeted 40MS/s speed. The new testing results will be published in the future
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.

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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.<br><p>QC 20170905</p>
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Books on the topic "Successive Approximation Register Analog-to- Digital Converter"

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Hung, Chung-Chih, and Shih-Hsing Wang. Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-to-Digital Converter for Biomedical Applications. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-88845-9.

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Yang, Ada. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2015.

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Yang, Ada. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Ferrigan, Kelly. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2020.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2017.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Microchip Technology Incorporated, 2015.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) FRM. Microchip Technology Incorporated, 2016.

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Aiyappa, Rekha. Section 22. 12-Bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) FRM. Microchip Technology Incorporated, 2019.

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Hung, Chung-Chih, and Shih-Hsing Wang. Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-To-Digital Converter for Biomedical Applications. Springer International Publishing AG, 2021.

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Book chapters on the topic "Successive Approximation Register Analog-to- Digital Converter"

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Konwar, Shruti, Utkarsh Jaiswal, and Bibhu Datta Sahoo. "Successive Approximation Register Analog-to-Digital Converter—A Tutorial." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0055-8_36.

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Artan, Nabi Sertac. "Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices." In Biomedical Engineering. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3158-6.ch018.

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The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.
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Artan, Nabi Sertac. "Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices." In Wearable Technologies. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-5484-4.ch012.

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The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.
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Wu, Pan, Bingyang Liu, Xuefei Zhao, and Bo Gao. "Design and Simulation of the 16-bit SAR ADC." In Advances in Transdisciplinary Engineering. IOS Press, 2024. https://doi.org/10.3233/atde241315.

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The paper presents a high-precision successive approximation register (SAR) analog-to-digital converters (ADCs) for the bio-signal detection in internet of things (IoT) applications. A 16-bit SAR ADC with 2.5V input voltage range is designed using 180nm CMOS process. The 16-bit SAR ADC mainly includes bootstrap switches, a capacitor DAC (CDAC), a dynamic comparator, SAR logic with rotation averaging correction. The CDAC adopts a three-segment structure to realize the high resolution. The control timing sequence of the SAR ADC is VCM-based, further reducing the area of the capacitor array, and the rotational averaging algorithm is designed to correct capacitor mismatch. The power supply voltage is 3.3V, and the overall layout area is about 3.5mm2. The post-simulation shows that SNDR is 86.32dB, the SFDR is 98.01dB, and the ENOB is 14.04bit. The overall power consumption is 2.56mW.
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Conference papers on the topic "Successive Approximation Register Analog-to- Digital Converter"

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Kuo, Ko-Chi, and Jia-Wei Chen. "A 10-Bit Successive Approximation Register Analog to Digital Converter Using VCO-Based Time-Domain Comparator." In 2025 1st International Conference on Consumer Technology (ICCT-Pacific). IEEE, 2025. https://doi.org/10.1109/icct-pacific63901.2025.11012804.

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Kuo, Ko-Chi, Hung-Yi Chang, and Chun-Wei Huang. "A 10-bit 300MS/s Time-Interleaved Successive-Approximation Register Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array and fault-tolerant." In 2024 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan). IEEE, 2024. http://dx.doi.org/10.1109/icce-taiwan62264.2024.10674124.

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Zhang, Yuanchang, Wei Zhang, Yuan Fei, Mengke Cai, Jing Qiu, and Hai-zhi Song. "Research on Successive Approximation Analog-to-Digital Converter Circuit for Readout Circuit." In 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2024. https://doi.org/10.1109/icicm63644.2024.10814595.

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Deepti, Kakarla, and S. Aruna Deepti. "Design and Implementation of Low Power and High-Performance Successive Approximation Analog to Digital Converter." In 2024 IEEE 4th International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC). IEEE, 2024. https://doi.org/10.1109/aespc63931.2024.10872153.

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Lee, Tzung-Je, Shih-Hsien Kuo, Ji-Hau Chiou, Chua-Chin Wang, and Friedel Gerfers. "A Low-Power 10-bit 72 MS/s Continuous Successive-Approximation Analog-to-Digital Converter." In 2025 IEEE Open Conference of Electrical, Electronic and Information Sciences (eStream). IEEE, 2025. https://doi.org/10.1109/estream66938.2025.11016865.

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Jhung, Seungho, Kilyoung Ko, Minju Lee, Seungryong Cho, Gyuseong Cho, and Inyong Kwon. "Radiation-hardened successive approximation register analog-to-digital converter." In 2020 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2020. http://dx.doi.org/10.1109/iceic49074.2020.9051346.

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Kuntz, Taimur Gibran Rabuske, and Saeid Nooshabadi. "An energy-efficient successive approximation register analog to digital converter in 180nm." In APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2010. http://dx.doi.org/10.1109/apccas.2010.5774967.

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Lai, Wen-Cheng, Jhin-Fang Huang, Ting Ye, and Chieh Wen Shih. "Integrated successive approximation register analog-to-digital converter for healthcare systems applications." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021242.

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Wei, Zebin, Min Gong, and Bo Gao. "Design of a High-voltage Successive Approximation Register Analog-to-Digital Converter." In 2021 IEEE 4th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE). IEEE, 2021. http://dx.doi.org/10.1109/auteee52864.2021.9668632.

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Sung, Guo-Ming, Po-En Wu, and Jun-Min Xu. "10-Bit Successive Approximation Register Analog-to-Digital Converter for BLDC Motor Drive." In 2020 International Symposium on Computer, Consumer and Control (IS3C). IEEE, 2020. http://dx.doi.org/10.1109/is3c50286.2020.00065.

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