Academic literature on the topic 'Successive approximation register analog-to-digital converter (SAR-ADC)'

The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.

Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.

In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm

À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présentant une résolution de 12bits pour une fréquence d’échantillonnage de 40MS/s, ainsi qu’une résistance aux irradiations. Compte tenu du grand nombre des voies, ce CAN doit remplir des critères sévères sur la consommation et la surface. Le but de cette thèse est de concevoir un CAN innovant qui peut répondre à ces spécifications. Une architecture à approximations successives (SAR) a été choisie pour concevoir notre CAN. Cette architecture bénéficie d’une basse consommation de puissance et d’une grande compatibilité avec les nouvelles technologies CMOS. Cependant, le SAR souffre de certaines limitations liées principalement aux erreurs de décisions et aux erreurs d’appariement des capacités du CNA. Deux prototypes de CAN-SAR 12bits ont été modélisés en Matlab afin d’évaluer leur robustesse. Ensuite les conceptions ont été réalisées dans une technologie CMOS 130nm d’IBM validée par la collaboration ATLAS pour sa tenue aux irradiations. Les deux prototypes intègrent un algorithme d’approximations avec redondance en 14 étapes de conversion, qui permet de tolérer des marges d’erreurs de décisions et d’ajouter une calibration numérique des effets des erreurs d’appariement des capacités. La partie logique de nos CAN est très simplifiée pour minimiser les retards de génération des commandes et la consommation d’énergie. Cette logique exécute un algorithme monotone de commutation des capacités du CNA permettant une économie de 70% de la consommation dynamique par rapport à un algorithme de commutation classique. Grâce à cet algorithme, une réduction de capacité totale est aussi obtenue : 50% en comparant notre premier prototype à un seul segment avec une architecture classique. Pour accentuer encore plus le gain en termes de surface et de consommation, un second prototype a été réalisé en introduisant un CNA à deux segments. Cela a abouti à un gain supplémentaire d’un facteur 7,64 sur la surface occupée, un facteur de 12 en termes de capacité totale, et un facteur de 1,58 en termes de consommation. Les deux CAN consomment respectivement une puissance de ~10,3mW et ~6,5mW, et ils occupent respectivement une surface de ~2,63mm2 et ~0,344mm2.Afin d’améliorer leurs performances, un algorithme de correction numérique des erreurs d’appariement des capacités a été utilisé. Des buffers de tensions de référence ont étés conçus spécialement pour permettre la charge/décharge des capacités du convertisseur en hautes fréquences et avec une grande précision. En simulations électriques, les deux prototypes atteignent un ENOB supérieur à 11bits tout en fonctionnant à la vitesse de 40MS/s. Leurs erreurs d’INL simulés sont respectivement +1,14/-1,1LSB et +1,66/-1,72LSB.Les résultats de tests préliminaires du premier prototype présentent des performances similaires à celles d’un CAN commercial de référence sur notre carte de tests. Après la correction, ce prototype atteint un ENOB de 10,5bits et un INL de +1/-2,18LSB. Cependant suite à une panne de carte de tests, les résultats de mesures du deuxième prototype sont moins précis. Dans ces circonstances, ce dernier atteint un ENOB de 9,77bits et un INL de +7,61/-1,26LSB. En outre la carte de tests actuelle limite la vitesse de fonctionnement à ~9MS/s. Pour cela une autre carte améliorée a été conçue afin d’atteindre un meilleur ENOB, et la vitesse souhaitée. Les nouvelles mesures vont être publiées dans le futur<br>By 2024, the ATLAS experiment plan to operate at luminosities 10 times the current configuration. Therefore, many readout electronics must be upgraded. This upgrade is rendered necessary also by the damage caused by years of total radiations’ effect and devices aging. A new Front-End Board (FEB) will be designed for the LAr calorimeter readout electronics. A key device of this board is a radiation hard Analog-to-Digital Converter (ADC) featuring a resolution of 12bits at 40MS/s sampling rate. Following the large number of readout channels, this ADC device must display low power consumption and also a low area to easy a multichannel design.The goal of this thesis is to design an innovative ADC that can deal with these specifications. A Successive Approximation architecture (SAR) has been selected to design our ADC. This architecture has a low power consumption and many recent works has shown his high compatibility with modern CMOS scaling technologies. However, the SAR has some limitations related to decision errors and mismatches in capacitors array.Using Matlab software, we have created the models for two prototypes of 12bits SAR-ADC which are then used to study carefully their limitations, to evaluate their robustness and how it could be improved in digital domain.Then the designs were made in an IBM 130nm CMOS technology that was validated by the ATLAS collaboration for its radiation hardness. The prototypes use a redundant search algorithm with 14 conversion steps allowing some margins with comparator’s decision errors and opening the way to a digital calibration to compensate the capacitors mismatching effects. The digital part of our ADCs is very simplified to reduce the commands generation delays and saving some dynamic power consumption. This logic follows a monotonic switching algorithm which saves about70% of dynamic power consumption compared to the conventional switching algorithm. Using this algorithm, 50% of the total capacitance reduction is achieved when one compare our first prototype using a one segment capacitive DAC with a classic SAR architecture. To boost even more our results in terms of area and consumption, a second prototype was made by introducing a two segments DAC array. This resulted in many additional benefits: Compared to the first prototype, the area used is reduced in a ratio of 7,6, the total equivalent capacitance is divided by a factor 12, and finally the power consumption in improved by a factor 1,58. The ADCs respectively consume a power of ~10,3mW and ~6,5mW, and they respectively occupy an area of ~2,63mm2 and ~0,344mm2.A foreground digital calibration algorithm has been used to compensate the capacitors mismatching effects. A high frequency open loop reference voltages buffers have been designed to allow the high speed and high accuracy charge/discharge of the DAC capacitors array.Following electrical simulations, both prototypes reach an ENOB better than 11bits while operating at the speed of 40MS/s. The INL from the simulations were respectively +1.14/-1.1LSB and +1.66/-1.72LSB.The preliminary testing results of the first prototype are very close to that of a commercial 12bits ADC on our testing board. After calibration, we measured an ENOB of 10,5bits and an INL of +1/-2,18LSB. However, due to a testing board failure, the testing results of the second prototype are less accurate. In these circumstances, the latter reached an ENOB of 9,77bits and an INL of +7,61/-1,26LSB. Furthermore the current testing board limits the operating speed to ~9MS/s. Another improved board was designed to achieve a better ENOB at the targeted 40MS/s speed. The new testing results will be published in the future

Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.<br><p>QC 20170905</p>

The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada.<br>Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.