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1
Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.
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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance.
The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18µ<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required.
A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control.
The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
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David, Christopher Leonidas. "All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.
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The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
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Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.
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In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Brenneman, Cody R. "Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.
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As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.
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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.
This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.
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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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Lanot, Alisson Jamie Cruz. "Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/114478.
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Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada.<br>Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.
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Zeloufi, Mohamed. "Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT115.
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À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne correspondra pas aux conditions de ces luminosités. Dans ces conditions, une nouvelle électronique devra être conçue. Cette mise à niveau est rendue nécessaire aussi par les dommages causés par les radiations et le vieillissement. Une nouvelle carte frontale va être intégrée dans l’électronique de lecture du calorimètre LAr. Un élément essentiel de cette carte est le Convertisseur Analogique-Numérique (CAN) présentant une résolution de 12bits pour une fréquence d’échantillonnage de 40MS/s, ainsi qu’une résistance aux irradiations. Compte tenu du grand nombre des voies, ce CAN doit remplir des critères sévères sur la consommation et la surface. Le but de cette thèse est de concevoir un CAN innovant qui peut répondre à ces spécifications. Une architecture à approximations successives (SAR) a été choisie pour concevoir notre CAN. Cette architecture bénéficie d’une basse consommation de puissance et d’une grande compatibilité avec les nouvelles technologies CMOS. Cependant, le SAR souffre de certaines limitations liées principalement aux erreurs de décisions et aux erreurs d’appariement des capacités du CNA. Deux prototypes de CAN-SAR 12bits ont été modélisés en Matlab afin d’évaluer leur robustesse. Ensuite les conceptions ont été réalisées dans une technologie CMOS 130nm d’IBM validée par la collaboration ATLAS pour sa tenue aux irradiations. Les deux prototypes intègrent un algorithme d’approximations avec redondance en 14 étapes de conversion, qui permet de tolérer des marges d’erreurs de décisions et d’ajouter une calibration numérique des effets des erreurs d’appariement des capacités. La partie logique de nos CAN est très simplifiée pour minimiser les retards de génération des commandes et la consommation d’énergie. Cette logique exécute un algorithme monotone de commutation des capacités du CNA permettant une économie de 70% de la consommation dynamique par rapport à un algorithme de commutation classique. Grâce à cet algorithme, une réduction de capacité totale est aussi obtenue : 50% en comparant notre premier prototype à un seul segment avec une architecture classique. Pour accentuer encore plus le gain en termes de surface et de consommation, un second prototype a été réalisé en introduisant un CNA à deux segments. Cela a abouti à un gain supplémentaire d’un facteur 7,64 sur la surface occupée, un facteur de 12 en termes de capacité totale, et un facteur de 1,58 en termes de consommation. Les deux CAN consomment respectivement une puissance de ~10,3mW et ~6,5mW, et ils occupent respectivement une surface de ~2,63mm2 et ~0,344mm2.Afin d’améliorer leurs performances, un algorithme de correction numérique des erreurs d’appariement des capacités a été utilisé. Des buffers de tensions de référence ont étés conçus spécialement pour permettre la charge/décharge des capacités du convertisseur en hautes fréquences et avec une grande précision. En simulations électriques, les deux prototypes atteignent un ENOB supérieur à 11bits tout en fonctionnant à la vitesse de 40MS/s. Leurs erreurs d’INL simulés sont respectivement +1,14/-1,1LSB et +1,66/-1,72LSB.Les résultats de tests préliminaires du premier prototype présentent des performances similaires à celles d’un CAN commercial de référence sur notre carte de tests. Après la correction, ce prototype atteint un ENOB de 10,5bits et un INL de +1/-2,18LSB. Cependant suite à une panne de carte de tests, les résultats de mesures du deuxième prototype sont moins précis. Dans ces circonstances, ce dernier atteint un ENOB de 9,77bits et un INL de +7,61/-1,26LSB. En outre la carte de tests actuelle limite la vitesse de fonctionnement à ~9MS/s. Pour cela une autre carte améliorée a été conçue afin d’atteindre un meilleur ENOB, et la vitesse souhaitée. Les nouvelles mesures vont être publiées dans le futur<br>By 2024, the ATLAS experiment plan to operate at luminosities 10 times the current configuration. Therefore, many readout electronics must be upgraded. This upgrade is rendered necessary also by the damage caused by years of total radiations’ effect and devices aging. A new Front-End Board (FEB) will be designed for the LAr calorimeter readout electronics. A key device of this board is a radiation hard Analog-to-Digital Converter (ADC) featuring a resolution of 12bits at 40MS/s sampling rate. Following the large number of readout channels, this ADC device must display low power consumption and also a low area to easy a multichannel design.The goal of this thesis is to design an innovative ADC that can deal with these specifications. A Successive Approximation architecture (SAR) has been selected to design our ADC. This architecture has a low power consumption and many recent works has shown his high compatibility with modern CMOS scaling technologies. However, the SAR has some limitations related to decision errors and mismatches in capacitors array.Using Matlab software, we have created the models for two prototypes of 12bits SAR-ADC which are then used to study carefully their limitations, to evaluate their robustness and how it could be improved in digital domain.Then the designs were made in an IBM 130nm CMOS technology that was validated by the ATLAS collaboration for its radiation hardness. The prototypes use a redundant search algorithm with 14 conversion steps allowing some margins with comparator’s decision errors and opening the way to a digital calibration to compensate the capacitors mismatching effects. The digital part of our ADCs is very simplified to reduce the commands generation delays and saving some dynamic power consumption. This logic follows a monotonic switching algorithm which saves about70% of dynamic power consumption compared to the conventional switching algorithm. Using this algorithm, 50% of the total capacitance reduction is achieved when one compare our first prototype using a one segment capacitive DAC with a classic SAR architecture. To boost even more our results in terms of area and consumption, a second prototype was made by introducing a two segments DAC array. This resulted in many additional benefits: Compared to the first prototype, the area used is reduced in a ratio of 7,6, the total equivalent capacitance is divided by a factor 12, and finally the power consumption in improved by a factor 1,58. The ADCs respectively consume a power of ~10,3mW and ~6,5mW, and they respectively occupy an area of ~2,63mm2 and ~0,344mm2.A foreground digital calibration algorithm has been used to compensate the capacitors mismatching effects. A high frequency open loop reference voltages buffers have been designed to allow the high speed and high accuracy charge/discharge of the DAC capacitors array.Following electrical simulations, both prototypes reach an ENOB better than 11bits while operating at the speed of 40MS/s. The INL from the simulations were respectively +1.14/-1.1LSB and +1.66/-1.72LSB.The preliminary testing results of the first prototype are very close to that of a commercial 12bits ADC on our testing board. After calibration, we measured an ENOB of 10,5bits and an INL of +1/-2,18LSB. However, due to a testing board failure, the testing results of the second prototype are less accurate. In these circumstances, the latter reached an ENOB of 9,77bits and an INL of +7,61/-1,26LSB. Furthermore the current testing board limits the operating speed to ~9MS/s. Another improved board was designed to achieve a better ENOB at the targeted 40MS/s speed. The new testing results will be published in the future
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.<br><p>QC 20170905</p>
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Radhakrishnan, Ram Harshvardhan. "Accelerated Successive Approximation Technique for Analog to Digital Converter Design." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1630.
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This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
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Kuntz, Taimur Gibran Rabuske. "TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA." Universidade Federal de Santa Maria, 2012. http://repositorio.ufsm.br/handle/1/5391.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico<br>New trends and emerging technologies motivate the design of analog-to-digital
converters (ADCs) which must fit in increasingly constrained environments. Within
this context, one design metric which is constantly forced towards reduction is the
power consumption, leading the designers to come up with improvements in both the
architecture and circuit levels. This work aims to push forward the energy efficiency of
the successive approximation charge sharing ADC, which is a relatively new and unexplored
architecture. Therefore, three complete ADCs are designed throughout this
work, each one bringing novelties that help decreasing the power consumption. The
techniques devised here include novel manners of dealing with the tracking of the input
signal and a circuit to reduce power drained in the pre-charge cycle. Also, three different
architectures of digital controller for this ADC topology are designed. Moreover,
a novel bootstrapping switch circuit is presented, which provides lower devices-count
and a extremely high energy efficiency.<br>As novas tendências e tecnologias emergentes motivam o projeto de conversores
analógico-digitais (ADCs) que precisam suprir especificações cada vez mais restritivas.
Nesse contexto, uma métrica de projeto que é constantemente forçada em direção à
redução é o consumo de potência, fato esse que leva à concepção de melhorias tanto
em nível arquitetural como em nível de circuito elétrico. Este trabalho tem como objetivo
elevar a eficiência energética dos ADCs por aproximações sucessivas e compartilhamento
de carga, visto que essa é uma arquitetura relativamente nova e inexplorada.
Portanto, três ADCs completos são projetados ao longo deste trabalho, e cada um traz
inovações que ajudam a reduzir o consumo de potência. As técnicas concebidas aqui
incluem maneiras novas de efetuar a captura do sinal de entrada e um circuito para
reduzir a potência drenada no ciclo de pré-carga. Além disso, três arquiteturas diferentes
de controlador digital para essa topologia de ADC são expostas. Mais, um novo
circuito de chave com bootstrapping é apresentado, o qual apresenta um número de
dispositivos menor e uma eficiência energética extremamente alta.
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Yang, Kun. "A 16 Bit 500KSps low power successive approximation analog to digital converter." Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Thesis/Fall2009/k_yang_111809.pdf.
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Thesis (M.S. in electrical engineering)--Washington State University, December 2009.<br>Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
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Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.
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This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence.
As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes.
The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization.
Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.
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Chan, Ka Yan. "Applying the "split-ADC" architecture to a 16 bit, 1 MS/s differential successive approximation analog-to-digital converter." Worcester, Mass. : Worcester Polytechnic Institute, 2008. http://www.wpi.edu/Pubs/ETD/Available/etd-043008-164352/.
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DESAI, VANDANA. "TRANSISTOR-LEVEL SIMULATION OF A NOVEL CMOS BINARY SEARCH BASED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER CIRCUIT." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1148305344.
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BHOOPATHY, MANIVANNAN. "EXPLOITING A MULTI-LEVEL MODELING TECHNIQUE WITH APPLICATION TO THE ANALYSIS OF A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132016200.
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Kotti, Vivek. "Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087.
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Liao, Bo-Shi, and 廖柏詩. "Power-Efficient Successive-Approximation Register Analog-to-Digital Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/88290005656371369947.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification.
In the field of low power SAR ADC, an 12-bit 10MS/s single-channel SAR and 7-bit 2GS/s calibration-free time-interleaved ADC are presented. This thesis first proposes an energy-efficient high resolution SAR ADC with small unit capacitance and simple controller logic. In order to save digital power, it combined with arbitrary capacitor array, which tolerates errors of dynamic offset and capacitor settling in MSBs during conversion and a differential control logic circuit are proposed to decrease the circuit complexity. The technique are verified by TSMC 1P6M3X1Z1U 40nm Low Power CMOS process. This work operates at 10MS/s in 0.9V supply voltage. Its power dissipation is only 36.9μW and gets 10.05 bit ENOB performance after off-chip calibration with low-frequency input. As the result, the peak FoM performance is 3.48fJ/conversion-step.
In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it. In addition, a front-end track-and-hold circuit is implemented in order to eliminate time skew mismatch. This time-interleaved ADC in 55nm CMOS technology post-simulation achieves an ENOB of 6.8 and consumes 24.8mW. It results in a FoM of 117fJ/conversion-step.
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Yeh, Kun-Ming, and 葉昆明. "Low Power Successive Approximation Register Analog to Digital Converter Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/52219798851756448222.
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碩士<br>國立中興大學<br>電機工程學系所<br>102<br>This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch are used.
The SAR ADC is designed and simulated by HSPICE with TSMC 0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS technology. The supply voltage of the 8-bit SAR ADC is 1.8V and the sampling rate is 5KHz. Its power consumption is 1100μW.
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Lin, Jhao-Huei, and 林昭輝. "All Digital Capacitance Calibration for Successive-Approximation Register Analog-to-Digital Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/btzwa7.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>106<br>This thesis presents a 12-bit 1 MS/s high power-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with 0.7V supply voltage. By using detect-and-skip (DAS) algorithm, the capacitive digital-to-analog converter (DAC) switching power can be reduced. To be more power-efficient, the unit capacitance can shrink to decrease the DAC switching power largely.
There is a bottleneck of weight compensation when the ADC takes the DAS algorithm to switch DAC. The weight-split compensation (WSC) can overcome this bottleneck perfectly. In the calibration mode, the reconfigurable redundancy can resolve the problem of the comparator offset. In addition, the Vcm-based tracking switching can enhance the resolution to decrease the calibration converge time.
The propose ADC is fabricated using a 40-nm CMOS process. It consumes 2.47 W from a 0.7-V supply at a conversion-rate of 1 MS/s. After foreground calibration, the measured DNL and INL are +0.61/-0.57 and +0.93/-0.92 LSB. The measured SNDR and SFDR are at 66.54 dB and 89.55 dB, respectively. The ENOB performance is 10.75 b, which is equivalent to a Walden and Schreier figure-of-merit of 1.47 fJ/conversion-step and 179.6 dB, respectively.
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Lee, Mao-Cheng, and 李茂誠. "Design of Low Power Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/91556839843235408859.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>To date ADCs play essential roles in the communication fields and in the bio-sensor applications. High-speed and low-power Analog-to-Digital converters (ADCs) are required in these applications. However, with the development of the CMOS technology, the design of high quality analog circuits becomes a challenge. The Successive approximation Register
(SAR) architectures primarily consist of digital circuits. With this property, the SAR ADCs are more suitable fabricated in advanced CMOS technology than other structures.
In this thesis, we present two SAR ADC architectures: a R-2R ladder DAC and a binary capacitive DAC. For the high speed applications, we chose a R-2R resistive DAC in our first work. We design a 10-bit R-2R ladder SAR ADC in TSMC 65nm CMOS technology. In addition, for the high resolution applications, we design a 12-bit capacitive SAR ADC in TSMC 65nm CMOS technology and we introduce two digital calibration technologies in this work.
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Chen, Chun-Fu, and 陳俊甫. "1.2V 10-bits Low Power Successive Approximation Register Analog-to-Digital Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/494753.
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碩士<br>國立虎尾科技大學<br>電機工程研究所<br>99<br>Recently, low power ADC has been developed for many energy-constrained applications, such as wireless sensor networks and bio-medical applications. Among many types of ADC, slope ADC, sigma-delta ADC, and successive approximation register ADC (SAR ADC) are good candidates for low power applications. SAR ADC has recently become very attractive due to their minimal active analog circuit requirements.
SAR ADC consists of dual sampling capacitor, sample-and-hold circuit (S/H), digital-to-analog converter (DAC), comparator, and successive approximation register. Bootstrapped switch is applied to sample-and-hold circuit to achieve rail-to-rail signal swing at low-voltage power supply. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC.
In this research, 10-bits 727kS/s SAR ADC under a single 1.2V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 57.5dB and SNDR of 56.3dB. The peak DNL is -0.7LSB ~ 0.95 LSB, the peak INL is -1.22LSB ~ 1.48LSB, and the power dissipation is about 21.9μW. Simulations have been performed to demonstrate the feasibility of this new technique.
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Ting-YuanChen and 陳丁源. "A Dual-Mode Successive-Approximation-Register Analog-to-Digital Converter for Biomedical Application." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78669934387424044578.
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碩士<br>國立成功大學<br>電機工程學系<br>103<br>This thesis presents a successive-approximation-register analog-to-digital converter (SAR ADC) which can measure voltage and current. By the techniques of exchanging capacitor arrays and multi-sampling, SAR ADC is enabled to sense current. Therefore, a dual-mode SAR ADC for biomedical application is achieved.
Because of biomedical application, power consumption is critical for the proposed circuit. Consequently, supply voltage of the proposed circuit is reduced to 0.5 V, and split capacitor array and differential control logic are adopted in the proposed circuit to reduce power consumption. Besides, double-bootstrapped technique and stacked-transistor technique are used in switches to enhance conductivity and solve leakage problem.
The proposed dual-mode SAR ADC is implemented by TSMC 0.18-μm 1P6M CMOS process. According to simulation results, the peak SNDR is 60 dB with sampling frequency of 20 kHz in voltage mode. The power consumption is 63.44 nW and the Figure-of-Merit (FoM) is 3.88 fJ/conversion. In current mode, the sensitivity of 1.18 pA is achieved with sampling frequency of 1 kHz. The measurement results shows that the peak SNDR is 51.95 dB with sampling frequency of 20 kHz in voltage mode. The power consumption is 64.46 nW and the Figure-of-Merit (FoM) is 9.94 fJ/conversion.
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Lin, Wei-Ting, and 林葦婷. "A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14040227441703086392.
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碩士<br>國立清華大學<br>電機工程學系<br>101<br>This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output better accuracy and higher speed because of positive feedback. Split capacitor array is used in D/A converter to decrease the total capacitance and save average power. Finally, the SAR control logic circuit uses a form of shift-registers-control conversion process and a row of D flip-flops for controlling the spilt capacitor array.
The performance of the converter would be degraded due to the process variation and device mismatches. This thesis proposes self-correction circuits for comparator and D/A separately capacitor array calibration, larger LSB is chosen as a new reference unit capacitor, and produce a new binary-weighted capacitor array by charge redistribution. After D/A calibration, comparator input offset voltage needs to be calibrated and canceled. Because this offset is not linear, a new calibration method is proposed that divides input voltage into multiple windows and use piecewise linear approximation to predict and reduce input offset. Before normal operation, calibration mode is created to do DAC and comparator calibrations. Digital calibration codes are saved in latches, and these digital codes can be used in normal operation mode without wasting other clock cycles. After digital calibration, when sampling rate is 100KS/s, the SNDR is found to be 66.78dB, and ENOB is 10.8 bits. DNL and INL are found to be 0.69 and 0.86 LSB, respectively.
Comparing to other calibration methods, the proposed calibration can predict and reduce offset for full range input voltages, thus has higher accuracy than other digital calibration methods. Since the digital calibration is used, calibration results are saved in flipflops and can be reused repeatedly. Smaller chip and shorter normal mode operation can be achieved. In addition, digital circuit is easier to scale and thus needs smaller area for advanced technologies.
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Lin, Ding-Kuo, and 林鼎國. "Power-Efficient and High-Resolution Successive-approximation Register Analog-to-Digital Converter with Digital Calibration." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/332j2n.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>106<br>An analog-to-digital converter (ADC) transforming natural signals to digital form can be used for many digital signal processor (DSP) applications such as smartphone and computer. A 0.7V 12-bit 1MS/s ADC fabricated in 40nm CMOS is proposed in the thesis.
The subranging architecture is used for improvement of speed and power. The detect-and-skip (DAS) algorithm and aligned switching method are adopted to reduce the switching energy of the DAC. To relax the noise design of comparator, tracking average is applied. With proposed capacitor calibration, we can use 0.5fF unit capacitor without affecting the performance of the ADC.
The subranging SAR ADC achieves an ENOB of 10.75 at 1MS/s sampling rate with Nyquist input frequency. The active area is only 0.0198 mm2. It consumes 2.47uW and FoMw of 1.43fJ/conversion-step. It is suitable for portable, wearable and biomedical devices with low power consumption.
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Tsai, Jen-Huan, and 蔡任桓. "Design of High-performance and Low-power Successive Approximation Register (SAR) Analog-to-Digital Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/70964394150851781416.
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Wang, Deng-Shian, and 王登賢. "A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/28138434795346363350.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>101<br>This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by using TSMC 0.25 μm 60V HV CMOS process, and verified by physical measurements.
Though the first topic presents a high-voltage multiplexer which is fabricated using an advanced high-voltage (HV) semiconductor process, the HV process usually is constrained by the voltage drop limitation between gate and source of HV CMOS transistors. To overcome such a limitation, a high-voltage switch is proposed in this work, including two gate voltage drivers and a buck converter driving the HV devices without causing any over-voltage hazard. Based on the system requirements, the output range of the HV multiplexer should be covered by the input range of the following ADC. The multiplexer employs a divider &; subtracter and a multiplier to carry out such a function. The entire design is designed for the voltage detection circuit in the Battery Management Systems, where the voltage detection error is verified to be less than 10 mV by simulations.
The second topic discloses a successive-approximation register ADC for the voltage detection as well in the Battery Management Systems. Due to the gentle variation of the battery voltage characteristic, an ADC with 20 KHz sampling rate and 12–bit resolution is proposed and used in the detection circuit. To reduce the capacitor size in the ADC, a single capacitor array based on the charge redistribution architecture is used in the proposed ADC. By the simulation results, the integral nonlinearity (INL) and the differential nonlinearity (DNL) of the proposed ADC are both less than two LSBs such that the error is less than 1 mV.
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Chi, Hsing-Yu, and 吉星宇. "A 8-bit Domino-style with Multiple Comparator Successive Approximation Register Analog to Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yw9ang.
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碩士<br>國立中山大學<br>資訊工程學系研究所<br>107<br>This thesis adopt a 90-nm TSMC process to complete a single-channel Domino-Successive Approximation Register Analog to Digital Converter progressive digital analog converter.
In the case of medium and high speed, in order to make the ADC have a certain fault tolerance, we added a redundant bit, so the whole conversion step is used to achieve the effect of eight bits. In order to improve the overall conversion speed, the first comparison is performed without switching any logic switches after sampling. This method can speed up the overall circuit speed by reducing the capacitance by half. In addition, Loop-unrolled technology is used to convert multiple comparators. The action of the comparator is like the action of a domino. One level pushes one level, which can greatly reduce the reset time of the comparator. The comparator uses a dynamic comparator from the Two Stage to achieve lower power consumption. Because multiple comparators are used, the output of the comparison can be stored in the latch side of the comparator, so the number of the register can be greatly reduced compared to the single or more than two comparators. It can effectively reduce a part of core area.
The supply voltage is 1.2V, Vp-p is 1V, the maximum and minimum values of DNL and INL under the static performance are (0.244, -0.254), (0.545, -0.029); the input signal at Nyquist is Fin=173.63281250MHz, Sampling frequency Fs=350MHz Dynamic performance: SNDR is 48.303dB
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Huang, Ding-Ke, and 黃頂科. "The Design and Implementation of 1.8V 10-bits Successive Approximation Register Analog-to-Digital Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/56p9bu.
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碩士<br>國立虎尾科技大學<br>電機工程研究所<br>102<br>Typical signal processing need to convert analog signals into digital signals for analysis, so the design analog-to-digital converter is an extremely important part of the mixed-signal system. In this paper, use successive approximation register architecture to design circuits for excellent balance between the power consumption and conversion accuracy. The entire circuit consists of sample-and-hold circuit, comparator, digital-to-analog converter, clock generator, and successive approximation register. Sample-and-hold circuit using bootstraped switch to improve on-resistance and linearity. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC.
In this research, 10-bits 727kS/s SAR ADC under a single 1.8V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 38.73dB and SNDR of
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37.69dB. The peak DNL is -0.71LSB ~ 0.96 LSB, the peak INL is -1.22LSB ~ 1.49LSB, and the power dissipation is about 150.83μW, the layout area is 0.217135×0.26828mm2. The circuit architecture simulation results are compared with the conventional architecture, to verify the practicality and advantages of this technology, especially to reduce the overall chip area and power consumption.
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Chen, De-Chin, and 陳得勤. "The Design and Implementation of 1.2V 10-bits Successive Approximation Register Analog-to-Digital Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/ptc86k.
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碩士<br>國立虎尾科技大學<br>電機工程研究所<br>103<br>In mixed-signal circuit, converting analog signals to digital signal is needed for processing, so analog-to-digital converter has become an important interface circuits. Among various analog-to-digital converters, successive approximation register digital-to-analog converter consumes low power and had high resolution feature. As a result, successive approximation register architecture is adopted in this thesis. The SAR ADC includes sample-and-hold circuit, a comparator, digital to analog convertor, clock generator and successive approximation register; using bootstrap switches to improve on-resistance and linearity for sample-and-hold circuit. In the digital-to-analog convertor, we use four kind of ADC, conventional single-ended capacitive architecture, conventional differential capacitive architecture, combined dual sampling with conventional capacitive architecture and combined dual sampling with C-2C capacitive architecture, and compare the four kind of architecture, find the balance between the overall capacitance value, layout area and power consumption.
In this paper, implement a 10-bits combination dual sampling with C-2C capacitive digital-to-analog converter in TSMC 0.18μm CMOS 1P6M process. The power supply voltage is 1.2V, the sampling frequency is 727kHz, when the input signal frequency is 13.5KHz, the post-simulation of the SFDR and SNDR are 57.5dB and 56.3dB, the resolution is 9.06 bits, he peak DNL is -0.7 ~ 0.95 LSB, the peak INL is -1.22LSB ~ 1.49LSB, and the power dissipation is about 21.9μW, the layout area is 0.217 × 0.268mm2, The circuit architecture simulation results are compared with the traditional differential capacitive, this architecture reduces 82% chip area and 74% power consumption.
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Chang, Ting-Kai, and 張廷愷. "Design of High-Speed Energy-Efficient Successive-Approximation Register Analog-to-Digital Converters." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/39481166797197627137.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>102<br>This dissertation proposes two circuit design techniques for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-and-concept prototypes, the proposed techniques are able ti improve the operating speed and decrease total circuit power consumption. The proposed techniques and chip measurement results are sketched as follows:
The first technique is using charge-sharing method to achieve a Pipelined SAR ADC, this architecture using passive components capacitors for second stage sampling without using OP amplifiers, so the power consumption can be decreased greatly. A 9-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 20MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.33 bits, 7.27 bits, 6.92 bits and 6.57 bits. The ADC consumes 2.2mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 231fJ/conversion-step.
The second technique is adding a for reference to decrease the area of capacitor array, also we using the nature of capacitor that current will lagging the voltage, we make some change at switching, so we can achieve the target voltage without charge redistribution, we call this method “voltage-jumping” method. By using this method, we can not only decrease the capacitor array area by 50%, but also reduce the settling time of second bit. A 10-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.42 bits, 7.57 bits and 7.32 bits. The ADC consumes 1.6mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 100fJ/conversion-step.
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Chun-PoHuang and 黃俊博. "Design Automation and Error Analysis for Successive Approximation Register Analog-to-Digital Converters." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/97029127283683469361.
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博士<br>國立成功大學<br>電機工程學系<br>104<br>Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent energy efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also difficult to quickly evaluate the feasibility of realizing a SAR ADC for a given specification in a specified process node. This dissertation presents a systematic device sizing procedure for SAR ADCs based on designer experiences. A sizing tool based on the proposed design procedure is also implemented. Experimental results show that the generated SAR ADCs are highly competitive to many recently published works. Moreover, by employing the appropriate search algorithms according to the circuit characteristic, the sizing time is relatively short. In addition to the simulation results, three silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.
Besides, a comprehensive investigation on several important error sources for the SAR ADCs is also presented in this dissertation. The error sources investigated here include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential non-linearities (INL/DNL) of SAR ADCs those are resulted from these error sources are analyzed and addressed. A diagnosis procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also recommended in this dissertation.
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LAI, SHENG-YAN, and 賴勝彥. "A 1.2V 10-bit Low-Power Successive Approximation Register Analog-to-Digital Converter for Biomedical Systems." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/643y5b.
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碩士<br>國立虎尾科技大學<br>電機工程系碩士班<br>107<br>In this paper, a low-energy and area-efficient switching scheme is proposed to design a successive approximation register analog-to-digital converter (SAR ADC). SAR ADC includes sample-and-hold circuit, capacitive digital-to-analog converter(CDAC), control logic circuit, comparator, and register. The proposed CDAC switching energy is calculated by MATLAB. Compared with the conventional CDAC, the switching energy of the proposed CDAC is reduced by 97.66% and the total required capacitance is also reduced by 75%.
The 10-bits low-power SAR ADC has been designed using TSMC 0.18um 1P6M technology. At a 1.2V supply and the conversion rate of 100KS/s, when the input signal is 24.9KHz, the dynamic parameters SNDR and SFDR are 59.97dB and 63.9 dB, respectively. The ENOB is 9.67 bits. When the input signal is 24.4Hz, the static parameters DNL is between －0.32LSB and 0.36LSB, and the INL is between －0.23LSB and 0.25LSB. The overall circuit consumes 2.6μW, the layout area of core circuit is 0.382×0.332mm2, and the FOM is 32fJ/conversion-step. Therefore, the proposed SAR ADC is very suitable for low-power biomedical applications.
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An-ShengChao and 趙安生. "Design of Built-In Self-Test for Successive Approximation Register Analog-to-Digital Converters." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/42106699323555976497.
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博士<br>國立成功大學<br>電機工程學系<br>102<br>In this dissertation, we develop a built-in self-test (BIST) design for successive approximation register (SAR) analog-to-digital converters (ADCs) to accomplish the linearity tests, including the differential nonlinearity (DNL) and integral nonlinearity (INL).
The design for testability (DfT) circuit combines the embedded stimulus generator and the SAR ADC. The internal digital-to-analog converter (DAC) in the SAR ADC is controlled by digital patterns to generate the piecewise linear signal as the test stimulus. The embedded stimulus generator reuses the internal DAC, thus the hardware cost is alleviated. The DfT circuit occupied additional 12.4% area of the SAR ADC. The DfT circuit, the pattern generator (PG), and the output response analyzer (ORA) are combined as the BIST design.
Moreover, another test method is proposed to estimate the linearity without the test stimulus generator by quantifying the capacitance ratios in the internal DAC of the SAR ADC. Firstly, the pattern generator issues the digital pattern to set up a capacitance ratio in the capacitor array. The voltage difference across the capacitor arrays is proportional to the capacitance ratio and quantified by the proposed quantifying circuit, which is combined with the comparator in the SAR ADC. By applying the derived equations between capacitance ratios and the DNL, the linearity test results of the SAR ADC under test, including DNL and INL, are estimated in the BIST design.
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Chang, Kwuang-Han, and 張光漢. "Analog-to-Digital Conversion Algorithm, Methodology and Optimization, and High-Speed High-Resolution Successive Approximation Register Analog-to-Digital Convertors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/92e2s3.
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Hsieh, Yi-Jie, and 謝依潔. "A Process and Temperature Compensation Oscillator and A Successive-Approximation Register Analog to Digital Converter for Biomedical Systems." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/96185440314727933405.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>101<br>This thesis consists of two topics, i.e., a process and temperature compensation oscillator and a successive-approximation register analog to digital converter, which are mainly designed for biomedical system applications.
The first topic presents a process and temperature compensation oscillator for an implantable spinal cord stimulation system. This design is basically a ring-based oscillator, particularly including a temperature and process compensation circuit to provide a compensation bias voltage to stabilize the frequency such that the variations of the temperature and process can be reduced. To reduce the chip size, we use transistors and resistors to replace the conventional BJT as the temperature compensation component. The frequency variation verified on silicon is less than 3.07 % in the temperature range from 0 to 100 °C. This design is realized using TSMC 0.25 μm 60V HV BCD CMOS technology.
The second topic presents a successive-approximation register analog to digital converter (SAR ADC) for FPW-based antibody sensing systems. The input voltages are sampled by the sampling capacitors and compared by a comparator. Then, the comparison result will be transmitted to the following switch control logic. The capacitors in the array will charge or discharge the sampling capacitors based on the control signal generated by the switch control logic. The capacitor array is based on a charge sharing architecture, where a split capacitor array is used to reduce the size of the MSB capacitor. The proposed design is realized using TSMC 0.18 μm CMOS technology.
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TUNG, PO-CHIANG, and 董帛強. "A 12-bit 2-MS/s Successive Approximation Register Analog-to-Digital Converter with Dual-Cycle Switching and Redundancy." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bs74ku.
Full textAbstract:
碩士<br>國立中正大學<br>電機工程研究所<br>106<br>This thesis presents an energy-efficient 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) for high-resolution wireless sensor networks. With the proposed dual-cycle switching procedure, compared to converts that use the conventional procedure, the average switching energy is reduced by about 88.5%. The primary aim of this switching procedure is to provide redundancy by using two conversion cycles to convert 1 bit. Additionally, in order to reduce the DAC power consumption and to reduce the settling time, we proposed a new capacitor architecture. The parasitic resistance and capacitance at the top place are lowered and the ground noise is decreased.
At a 0.9-V supply voltage and a 2 MS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 58.349 dB and consumes 16.51μW. The effective number of bits (ENOB) is 9.4 bits. The peak DNL and INL are +0.74/-0.85 LSB and +1.31/-1.14 LSB, finally resulting in a figure of merit of 12.2 fJ/conversion-step. The implemented prototype in 40 nm CMOS process occupies an active area of 0.08 mm2.
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Hsu, Shih-Ying, and 許世穎. "A 10-bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with Charge-Pump Phase-Locked Loop." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/r868q2.
Full textAbstract:
碩士<br>國立臺北科技大學<br>電機工程系<br>106<br>This thesis presents a successive approximation register analog-to-digital converter (SAR ADC), which is fabricated in TSMC 0.25μm 1P3M CMOS high-voltage process for electric car. There are two chips were designed, in this thesis, the first chip(chip1) is a 10-bit 5MS/s SAR ADC; and the second chip(chip2) is the modified one, which is combined a charge-pump phase-locked loop and improved the chip1 sample and hold circuit and dynamic comparator. Two chips used a monotonic capacitor switching procedure to reduce power consumption.
A high-speed SAR ADC is hard to implement due to the TSMC 0.25μm CMOS is a high-voltage process, especially for integrating with motor control circuit. The TSMC 0.25μm CMOS high-voltage process lays the NBL (N-type buried layer) in the end for the withstand voltage. This layer leads to all of PMOS bodies to be shorted together. It is necessary to avoid from this negative impact, that the body is connected to source.
The measurements of chip1 show that, the SFDR, SNDR, ENOB, power consumption, and chip area are 62.2 dB, 53.82 dB, 8.65 bits, 855 μW, and 0.974×0.975 mm^2, respectively; and that the post simulation of chip2 show that, the SFDR, SNDR, ENOB, power consumption, and chip area are 75.92 dB, 58.23 dB, 9.38 bits, 1256 μW, and 1.261×0.975 mm^2, respectively.
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Yu-HaoChiu and 裘愉豪. "An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/05453079061978941158.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系<br>103<br>Analog-to-digital converters (ADCs) play an important role in audio system. Successive approximate register ADC (SAR ADC) is a low cost, low power consumption, medium speed ADC which is widely used in audio system.
This study proposed on chip calibration to implement 1.5 bits/stage chip design with time-to-digital converter (TDC). There will be a 25% chance that the capacitor array will not switch with random input signals. Therefore, the switching energy can be lower. By combining the monotonic switching, it will efficiently reduce the power consumption. Additionally, we add the asynchronous clock technique for lower our system clock 15 times.
For implementation, we have been tape-out in TSMC’s 90nm process via Chip Implementation Center (CIC). The chip area is 0.28*0.29 mm2, the power dissipation is 1.215uW, the operation frequency is 100 kHz and ENOB is 11.16.
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Lyu, Yuan-Fu, and 呂元復. "A Low Power 10-Bit 500-KS/s Delta-Modulated Successive Approximation Register Analog-to-Digital Converter for Implantable Medical Devices." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/80086516522557983915.
Full textAbstract:
碩士<br>國立交通大學<br>電子研究所<br>100<br>For reducing outside noise in the applications of detection and stimulation of epilepsy, implantable epileptic devices require low power consumption. ADC is a power-hungry device in whole system. Delta-modulated SAR ADC using successive approximation register is power-efficiency than the other architectures, but conventional SAR ADC solving n-bit code form MSB to LSB is non-efficient. This work is proposed to modulate input signal and predicts the range to reduce redundant steps. Using the difference between the previously solved code and sampled input signal as input signal of ADC increases the hit rate of prediction, because in the same channel, the delta value between two successive samples is considerably small. Prof. F. Shaw and coworkers use external instruments to detect ECoG of Long-Evens rats. When epileptic seizure happened, the amplified voltage can reach above 2V. However, the delta value interpolated by 500kHz is less than 3mV. Since signal frequency of most of the bio-potential signals is in the range between 0.5Hz and 2KHz. Multi-channel design can simultaneously detect localized variations. Measured results of proposed delta-modulated SAR ADC show the total power consumption is 2.95μW, SNDR of 59.375dB, and ENOB of 9.57 at Fin=100Hz with supply voltage of 1.8V.
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Chen, Yi-Ting, and 陳奕廷. "A 10-bit 100MS/s 1.58mW Successive-Approximation Register Analog-to-Digital Converters in 90 nm CMOS Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/vz9c86.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>This thesis proposes a high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). The dual path fast-switching and asynchronous resetting method effectively improve the operating speed of SAR ADC. Following shows the proposed methods and measurement results.
A 10-bit 100MS/s 1.58mW SAR ADC with the novel methods is implemented in TSMC 90nm CMOS technology. The dual path fast-switching method shortens the decision time and dramatically improves operating speed of the ADC. The asynchronous resetting method clears the unnecessary charges on capacitors as soon as possible. In measurement results, when the SAR ADC operates at 10MS/s sampling rate with Nyquist-rate input frequency, the measured ENOB and SFDR is 9.13 and 75.50dB. At 20MS/s sampling rate with Nyquist-rate input frequency, the measured ENOB and SFDR is 9.01 and 69.84dB. At 50MS/s sampling rate with 2MHz input frequency, the measured ENOB and SFDR is 8.40 and 66.68dB. With 20MHz input frequency, the measured ENOB and SFDR is 8.25 and 66.39dB. At 100MS/s sampling rate with 2MHz input frequency, the measured ENOB is 8.20 and SFDR is 59.36dB. The ADC consumes 1.58mW from 1-V supply when the sampling rate is 100MS/s, the resulting figure of merit (FOM) is 51fJ/conversion-step at 2MHz input frequency, and 99fJ/conversion-step at 50MHz input frequency.
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Chen, Yan-Lin, and 陳彥霖. "A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/9revbt.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>107<br>In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18m process technology. This circuit primary is implemented for the CMOS Image Sensor.
In the circuit design, the input source of the analog-to-digital converter is determined by the output of the correlated double sampling or programmable gain amplifier, and both inputs are already sampled. Hence, it is different from the other analog digital converters. The sample and hold circuits can be not required in this cirucit. In combing with the fine step SAR and the coarse step single-slope modes, the edge images can be generated to adjust the sharpness of the image. By using 7 cycles in the capacitance switchig, the 10-bit conversion can effectively reduce the power consumption and increase the conversion efficiency. Because the input has two different signals to be chosen, this circuit also provides two modes of high resolution and low resolution. In the low resolution mode, the shortend and unused circuits also can reduce the power consumption.
In this thesis, a 10-bit, 10 MS/s analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18 m process technology. The INL and DNL need to be less than 1 and the power consumption should be less than 3mW.
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Chen, Guan-Ting, and 陳冠廷. "A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/x96ub8.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>106<br>In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed, the 2b/cycle conversion is adapted in the conversion of the upper bits. Since three comparators are required to perform the 2b/cycle conversion, it may cause the increase of the error probability. Therefore, the proposed architecture adapts the non-binary correction technique in the upper bits to tolerate fault error and hence correct the error. In the lower bit conversion, a 1b/cycle conversion is implmented to increase the accuracy. Moreover, the architecture also adopted the alternate technique in lower bit conversion to improve the conversion efficiency. This technique not only uses the comparators more efficiently, but also relaxing the issue of the longer comparison time in the lower bit conversions. At last, a redundant bit is added in the lower bits to increase the fault tolerance capability of the lower bits.
This thesis implements a 10-bit analog-to-digital converter with 100MHz sampling frequency by using the TSMC 90nm process technology. For the static analysis, the DNL and INL are +1.248 / -0.750 LSB and +1.679 / -1.677 LSB, respectively. For the dynamic analysis, the SFDR and SNDR at the Nyquist rate are 62.76 dB and 56.099 dB. The ENOB is 9.026 bit, the power consumption is 2.397 mW and FoM is 45.98 fJ / conv.-step.
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YANG, JYUN-JIE, and 楊竣傑. "A Interdigitater Extended CMOS-MEMS Capacitive Sensing System with Bypass Successive Approximation Register Capacitance to Digital Converter Readout." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t79443.
Full textAbstract:
碩士<br>國立中正大學<br>電機工程研究所<br>107<br>A pressure sensing system consisting of the MEMS pressure sensor and the readout circuits on a single chip by CMOS MEMS technology is presented. In-house wet etching post process is used to release the MEMS structure. Pressure signal is converted into capacitance value by the proposed on-chip MEMS capacitive sensor then digitized by an Bypass Successive-Approximation-Register Capacitance to Digital Converter(Bypass SAR CDC) .Parasitic capacitance, noise and area of sensing system is greatly reduced by the integration of capacitive sensor and CDC on a single chip.
The proposed Bypass SAR CDC is composed of a Interdigitater Extended CMOS MEMS Pressure Sensor, a Bypass Comparator and Bypass Control Logic; The sensor parallel plate capacitance structure is combined with interdigitated structure to increase the unit capacitance value, and increase the sensitivity of the sensor using an extended architecture. Place this sensor on a capacitor array in the Bypass SAR CDC. Hence, when the sensing capacitance changes, it will produce voltage drift. Then the system will track the voltage drift and generate output digital codes. In addition, Bypass SAR CDC can automatically adjust the power according to the ICP input signal size to achive power optimization performance. The sensitivity and sensing range of MEMS capacitive sensor are 53.25 pF/Mpa and 0-40kPa, respectively. The prototype chip is fabricated using the UMC 0.18μm 1P6M CMOS technology with an area of 1.5*1.5〖mm〗^2, 0.9μW/1.62μW(Bypass/no Bypass) power consumption and FoM 0.1 7pJ/step (Bypass) 0.307 pJ/step (no Bypass).
Keywords: MEMS, capacitive sensor, sensor readout, Bypass SAR CDC
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Hou, Jhih-Pian, and 侯志平. "The Design of a Fully Differential Bypass Window Successive Approximation Register Analog to Digital Converter and an Electrode-Tissue Impedance Measurement Circuit for Cochlear Implants." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/bh7d2x.
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Pereira, Nuno Ruben Ferreira. "Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers." Doctoral thesis, 2019. http://hdl.handle.net/10362/91170.
Full textAbstract:
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiver’s performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of “pre-charging” the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 μm CMOS technology validate the proposed technique.
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Yang, Jiao. "Design of a low power 8-bit A/D converter for wireless neural recorder applications." Thesis, 2017. https://hdl.handle.net/2144/23685.
Full textAbstract:
Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/D converter, ADC) is the key component in a neural recorder chip.
This thesis proposes the complete design of a low power 8-bit successive approximation register (SAR) A/D converter for use in a wireless neural recorder chip, realizing the function of digitizing a sampled neural signal with a frequency distribution of 10Hz to 10kHz. A modified energy-saving capacitor array in the SAR structure is provided to help save power dissipation. Therefore, the ADC shall operate within a power budget of 20μW maximum from a 1V power source, at a clock frequency of 500kHz corresponding to a conversion rate of 55.5-kS/s. All the circuits are designed and implemented based on the IBM/Global Foundries 8HP 130nm BiCMOS technology. Simulations of schematic and layout versions are done respectively to verify the functionality, linearity and power consumption of the ADC.
Key words: Successive approximation register analog-to-digital converter (SAR-ADC), low power design, energy-saving capacitor array, neural recorder applications
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Fitas, Ricardo Jorge Barros. "Study of a Time Assisted SAR ADC." Master's thesis, 2017. http://hdl.handle.net/10362/30820.
Full textAbstract:
The demand for low power systems has been increasing in recent years and Analogto-
Digital Converters (ADCs) are key blocks of many of these systems as they convert a
physical quantity into the digital domain so that this information can be further processed or stored using digital techniques.
Data Converters based on Charge Redistribution using of Successive Approximation
Registers (SAR) are becoming one of the most popular ADC architectures for moderate
speed, medium resolution and low power applications. Due to their low analog complexity SAR ADCs benefit from technology scaling. However, this scaling often comes with a supply voltage reduction and the noise levels do not decrease at the same rate, which translates into a performance decrease. Therefore, new opportunities emerge to explore other physical quantities such as time, frequency, phase or charge in the circuit.
This thesis focuses on studying how the time domain information can be used to
increase the performance of SAR ADCs. To do so, a new SAR ADC architecture is proposed in which a Time-to-Digital Converter (TDC) is used to convert the time domain information, provided by the comparator, into the digital domain. This new architecture was modelled in MATLAB as a 12 bit TDC assisted SAR ADC, using information from electrical simulations of the comparator and the TDC, designed in Cadence in 65 nm ST Microelectronics CMOS technology.
Simulation results demonstrated that, to achieve a better performance when compared
to more traditional SAR structures, the TDC energy and latency should be minimized.
Another limiting factor was the large voltage range in which only 1 bit could be extracted from the time-to-voltage conversion by the TDC due to the comparator’s fast response in this range. The proposed architecture was also extended to incorporate a Bypass Window in the time domain, which allowed to substantially decrease the number of clock cycles necessary to solve the 12 bits of the ADC.
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Omran, Hesham. "Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes." Diss., 2015. http://hdl.handle.net/10754/582481.
Full textAbstract:
Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants,
and wearable devices. The energy consumption of the sensor node needs to
be minimized to avoid battery replacement, or even better, to enable the device to
survive on energy harvested from the ambient. Capacitive sensors do not consume
static power; thus, they are attractive from an energy efficiency perspective. In addition,
they can be employed in a wide range of sensing applications. However, the
sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the
dominant source of energy consumption in the system. Thus, the development of
energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive
sensor nodes.
In the first part of this dissertation, we propose several energy-efficient CDC architectures
for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine
multislope CDC that employs both current and frequency scaling to achieve
significant improvement in energy efficiency. Second, we analyze the limitations of
successive approximation (SAR) CDC, and we address these limitations by proposing
a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an
inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM)
of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent
energy efficiency for a scalable sample rate.
In the second part of this dissertation, we study the matching properties of small
integrated capacitors, which are an integral component of energy-efficient CDCs. Despite
conventional wisdom, we experimentally illustrate that the mismatch of small
capacitors can be directly measured, and we report mismatch measurements for subfemtofarad
integrated capacitors. We also correct the common misconception that
lateral capacitors match better than vertical capacitors, and we identify the conditions
that make one implementation preferable.
In the third and last part of this dissertation, we investigate the potential of novel
metal-organic framework (MOF) thin films in capacitive gas sensing. We provide
sensitivity-based optimization and simple fabrication flow for capacitive interdigitated
electrodes. We use a custom flexible gas sensor test setup that is designed and built
in-house to characterize MOF-based capacitive gas sensors.