Journal articles: 'Successive Approximation Register Analog-to- Digital Converter'

1

Cao, Chao, and Haijun Guo. "High-resolution calibrated successive-approximation-register analog-to-digital converter." Integration 87 (November 2022): 205–10. http://dx.doi.org/10.1016/j.vlsi.2022.08.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Cao, Chao, and Haijun Guo. "High-resolution calibrated successive-approximation-register analog-to-digital converter." Integration 87 (November 2022): 205–10. http://dx.doi.org/10.1016/j.vlsi.2022.08.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

Full text

Abstract:

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

APA, Harvard, Vancouver, ISO, and other styles

4

Du, Ling, Ning Ning, Shuangyi Wu, Qi Yu, and Yang Liu. "A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter." Journal of Computer and Communications 01, no. 06 (2013): 30–36. http://dx.doi.org/10.4236/jcc.2013.16006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

Full text

Abstract:

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

APA, Harvard, Vancouver, ISO, and other styles

6

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

Full text

Abstract:

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

APA, Harvard, Vancouver, ISO, and other styles

7

Zhu, Donglin, Maliang Liu, and Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 01 (2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.

Full text

Abstract:

In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.

APA, Harvard, Vancouver, ISO, and other styles

8

Pham, Duy Phong, Thanh Pham Xuan, Nguyen Thi Viet Ha, and Manh Kha Hoang. "Designing and simulation a 15-bit successive approximation register analog-to-digital converter." Journal of Military Science and Technology 87 (May 25, 2023): 1–8. http://dx.doi.org/10.54939/1859-1043.j.mst.87.2023.1-8.

Full text

Abstract:

Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.

APA, Harvard, Vancouver, ISO, and other styles

9

R, Yashaswini, and Kumar N. Krishna Murthy. "Design and Simulation of 16 Bit ADC." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 1017–24. http://dx.doi.org/10.22214/ijraset.2023.54790.

Full text

Abstract:

Abstract: In this study, it was looked into how a 16-bit architecture might be used to develop an Analog-to-Digital Converter (ADC) Successive Approximation Register (SAR). The SAR ADC architecture is widely adopted for high-resolution applications because to its ease of use and minimal power requirements. The design also includes a voltage reference, a comparator, a successive approximation register, a sample-and-hold circuit, an analog-to-digital converter (DAC), and other components. A range of design approaches and circuit topologies are employed to maximize performance and satisfy the required criteria. The comparator is intended to properly detect the analogue input voltage and operate at high speeds. A binary search technique is used by the successive approximation register to find the input voltage's digital representation. The design is implemented using 250nm Gate Diffusion Input [GDI] Technology. Simulation and verification are performed using Tanner EDA tool. The results indicate that the proposed 16-bit SAR ADC achieves the desired resolution and meets the specified performance requirements. The ADC exhibits low power consumption, and satisfactory performance. This architecture its applications span across multiple disciplines, encompassing communication systems, scientific instrumentation, and medical imaging, where there is a requirement for accurate ADC conversion.

APA, Harvard, Vancouver, ISO, and other styles

10

Zghoul, Fadi Nessir, Yousra Hussein Al-Bakrawi, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 3830. http://dx.doi.org/10.11591/ijece.v14i4.pp3830-3854.

Full text

Abstract:

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

APA, Harvard, Vancouver, ISO, and other styles

11

Nessir, Zghoul Fadi, Al-Bakrawi Yousra Hussein, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology 14, no. 4 (2024): 3830–54. https://doi.org/10.11591/ijece.v14i4.pp3830-3854.

Full text

Abstract:

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

APA, Harvard, Vancouver, ISO, and other styles

12

Lin, Chih-Hsuan, and Kuei-Ann Wen. "An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System." Journal of Low Power Electronics and Applications 11, no. 1 (2021): 3. http://dx.doi.org/10.3390/jlpea11010003.

Full text

Abstract:

With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.

APA, Harvard, Vancouver, ISO, and other styles

13

Lin, Chih-Hsuan, and Kuei-Ann Wen. "An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System." Journal of Low Power Electronics and Applications 11, no. 1 (2021): 3. http://dx.doi.org/10.3390/jlpea11010003.

Full text

Abstract:

With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.

APA, Harvard, Vancouver, ISO, and other styles

14

Chavhan, Sarvesh S., and K. M. Bogawar. "Energy Efficient Quaternary Capacitive DAC Switching Scheme for SAR -ADC." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 2, no. 6 (2015): 13–16. http://dx.doi.org/10.53555/nneee.v2i6.191.

Full text

Abstract:

This paper presents energy efficient 4-bit successive approximation register analog to digital converter (SAR-ADC) for neural recording front end interface of neural prosthetic system(Brain machine interface). The energy efficient quaternary capacitive switching scheme (QCS) in the implementation of capacitive digital to analog converter (C-DAC) is employed which makes the energy consumption in the C-DAC independent of the output digital code. The proposed quaternary capacitive technique in C-DAC achieves a 50% reduction in the average energy consumption. The design is implemented in 0.25um standard complementary metal-oxide semiconductor technology (CMOS).

APA, Harvard, Vancouver, ISO, and other styles

15

An, Sheng-Biao, Li-Xin Zhao, Shi-Cong Yang, Tao An, and Rui-Xia Yang. "Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique." Journal of Nanoelectronics and Optoelectronics 15, no. 4 (2020): 478–86. http://dx.doi.org/10.1166/jno.2020.2782.

Full text

Abstract:

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

APA, Harvard, Vancouver, ISO, and other styles

16

Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

Full text

Abstract:

Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

APA, Harvard, Vancouver, ISO, and other styles

17

HUANG, Jhin-Fang, Wen-Cheng LAI, and Cheng-Gu HSIEH. "A 10-bit 100 MS/s Successive Approximation Register Analog-To-Digital Converter Design." IEICE Transactions on Electronics E97.C, no. 8 (2014): 833–36. http://dx.doi.org/10.1587/transele.e97.c.833.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Park, Joonsung, Jiwon Lee, Jacob A. Abraham, and Byoungho Kim. "A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter." Electronics 13, no. 4 (2024): 755. http://dx.doi.org/10.3390/electronics13040755.

Full text

Abstract:

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively.

APA, Harvard, Vancouver, ISO, and other styles

19

Kobayashi, Yutaro, and Haruo Kobayashi. "Redundant SAR ADC Algorithm Based on Fibonacci Sequence." Key Engineering Materials 698 (July 2016): 118–26. http://dx.doi.org/10.4028/www.scientific.net/kem.698.118.

Full text

Abstract:

This paper describes a redundant Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design method which enables high-reliability and high-speed AD conversion by using digital error correction. Especially we introduce to apply Fibonacci sequence and its property called Golden ratio to SAR ADC design to improve conventional redundant search algorithms. We also present some derived equations and many beautiful properties for well-balanced redundancy design for SAR ADC

APA, Harvard, Vancouver, ISO, and other styles

20

Momeni, Mahdi, and Mohammad Yavari. "Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area." International Journal of Circuit Theory and Applications 48, no. 11 (2020): 1873–86. http://dx.doi.org/10.1002/cta.2852.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Fuente-Cortes, Gisela De La, Guillermo Espinosa Flores-Verdad, Alejandro Díaz-Méndez, and Victor R. Gonzalez-Diaz. "A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance." Electronics 13, no. 14 (2024): 2756. http://dx.doi.org/10.3390/electronics13142756.

Full text

Abstract:

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

APA, Harvard, Vancouver, ISO, and other styles

22

Adsul, Jayamala, and Harsh Sawardekar. "Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 13, no. 02 (2021): 93–97. http://dx.doi.org/10.18090/samriddhi.v13i02.6.

Full text

Abstract:

The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-bit + 8-bit) resolution in pipeline mode with optimum conversion time and 16-bit (8-bit + 8-bit) resolution in sub ranging mode with more conversion time using exsisting components. This proposed ADC behaves as 8-bit SAR ADC, 16-bit (8-bit + 8-bit) two stage SAR-Assisted pipeline ADC and 16-bit (8-bit + 8-bit) two step sub-ranging ADC. The reconfigurability is obtained using control signals. This circuit has been designed and simulated in NI Multisim 14.0, and the results are presented in the paper.

APA, Harvard, Vancouver, ISO, and other styles

23

Laoudias, Costas, George Souliotis, and Fotis Plessas. "A High ENOB 14-Bit ADC without Calibration." Electronics 13, no. 3 (2024): 570. http://dx.doi.org/10.3390/electronics13030570.

Full text

Abstract:

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

APA, Harvard, Vancouver, ISO, and other styles

24

Zhao, Yi-qiang, Ming Yang, and Hong-liang Zhao. "A cryogenic 10-bit successive approximation register analog-to-digital converter design with modified device model." Journal of Shanghai Jiaotong University (Science) 18, no. 5 (2013): 520–25. http://dx.doi.org/10.1007/s12204-013-1436-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Jagadish, D. N., and M. S. Bhat. "Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter." Journal of Low Power Electronics 11, no. 3 (2015): 436–43. http://dx.doi.org/10.1166/jolpe.2015.1389.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

He, Xinyuan, Weifeng Qiao, Xinpeng Xing та Haigang Feng. "A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor". Journal of Low Power Electronics and Applications 14, № 2 (2024): 32. http://dx.doi.org/10.3390/jlpea14020032.

Full text

Abstract:

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

APA, Harvard, Vancouver, ISO, and other styles

27

Li, Shouping, Yang Guo, Jianjun Chen, and Bin Liang. "A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm." Symmetry 12, no. 1 (2020): 165. http://dx.doi.org/10.3390/sym12010165.

Full text

Abstract:

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

APA, Harvard, Vancouver, ISO, and other styles

28

SARAFI, SAHAR, KHEYROLLAH HADIDI, EBRAHIM ABBASPOUR, ABU KHARI BIN AAIN, and JAVAD ABBASZADEH. "100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION." Journal of Circuits, Systems and Computers 23, no. 05 (2014): 1450057. http://dx.doi.org/10.1142/s0218126614500571.

Full text

Abstract:

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

APA, Harvard, Vancouver, ISO, and other styles

29

Jia, Shichao, Tianchun Ye, and Shimao Xiao. "Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain." Electronics 13, no. 17 (2024): 3400. http://dx.doi.org/10.3390/electronics13173400.

Full text

Abstract:

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented.

APA, Harvard, Vancouver, ISO, and other styles

30

Lee, Hyun-Yeop, Jin-Seop Lee, Chang-Kyun Noh, et al. "Low-Power Switching Scheme with Quarter Reference Voltage Sources for SAR ADCs." Journal of Electromagnetic Engineering and Science 22, no. 2 (2022): 129–37. http://dx.doi.org/10.26866/jees.2022.2.r.69.

Full text

Abstract:

In this paper, an energy-efficient switching scheme with additional quarter-reference voltage sources in a successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for a low power and small area device for frequency modulated continuous wave (FMCW) radar transceivers. Recently, state-of-the-art ADCs have adopted a configuration that also uses Vref/2 as the reference voltage of the ADCs to improve the switching energy of capacitive digital-to-analog converter (CDAC). The proposed switching configuration additionally uses Vref/4 and 3Vref/4 reference voltages as the reference voltage of CDAC. Compared to state-of-the-art configurations that use the additional reference voltage of Vref/2, the average switching energy, and the total capacitance of CDAC in the proposed configuration are reduced by about 87.5% and 50%, respectively. In this switching scheme, the CDAC output voltage gradually converges to Vref/2, like with conventional SAR ADCs, which minimizes the dynamic offset that deteriorates the linearity of the SAR ADC.

APA, Harvard, Vancouver, ISO, and other styles

31

Siti, Idzura Yusuf, Shafie Suhaidi, Abdul Majid Hasmayadi, and Abdul Halin Izhal. "Differential input range driver for SAR ADC measurement setup." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 17, no. 2 (2020): 750–58. https://doi.org/10.11591/ijeecs.v17.i2.pp750-758.

Full text

Abstract:

Differential successive approximation register (SAR) of analog to digital converter (ADC) requires two balancing input signals that have same amplitude with 180⁰ out of phase. Otherwise, it performs inaccurately and degrades the performance during ADC testing procedure. Therefore, an implementation of AD8139 chip single to differential amplifier was chosen as an ADC driver to generate sufficient differential output for the ADC. The chip was placed on a printed circuit board (PCB) to test the functionality as well as the performance of static and dynamic SAR ADC. The result shows that the single-ended input transform into differential voltage outputs. The amplitudes for the amplifier remain equal and is 180° out of phase for DC and AC voltage input signal. Besides, the fabricated 0.18µm CMOS technology of differential 10-bit SAR ADC is capable of digitising full code digital output and perform 9.5-bit effective number of bit (ENOB) from analog input driving by the ADC driver.

APA, Harvard, Vancouver, ISO, and other styles

32

Melnychuk, S. I., M. H. Tarnovskyi, and O. H. Murashchenko. "ANALYSIS OF THE ARCHITECTURE OF SUCCESSIVE APPROXIMATION REGISTER ADC AND APPROACHES TO ITS IMPROVEMENT." Information technology and computer engineering 57, no. 2 (2023): 4–12. http://dx.doi.org/10.31649/1999-9941-2023-57-2-4-12.

Full text

Abstract:

Successive approximation register analog-digital converters (SAR ADC) represent the majority of the ADC market for medium- to high-resolution ADCs. Modern SAR ADCs allow to ensure a sampling frequency of more than 100 MHz with a resolution of 10 to 12 bits. Features of the ADC architecture of this type: simplicity, high energy efficiency and dependency of conversion time from resolution. The two main components of a SAR ADC that affect its basic characteristics are the comparator and the digital-to-analog converter (DAC). The DAC based on a capacitor matrix is most often used. In practice, when implementing an ADC in an integrated view, when increasing the resolution, the natural increase of the chip area crystals, increase of the energy, which is consumed during the transformation, and decrease in productivity is intensified by number of technical and technological factors The work analyzes a number of modern approaches that are used to improve the characteristics of the SAR ADC in increased resolution. In particular, the segmentation of the DAC capacitor matrix or the division of the capacitor matrix into a matrix of binary weighted capacitors and a matrix of C-2C capacitors allows to reduce the range of required values of capacitor capacities and reduce the total capacity of the matrix. Due to this, in comparison with the basic architecture, when the ADC bit rate is increased, a smaller area on the crystal is required for the implementation of the matrix and higher performance is ensured. Replacing the capacitor of the most significant discharge of the matrix with an exact copy of its other part allows to reduce the energy consumed from the reference voltage source and spent on redistributing the charge between the capacitors of the matrix during conversion.

APA, Harvard, Vancouver, ISO, and other styles

33

Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

Full text

Abstract:

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

APA, Harvard, Vancouver, ISO, and other styles

34

Fahmy, Ghazal A., and Mohamed Zorkany. "Design of a Memristor-Based Digital to Analog Converter (DAC)." Electronics 10, no. 5 (2021): 622. http://dx.doi.org/10.3390/electronics10050622.

Full text

Abstract:

A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

APA, Harvard, Vancouver, ISO, and other styles

35

Huang, Jhin-Fang, Jin-Yu Wen, and Cheng-Ku Hsieh. "An 8-bit 20 MS/s Successive Approximation Register Analog-to-digital Converter with Low Input Capacitance." International Journal of Engineering Practical Research 3, no. 4 (2014): 83. http://dx.doi.org/10.14355/ijepr.2014.0304.04.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Bai, Suping, Zhi Wan, Peiyuan Wan, et al. "A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC." Electronics 10, no. 21 (2021): 2650. http://dx.doi.org/10.3390/electronics10212650.

Full text

Abstract:

This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm2. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.

APA, Harvard, Vancouver, ISO, and other styles

37

Liu, Wenbo, Pingli Huang, and Yun Chiu. "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration." IEEE Journal of Solid-State Circuits 46, no. 11 (2011): 2661–72. http://dx.doi.org/10.1109/jssc.2011.2163556.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Malandruccolo, Vezio, Mauro Ciappa, Hubert Rothleitner, M. Hommel, and Wolfgang Fichtner. "A new built-in screening methodology for Successive Approximation Register Analog to Digital Converters." Microelectronics Reliability 50, no. 9-11 (2010): 1750–57. http://dx.doi.org/10.1016/j.microrel.2010.07.096.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Liu, Shubin, Haolin Han, and Ruixue Ding. "Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC." Journal of Circuits, Systems and Computers 28, no. 13 (2019): 1930010. http://dx.doi.org/10.1142/s0218126619300101.

Full text

Abstract:

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

APA, Harvard, Vancouver, ISO, and other styles

40

Li, Nan, Xinyuan He, and Xinpeng Xing. "A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS." Journal of Physics: Conference Series 2613, no. 1 (2023): 012021. http://dx.doi.org/10.1088/1742-6596/2613/1/012021.

Full text

Abstract:

Abstract A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

APA, Harvard, Vancouver, ISO, and other styles

41

Bontems, W., and D. Dzahini. "Design of a very low power 12 bits, 40 MS/s ADC based on a time-interleaved SAR architecture." Journal of Instrumentation 19, no. 05 (2024): C05033. http://dx.doi.org/10.1088/1748-0221/19/05/c05033.

Full text

Abstract:

Abstract The paper describes a new figure of merit reachable in terms of very low power dissipation for a 12 bit, 40 MS/s Analog to Digital Converter in a 65 nm CMOS process with 1 V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized with regard to power consumption hence interleaving 28 ADC channels in an analog memory like method, the total power consumption is only 280 μW including all the reference voltage drivers, the clock management and the digital sections. The total layout area of this converter is 0.87 mm2.

APA, Harvard, Vancouver, ISO, and other styles

42

Wang, Jiaqi. "A 10-bit 160 MS/s Asynchronous SAR ADC design." Journal of Physics: Conference Series 2645, no. 1 (2023): 012001. http://dx.doi.org/10.1088/1742-6596/2645/1/012001.

Full text

Abstract:

Abstract This study describes a 10-bit 160 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) design in a 40 nm CMOS technical process. The SAR ADC is provided with an improved capacitive digital-to-analog converter (CDAC), and the capacitor array is featured by six split high-bit capacitors and a combination of splitting and monotonic switching schemes. This structure and switching scheme can both save power and improve speed while introducing negligible common-mode voltage change. An improved double-tail comparator and TSPC D flip-flops are implemented to further enhance the speed. Simulation results show that the ADC achieves SFDR 72.17 dB, SNDR 61.37 dB, and ENOB 9.90 bits at Nyquist input frequency. The power consumption of the ADC under a 1.2 V power supply is 2.808 mW, achieving 18.4 fJ/conv FoM.

APA, Harvard, Vancouver, ISO, and other styles

43

Arzate-Palma, Victor H., David G. Rivera-Orozco, Gerardo Molina Salgado, and Federico Sandoval-Ibarra. "A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations." Chips 3, no. 2 (2024): 153–81. http://dx.doi.org/10.3390/chips3020007.

Full text

Abstract:

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

APA, Harvard, Vancouver, ISO, and other styles

44

Sun, Lei, Chi Tung Ko, Marco Ho, et al. "23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme." Journal of Engineering 2014, no. 8 (2014): 420–25. http://dx.doi.org/10.1049/joe.2014.0137.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Silpa, Kesav Velagaleti, K. S. Nayanathara, and B. K. Madhavi. "A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 2 (2021): pp. 547~555. https://doi.org/10.12928/TELKOMNIKA.v19i2.18318.

Full text

Abstract:

In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration.

APA, Harvard, Vancouver, ISO, and other styles

46

Ro, Duckhoon, Minseong Um, and Hyung-Min Lee. "A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems." Sensors 21, no. 14 (2021): 4768. http://dx.doi.org/10.3390/s21144768.

Full text

Abstract:

For a reliable and stable sensor system, it is essential to precisely measure various sensor signals, such as electromagnetic field, pressure, and temperature. The measured analog signal is converted into digital bits through the sensor readout system. However, in extreme radiation environments, such as in space, during flights, and in nuclear fusion reactors, the performance of the analog-to-digital converter (ADC) constituting the sensor readout system can be degraded due to soft errors caused by radiation effects, leading to system malfunction. This paper proposes a soft-error-tolerant successive-approximation-register (SAR) ADC using dual-capacitor sample-and-hold (S/H) control, which has robust characteristics against total ionizing dose (TID) and single event effects (SEE). The proposed ADC was fabricated using 65-nm CMOS process, and its soft-error-tolerant performance was measured in radiation environments. Additionally, the proposed circuit techniques were verified by utilizing a radiation simulator CAD tool.

APA, Harvard, Vancouver, ISO, and other styles

47

Jyoti, Sehgal, and Kumar Manoj. "12-Bit Clock Gated SAR-ADC for Bio-Medical Applications." Indian Journal of Science and Technology 15, no. 34 (2022): 1648–54. https://doi.org/10.17485/IJST/v15i34.1033.

Full text

Abstract:

Abstract Background/Objectives: Power optimization is a critical design criterion in modern integrated circuits. The unwanted clock signals are neutralized and the reduction in power consumption is made presumable by using the clock gating technique. Methods: Analog-to-digital converters (ADCs) are important components in these systems. A widely used successive approximation register A/D converter includes an internal clock, reference, and high resolution. The number of redundant cycles is increased with improved resolutions but enhances the consumption of power. Thus, the clock gating strategy is used to substantially lower the circuit’s dynamic power consumption. The clock gating technique is implemented with a reduced number of transistors to minimize the overhead with high switching activity. Also, demonstrate no imperfection on the clock duty cycle. Findings: A 12-bit clock gated SAR register using a D-flip flop with 1.8 V supply voltage is proposed in this study for efficient biomedical applications. SAR without a clock gating technique consumes 54 mW of power and SAR with a clock gating technique consumes a power of 22.68 mW. Novelty: The clock gating technique is stipulated to minimize power consumption of clock gated SAR-ADC and improves the battery life of the portable device. Keywords: Clock gated technique; power consumption; resolution; SARADC; successive approximation register

APA, Harvard, Vancouver, ISO, and other styles

48

Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, and Jong-Kee Kwon. "A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 7 (2010): 502–6. http://dx.doi.org/10.1109/tcsii.2010.2048387.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Chi, Yingying, and Dongmei Li. "A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration." Journal of Semiconductors 34, no. 4 (2013): 045007. http://dx.doi.org/10.1088/1674-4926/34/4/045007.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Villa, Jorge, José I. Artigas, Luis A. Barragán, and Denis Navarro. "An Amplifier-Less Acquisition Chain for Power Measurements in Series Resonant Inverters." Sensors 19, no. 19 (2019): 4343. http://dx.doi.org/10.3390/s19194343.

Full text

Abstract:

Successive approximation register (SAR) analog-to-digital converter (ADC) manufacturers recommend the use of a driver amplifier to achieve the best performance. When a driver amplifier is not used, the conversion speed is severely penalized because of the need to meet the settling time constraint. This paper proposes a simple digital correction method to raise the performance (conversion speed and/or accuracy) when the acquisition chain lacks a driver amplifier. It is intended to reduce the cost, size and power consumption of the conditioning circuit while maintaining acceptable performance. The method is applied to the measurement of the output power delivered by a series resonant inverter for domestic induction heating.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Successive Approximation Register Analog-to- Digital Converter'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles