Journal articles: 'Successive approximation register converters'

1

Rossi, A., and G. Fucili. "Nonredundant successive approximation register for A/D converters." Electronics Letters 32, no. 12 (1996): 1055. http://dx.doi.org/10.1049/el:19961113.

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Park, Himchan, Qiwei Huang, Changzhi Yu, Seulki Kim, Gilcho Ahn, and Jinwook Burm. "Two CMOS time to digital converters using successive approximation register logic." IEICE Electronics Express 15, no. 22 (2018): 20180840. http://dx.doi.org/10.1587/elex.15.20180840.

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Chiang, Shiuh‐hua Wood. "Charge‐dumping switching scheme for successive‐approximation‐register analogue‐to‐digital converters." Electronics Letters 52, no. 5 (March 2016): 348–50. http://dx.doi.org/10.1049/el.2015.3664.

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Kumar, Manoj, and Raj Kumar. "A Ultra Low Power 12 Bit Successive Approximation Register for Bio-Medical Applications." International Journal of Engineering & Technology 7, no. 3.16 (July 26, 2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.4.16192.

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Successive Approximation Register (SAR) analog to digital Converters (ADC) is favorable choice for the high resolution. As resolution of ADC increases, the no. of redundant cycles increases which increases power. So the Paper presents clock gated ADC with no redundant cycles/transition cycles for low power requirement and comparison between without Clock Gating and Clock Gated SAR. Using Simulation, Power consumption for Clock gated SAR 736.1nW at 1.8V power supply where as without Clock Gating SAR consumption is 54µW at 1.8 power supply.

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Zhu, Donglin, Maliang Liu, and Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.

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In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.

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Malandruccolo, Vezio, Mauro Ciappa, Hubert Rothleitner, M. Hommel, and Wolfgang Fichtner. "A new built-in screening methodology for Successive Approximation Register Analog to Digital Converters." Microelectronics Reliability 50, no. 9-11 (September 2010): 1750–57. http://dx.doi.org/10.1016/j.microrel.2010.07.096.

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Lin, Chih-Hsuan, and Kuei-Ann Wen. "An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System." Journal of Low Power Electronics and Applications 11, no. 1 (January 9, 2021): 3. http://dx.doi.org/10.3390/jlpea11010003.

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With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.

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Lin, Chih-Hsuan, and Kuei-Ann Wen. "An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System." Journal of Low Power Electronics and Applications 11, no. 1 (January 9, 2021): 3. http://dx.doi.org/10.3390/jlpea11010003.

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With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.

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Wang, Hao, Lungui Zhong, and Guocheng Zhang. "Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 10 (May 24, 2018): 1850161. http://dx.doi.org/10.1142/s021812661850161x.

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A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.

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Sun, Lei, Kong-Pang Pun, and Wai-Tung Ng. "Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs." Journal of Engineering 2014, no. 1 (January 1, 2014): 45–48. http://dx.doi.org/10.1049/joe.2013.0219.

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Al-Naamani, Yahya Mohammed Ali, K. Lokesh Krishna, and A. M. Guna Sekhar. "A Successive Approximation Register Analog to Digital Converter for Low Power Applications." Journal of Computational and Theoretical Nanoscience 17, no. 1 (January 1, 2020): 451–55. http://dx.doi.org/10.1166/jctn.2020.8689.

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In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

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Qu, Weiyue, Jinqiang Zhao, Zhaofeng Zhang, and Niansong Mei. "Low-Energy Switching Method Based on Asymmetric Binary Search Algorithm for SAR ADCs." Journal of Circuits, Systems and Computers 29, no. 06 (August 15, 2019): 2050087. http://dx.doi.org/10.1142/s0218126620500875.

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An area-efficient and low-energy switching method for the successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. Unlike most switching methods, the proposed switching method resolves the first three bits by using asymmetric binary search algorithm. Benefiting from the novel reference voltages – [Formula: see text], [Formula: see text](1/4[Formula: see text]), ground, this proposed switching method achieves 87.5% area reduction and 98.71% energy reduction over the conventional method. Furthermore, it also achieves good linearity.

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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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Wang, Hao, Wenming Xie, Zhixin Chen, and Sijing Cai. "A Capacitor-Splitting Switching Scheme with Low Total Power Consumption for SAR ADCs." Journal of Circuits, Systems and Computers 28, no. 04 (March 31, 2019): 1920002. http://dx.doi.org/10.1142/s0218126619200020.

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A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-efficient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CV[Formula: see text] total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.

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Du, Ling, Ning Ning, Shuangyi Wu, Qi Yu, and Yang Liu. "A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter." Journal of Computer and Communications 01, no. 06 (2013): 30–36. http://dx.doi.org/10.4236/jcc.2013.16006.

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Liang, Hongzhi, Ruixue Ding, Shubin Liu, and Zhangming Zhu. "Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs." Journal of Circuits, Systems and Computers 27, no. 07 (March 26, 2018): 1850109. http://dx.doi.org/10.1142/s0218126618501098.

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An asymmetric architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) are proposed. The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively.

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SARAFI, SAHAR, KHEYROLLAH HADIDI, EBRAHIM ABBASPOUR, ABU KHARI BIN AAIN, and JAVAD ABBASZADEH. "100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450057. http://dx.doi.org/10.1142/s0218126614500571.

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This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

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HUANG, Jhin-Fang, Wen-Cheng LAI, and Cheng-Gu HSIEH. "A 10-bit 100 MS/s Successive Approximation Register Analog-To-Digital Converter Design." IEICE Transactions on Electronics E97.C, no. 8 (2014): 833–36. http://dx.doi.org/10.1587/transele.e97.c.833.

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Li, Jianwen, Xuan Guo, Jian Luan, Danyu Wu, Lei Zhou, Nanxun Wu, Yinkun Huang, et al. "A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology." Electronics 9, no. 2 (February 23, 2020): 375. http://dx.doi.org/10.3390/electronics9020375.

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A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

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Liang, Yuhua, and Zhangming Zhu. "An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850015. http://dx.doi.org/10.1142/s0218126618500159.

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A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the [Formula: see text]-based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100[Formula: see text]kS/s SAR ADC is designed in SMIC 0.18-[Formula: see text]m CMOS process. At a 0.6-V supply, the ADC consumes 43.7[Formula: see text]nW. Consequently, the figure-of-merit (FOM) is optimized to 0.58[Formula: see text]fJ/conversion-step.

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Momeni, Mahdi, and Mohammad Yavari. "Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area." International Journal of Circuit Theory and Applications 48, no. 11 (July 26, 2020): 1873–86. http://dx.doi.org/10.1002/cta.2852.

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Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (December 28, 2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

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This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

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Mueller, Jan Henning, Sebastian Strache, Laurens Busch, Ralf Wunderlich, and Stefan Heinen. "The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions." International Journal of Electronics and Telecommunications 59, no. 2 (June 1, 2013): 161–67. http://dx.doi.org/10.2478/eletel-2013-0019.

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Abstract This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.

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Pham, Huyen Thanh, Thang Vu Nguyen, Loan Pham-Nguyen, Heisuke Sakai, and Toan Thanh Dao. "Design and Simulation of a 6-Bit Successive-Approximation ADC Using Modeled Organic Thin-Film Transistors." Active and Passive Electronic Components 2016 (2016): 1–11. http://dx.doi.org/10.1155/2016/7201760.

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We have demonstrated a method for using proper models of pentacene P-channel and fullerene N-channel thin-film transistors (TFTs) in order to design and simulate organic integrated circuits. Initially, the transistors were fabricated, and we measured their main physical and electrical parameters. Then, these organic TFTs (OTFTs) were modeled with support of an organic process design kit (OPDK) added in Cadence. The key specifications of the modeled elements were extracted from measured data, whereas the fitting ones were elected to replicate experimental curves. The simulating process proves that frequency responses of the TFTs cover all biosignal frequency ranges; hence, it is reasonable to deploy the elements to design integrated circuits used in biomedical applications. Complying with complementary rules, the organic circuits work properly, including logic gates, flip-flops, comparators, and analog-to-digital converters (ADCs) as well. The proposed successive-approximation-register (SAR) ADC consumes a power of 883.7 µW and achieves an ENOB of 5.05 bits, a SNR of 32.17 dB at a supply voltage of 10 V, and a sampling frequency of about 2 KHz.

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Koppa, Santosh, Manouchehr Mohandesi, and Eugene John. "An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications." Journal of Low Power Electronics 12, no. 4 (December 1, 2016): 385–93. http://dx.doi.org/10.1166/jolpe.2016.1452.

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An, Sheng-Biao, Li-Xin Zhao, Shi-Cong Yang, Tao An, and Rui-Xia Yang. "Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique." Journal of Nanoelectronics and Optoelectronics 15, no. 4 (April 1, 2020): 478–86. http://dx.doi.org/10.1166/jno.2020.2782.

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This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

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Jagadish, D. N., and M. S. Bhat. "Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter." Journal of Low Power Electronics 11, no. 3 (September 1, 2015): 436–43. http://dx.doi.org/10.1166/jolpe.2015.1389.

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Zhao, Yi-qiang, Ming Yang, and Hong-liang Zhao. "A cryogenic 10-bit successive approximation register analog-to-digital converter design with modified device model." Journal of Shanghai Jiaotong University (Science) 18, no. 5 (October 2013): 520–25. http://dx.doi.org/10.1007/s12204-013-1436-8.

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Kobayashi, Yutaro, and Haruo Kobayashi. "Redundant SAR ADC Algorithm Based on Fibonacci Sequence." Key Engineering Materials 698 (July 2016): 118–26. http://dx.doi.org/10.4028/www.scientific.net/kem.698.118.

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This paper describes a redundant Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design method which enables high-reliability and high-speed AD conversion by using digital error correction. Especially we introduce to apply Fibonacci sequence and its property called Golden ratio to SAR ADC design to improve conventional redundant search algorithms. We also present some derived equations and many beautiful properties for well-balanced redundancy design for SAR ADC

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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

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Huang, Jhin-Fang, Jin-Yu Wen, and Cheng-Ku Hsieh. "An 8-bit 20 MS/s Successive Approximation Register Analog-to-digital Converter with Low Input Capacitance." International Journal of Engineering Practical Research 3, no. 4 (2014): 83. http://dx.doi.org/10.14355/ijepr.2014.0304.04.

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Lin, Jie, and Jiann-Shiun Yuan. "A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs." Journal of Low Power Electronics 13, no. 3 (September 1, 2017): 497–510. http://dx.doi.org/10.1166/jolpe.2017.1503.

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Liu, Shubin, Haolin Han, and Ruixue Ding. "Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC." Journal of Circuits, Systems and Computers 28, no. 13 (January 30, 2019): 1930010. http://dx.doi.org/10.1142/s0218126619300101.

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A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

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Ro, Duckhoon, Changhong Min, Myounggon Kang, Ik Joon Chang, and Hyung-Min Lee. "A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems." Sensors 20, no. 1 (December 27, 2019): 171. http://dx.doi.org/10.3390/s20010171.

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For stable and effective control of the sensor system, analog sensor signals such as temperature, pressure, and electromagnetic fields should be accurately measured and converted to digital bits. However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from radiation effects that degrade the performance of the sensor readout system including analog-to-digital converters (ADCs) and cause system malfunctions. This paper investigates an optimal ADC structure in radiation environments and proposes a successive- approximation-register (SAR) ADC using delay-based double feedback flip-flops to enhance the system tolerance against radiation effects, including total ionizing dose (TID) and single event effects (SEE). The proposed flip-flop was fabricated using 130 nm complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process, and its radiation tolerance was measured in actual radiation test facilities. Also, the proposed radiation-hardened SAR ADC with delay-based dual feedback flip-flops was designed and verified by utilizing compact transistor models, which reflect radiation effects to CMOS parameters, and radiation simulator computer aided design (CAD) tools.

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Li, Shouping, Yang Guo, Jianjun Chen, and Bin Liang. "A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm." Symmetry 12, no. 1 (January 14, 2020): 165. http://dx.doi.org/10.3390/sym12010165.

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This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

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Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, and Jong-Kee Kwon. "A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 7 (July 2010): 502–6. http://dx.doi.org/10.1109/tcsii.2010.2048387.

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Chi, Yingying, and Dongmei Li. "A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration." Journal of Semiconductors 34, no. 4 (April 2013): 045007. http://dx.doi.org/10.1088/1674-4926/34/4/045007.

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RAMAMOORTHY, SARAVANAN, and HAIBO WANG. "ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE." Journal of Circuits, Systems and Computers 22, no. 06 (July 2013): 1350048. http://dx.doi.org/10.1142/s0218126613500485.

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Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

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Li, Jing, Xin Ye, Jian Luo, Ning Ning, and Qi Yu. "A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs." Journal of Circuits, Systems and Computers 28, no. 06 (June 12, 2019): 1950092. http://dx.doi.org/10.1142/s0218126619500920.

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This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with [Formula: see text] samples and costs less hardware with 2.1[Formula: see text]k gate counts.

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Ren, Si Kui, and Zhi Qun Li. "Design of Low Voltage Low Power ADC for WSN Node." Advanced Materials Research 760-762 (September 2013): 561–66. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.561.

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This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

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Liu, Wenbo, Pingli Huang, and Yun Chiu. "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration." IEEE Journal of Solid-State Circuits 46, no. 11 (November 2011): 2661–72. http://dx.doi.org/10.1109/jssc.2011.2163556.

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Wadatsumi, Takuya, Takuji Miki, and Makoto Nagata. "A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks." Japanese Journal of Applied Physics 60, SB (February 10, 2021): SBBL03. http://dx.doi.org/10.35848/1347-4065/abde26.

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Gao, Bo, Xin Li, Jie Sun, and Jianhui Wu. "Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM." Electronics 9, no. 1 (January 10, 2020): 137. http://dx.doi.org/10.3390/electronics9010137.

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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Li, Shouping, Jianjun Chen, Bin Liang, and Yang Guo. "Low Power SAR ADC Design with Digital Background Calibration Algorithm." Symmetry 12, no. 11 (October 23, 2020): 1757. http://dx.doi.org/10.3390/sym12111757.

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This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

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Kumar Y, L. V. Santosh. "Design and Implementation of SAR-ADC for Medical Electronic Applications." International Journal of Advanced Research in Computer Science and Software Engineering 8, no. 5 (June 2, 2018): 55. http://dx.doi.org/10.23956/ijarcsse.v8i5.665.

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in today’s advance electronic and communication systems the role of high accuracy analog to digital converters are of great importance. Nowadays, a larger percentage of mixed-signal applications requires for health care systems. Also the speed of the chosen ADC design matters a lot as we are connected with the real world signals. SAR based ADC will provides us a better solution for various analog to digital systems. It is an essential device whenever data from the analog world, through sensors or transducers, should be digitally processed or when transmitting data between chips through either long-range wireless links or high-speed transmission between chips on the same printed circuit board. The paper projects up down and ring counter as a logic for successive approximation register (SAR logic for a ADC that is one of the best suited for low power. Here the resolution is of 4-bit and a power consumption of few milli watts. SAR ADC is implemented in 45 nm nano-meter scaling technology CMOS technology with a power supply of 0.5v by maintaining 4:1 w/l ratio.

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Babayan-Mashhadi, Samaneh, and Mona Jahangiri-Khah. "A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850230. http://dx.doi.org/10.1142/s0218126618502304.

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As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

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Villa, Jorge, José I. Artigas, Luis A. Barragán, and Denis Navarro. "An Amplifier-Less Acquisition Chain for Power Measurements in Series Resonant Inverters." Sensors 19, no. 19 (October 8, 2019): 4343. http://dx.doi.org/10.3390/s19194343.

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Successive approximation register (SAR) analog-to-digital converter (ADC) manufacturers recommend the use of a driver amplifier to achieve the best performance. When a driver amplifier is not used, the conversion speed is severely penalized because of the need to meet the settling time constraint. This paper proposes a simple digital correction method to raise the performance (conversion speed and/or accuracy) when the acquisition chain lacks a driver amplifier. It is intended to reduce the cost, size and power consumption of the conditioning circuit while maintaining acceptable performance. The method is applied to the measurement of the output power delivered by a series resonant inverter for domestic induction heating.

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Hu, Yunfeng, Chao Xiong, and Bin Li. "A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme." Modern Physics Letters B 31, no. 19-21 (July 27, 2017): 1740051. http://dx.doi.org/10.1142/s0217984917400516.

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A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

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Kim, Jaesung, Kwonsang Han, Hyungseup Kim, Byeoncheol Lee, Sangyoun Shin, and Hyoungho Ko. "4.36 fJ/Conversion-step Ultralow-power 16-bit Successive Approximation Register Capacitance-to-digital Converter in 0.18 ��m CMOS Process." Sensors and Materials 31, no. 5 (May 16, 2019): 1535. http://dx.doi.org/10.18494/sam.2019.2273.

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Yu, Zhiguo, Tao Wang, Xinyu Song, Tian Wang, Kangsheng Liu, and Xiaofeng Gu. "An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter." International Journal of Circuit Theory and Applications 49, no. 3 (January 12, 2021): 820–29. http://dx.doi.org/10.1002/cta.2941.

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Journal articles on the topic 'Successive approximation register converters'

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