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MURATORE, DANTE GABRIEL. "A Study of Successive Approximation Register ADC Architectures." Doctoral thesis, Università degli studi di Pavia, 2017. http://hdl.handle.net/11571/1203278.
Full textAbstract:
In the era of all-mobile devices and the Internet of Things, power efficient solutions are required by new applications. Wearables and battery supplied systems are in high demand, asking designers to come up with new ideas for ultra low- power high-performances data converters. Among all the possible architectures, SAR ADCs stand out because of their high efficiency. Besides, the quasi all-digital nature of this topology greatly adapts to the technological scaling and the simple structure better suits to more complex system-level designs. Apart from being an excellent choice as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited for hybrid solutions that further pushes away the limits of other types of converters, such pipeline or oversampled ADCs.
The goal of this thesis is to study the versatility and adaptability of the SAR algorithm for different applications. In order to do so, 3 different projects carried out during the Ph.D. activity are presented. These are
1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS.
2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring.
3. A 200 μW 12-b 8 MS/s SAR ADC for Ultrasound Systems.
The presented ADCs highly differ from the performances point of view, but they all share the fact that they use the SAR algorithm to meet the requirements of the given application. The first two projects were fabricated and tested, while the third has been simulated at post-layout level.
Project # 1 is a high-speed single-channel ADC for wireline communications. The architecture uses a sub-ranging approach with a flash converter and a multi-bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements of the first stages, and a shift-register free logic is implemented. Thresholds in the multi-bit per cycle SAR converter are produced by a special preamplifier that uses an interpolation-like technique. A novel comparator speeds up the overall operation of the converter, by using a built-in preamplifier that initially unbalances the output of the latch.
Project # 2 implements an extended-range ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC for the coarse conversion of the battery cell voltages, and a single SAR ADC for the fine conversion. The high-voltage section is limited to 8 switches and a high- voltage capacitor reducing the cost of the converter. The remaining part of the circuit operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-simultaneous sampling of the battery cells, and the single fine converter limits the mismatch between channels.
Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems. The ADC is intended to be used in the acquisition channel of a wearable tran- scranial doppler ultrasound system (TCD) to measure cerebral blood flow velocity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so area and power constraints are the most stringent specifications. An hybrid resistive- capacitive structure is used to reduce the area of the DAC, while an asynchronous logic optimises the timing of the converter and the power consumption.
Chapter 1 introduces to the reader the most common data converter architec- tures and provides a discussion on the evolution of data converter during the past years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chap- ters 2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while con- clusions are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to provide a more direct access to the reader.<br>In the era of all-mobile devices and the Internet of Things, power efficient solutions are required by new applications. Wearables and battery supplied systems are in high demand, asking designers to come up with new ideas for ultra low- power high-performances data converters. Among all the possible architectures, SAR ADCs stand out because of their high efficiency. Besides, the quasi all-digital nature of this topology greatly adapts to the technological scaling and the simple structure better suits to more complex system-level designs. Apart from being an excellent choice as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited for hybrid solutions that further pushes away the limits of other types of converters, such pipeline or oversampled ADCs.
The goal of this thesis is to study the versatility and adaptability of the SAR algorithm for different applications. In order to do so, 3 different projects carried out during the Ph.D. activity are presented. These are
1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS.
2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring.
3. A 200 μW 12-b 8 MS/s SAR ADC for Ultrasound Systems.
The presented ADCs highly differ from the performances point of view, but they all share the fact that they use the SAR algorithm to meet the requirements of the given application. The first two projects were fabricated and tested, while the third has been simulated at post-layout level.
Project # 1 is a high-speed single-channel ADC for wireline communications. The architecture uses a sub-ranging approach with a flash converter and a multi-bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements of the first stages, and a shift-register free logic is implemented. Thresholds in the multi-bit per cycle SAR converter are produced by a special preamplifier that uses an interpolation-like technique. A novel comparator speeds up the overall operation of the converter, by using a built-in preamplifier that initially unbalances the output of the latch.
Project # 2 implements an extended-range ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC for the coarse conversion of the battery cell voltages, and a single SAR ADC for the fine conversion. The high-voltage section is limited to 8 switches and a high- voltage capacitor reducing the cost of the converter. The remaining part of the circuit operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-simultaneous sampling of the battery cells, and the single fine converter limits the mismatch between channels.
Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems. The ADC is intended to be used in the acquisition channel of a wearable tran- scranial doppler ultrasound system (TCD) to measure cerebral blood flow velocity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so area and power constraints are the most stringent specifications. An hybrid resistive- capacitive structure is used to reduce the area of the DAC, while an asynchronous logic optimises the timing of the converter and the power consumption.
Chapter 1 introduces to the reader the most common data converter architec- tures and provides a discussion on the evolution of data converter during the past years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chap- ters 2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while con- clusions are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to provide a more direct access to the reader.
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Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.
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Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.
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Radhakrishnan, Ram Harshvardhan. "Accelerated Successive Approximation Technique for Analog to Digital Converter Design." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1630.
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This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
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Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.
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<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.</p>
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Mahsereci, Yigit Uygar. "A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers." Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.
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Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance.
The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18µ<br>m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required.
A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta<br>-&Sigma<br>DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control.
The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.
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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.
This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Yang, Kun. "A 16 Bit 500KSps low power successive approximation analog to digital converter." Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Thesis/Fall2009/k_yang_111809.pdf.
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Thesis (M.S. in electrical engineering)--Washington State University, December 2009.<br>Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
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Sekar, Ramgopal. "LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.
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In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
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Guo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.
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An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. A proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215×215 μm². Due to an unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 μW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.
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Barton, Patrick Randal. "A synthesis program for CMOS successive approximation A/D and D/A converters." Thesis, Georgia Institute of Technology, 1986. http://hdl.handle.net/1853/15347.
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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Tirunelveli, Kanthi Saravanan. "Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33884.
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In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.
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David, Christopher Leonidas. "All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.
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The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
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Chung, Hong-Yi, and 鐘鴻儀. "A 10-bit Successive Approximation ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57183272659084856815.
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碩士<br>國立暨南國際大學<br>電機工程學系<br>98<br>Propose a fully differentially successive approximation ADC with a binary-weighted capacitor array networks. Add bootstrapped switches to accelerate charging to the capacitor networks in front of this architecture, and decrease the settling time of capacitor array. Also keep circuit operate correctly under low supply voltage driving switches. Use asynchronous control logic to generate the necessary clock signals internally, rather then provide clocks by external clock generator. Unit capacitors of the capacitor array are laid out in a common-centroid scheme to reduce the undercutting effect, for achieving the correct ratio of capacitor array.
According to the result of simulation , the proposed ADC is designed to operate at 5Ms/s.Signal-to-noise and distortion ratio is 58.696dB, under the frequency of input signal is 2.5Mhz, the effective number of bit is 9.458 bit. The integral nonlinearity (INL) is 1.9 LSB. The differential nonlinearity (DNL) is 1.85 LSB. The power consumption is 5.3mW. Layout area of this architecture is 1080um * 880um.
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Jaber, Nasser M. A. Jr. "Accelerating Successive Approximation Algorithm Via Action Elimination." Thesis, 2008. http://hdl.handle.net/1807/16794.
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This research is an effort to improve the performance of successive approximation algorithm with a prime aim of solving finite states and actions, infinite horizon, stationary, discrete and discounted
Markov Decision Processes (MDPs). Successive approximation is a simple and commonly used method to solve MDPs. Successive approximation often appears to be intractable for solving large scale MDPs due to its computational complexity. Action elimination, one of the techniques used to accelerate solving MDPs, reduces the
problem size through identifying and eliminating sub-optimal actions. In some cases successive approximation is terminated when all actions but one per state are eliminated.
The bounds on value functions are the key element in action elimination. New terms (action gain, action relative gain and action
cumulative relative gain) were introduced to construct tighter bounds on the value functions and to propose an improved action
elimination algorithm.
When span semi-norm is used, we show numerically that the actual convergence of successive approximation is faster than the known theoretical rate. The absence of easy-to-compute bounds on the actual convergence rate motivated the current research to try a
heuristic action elimination algorithm. The heuristic utilizes an estimated convergence rate in the span semi-norm to speed up action
elimination. The algorithm demonstrated exceptional performance in terms of solution optimality and savings in computational time.
Certain types of structured Markov processes are known to have monotone optimal policy. Two special action elimination algorithms
are proposed in this research to accelerate successive approximation for these types of MDPs. The first algorithm uses the state space partitioning and prioritize iterate values updating in a way that maximizes temporary elimination of sub-optimal actions based on the policy monotonicity. The second algorithm is an improved version that includes permanent action elimination to improve the performance of the algorithm. The performance of the proposed algorithms are assessed and compared to that of other algorithms. The proposed algorithms demonstrated outstanding performance in
terms of number of iterations and omputational time to converge.
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Yeh, Li-Ken, and 葉力墾. "A Successive Approximation ADC for Accelerometer System." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85409347982202791714.
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碩士<br>國立清華大學<br>電子工程研究所<br>97<br>This work presents a 10Ks/s 10-bit successive approximation analog-to-digital converter which is realized in a 0.35um CMOS process. The design combines an input offset storage latch-comparator, a sample and hold, a resistor-capacitor array DAC, and SAR digital logic while consuming less than 720uW with a 3.0V power supply. The experimental results show that the effective number of 7.61 bits with 10Ks/s and 100Hz signal frequency.
Main purpose of the whole circuit is integrating into CMOS MESMS accelerometer and IIC interface circuit.
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Liu, Te-Hsiang, and 劉德祥. "A Low-power 10-bit Successive Approximation ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/93018442633893142862.
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碩士<br>國立暨南國際大學<br>電機工程學系<br>101<br>A low-power 10-bit successive approximation ADC for wireless sensor networks is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.7 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multilayered sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption.
The low-power 10-bit successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS process provided by Chip Implementation Center (CIC). The core area of the chip is 201 μm × 180 μm (0.03618 mm2), and the total area including pads is 680 μm × 680 μm (0.4624 mm2). From the measurement results at 0.7 V supply voltage, 2.4 MHz operating frequency, 200 kS/s sampling rate, and 1 kHz input frequency, an SNDR of 52.95 dB (ENOB of 8.5 bits) is achieved with 1.624 μW power consumption. The FOM is 22.4 fJ/conversion, and its ERBW is up to Nyquist rate.
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Liu, Yu-Hsun, and 劉宇珣. "A Low Power Sub-range Successive-Approximation ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/29200334853561401027.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving total conversion rate. Then we use overlap action to correct error exist in the MSB comparison. A 12-bit 10MS/s low power consumption Successive-Approximation Analog-to-Digital Converter applied for the Bluetooth system is proposed. This design adopted TSMC 0.13-um 1P8M CMOS process. While the chip operates at sampling rate 10MS/s and Nyquist rate input frequency, the SNDR and SFDR achieve 59.7dB and 69.8dB respectively. The power consumption of core circuit is 3mW. The chip with pads occupies 1.19mm2 and the core area is about 0.096 mm2.
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Hui-WenChang and 張惠雯. "Adaptive Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/51357130831815732105.
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Coe, Matthew T. "Digital implementation of a mismatch-shaping successive-approximation ADC." Thesis, 2001. http://hdl.handle.net/1957/31137.
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Utilizing a two-capacitor topology, the digital implementation of an audio-band
successive-approximation analog-to-digital converter (ADC) is explored in the
context of mismatch-shaping where the mismatch estimates are accurate to the first
order. A second-order ����� loop was found to be effective in system simulations
given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic
improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise
and distortion ratio) for an oversampling ratio of 10.<br>Graduation date: 2002
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Chen, Tsung-Huan, and 陳宗煥. "Successive Approximation Architecture for Low-Power A/D Converter." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10379417291187109746.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>97<br>Two successive approximation analog-to-digital converters are presented in this thesis. In the first architecture, a converter that meets the specification of HDTV system is implemented. We use simple boot-strapped technique in sample-and-hold to ensure the quality of sampled signal is above specification while still has sufficient bandwidth. Besides, both PMOS and NMOS are adopted in the input differential pairs of the comparator to guarantee the input signal range could reach rail-to-rail. The experimental results of the first converter, an 8-bit 54 MS/s SAR ADC, show that the total power consumption is 1.8 mW by using TSMC 0.18-�慆 process. The signal-to-noise and distortion ratio (SNDR) is 49.1 dB with 1 MHz input frequency and the figure-of-merit (FOM) is only 140 fJ/conversion-step.
In the second architecture, we employ double sampling technique in the front-end track-and-hold. This not only improves the drawback of reduced input signal range as in the conventional passive charge sharing architecture, but halves the size of sampling capacitor, thus greatly decreases the silicon area and certain unnecessary power wasting. The experimental results of the second converter, an 8-bit 20 MS/s SAR ADC, show that the total power consumption is 150 �巰. The SNDR is 48 dB with 1 MHz input frequency and the FOM of pre-layout simulation is 36 fJ by using TSMC 0.13-�慆 process which is comparable with the current state-of-the-art inventions.
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Weng, Hou-Sheng, and 翁穫勝. "Worst-Case Robust Multiuser Beamforming by Successive Convex Approximation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/32670077695041157525.
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碩士<br>國立臺灣科技大學<br>電子工程系<br>103<br>This work considers multiuser downlink beamforming design problems for maximizing the system spectrum efficiency and energy efficiency, respectively. Specifically, we assume that the base station has only imperfect, but bounded channel state information (CSI) error, and aim to design beamforming strategies for maximizing the worst-case spectrum efficiency and energy efficiency, respectively. The considered problems have been known to be NP-hard in general. Therefore, we seek computationally efficient and high-quality approximate solutions to the considered problems. The proposed methods are based on the successive convex approximation techniques, in which the difficult problem is approximated by a sequence of convex problems. The presented simulation results demonstrate that the proposed methods either outperform the existing methods or are computationally more efficient.
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Liao, Bo-Shi, and 廖柏詩. "Power-Efficient Successive-Approximation Register Analog-to-Digital Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/88290005656371369947.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification.
In the field of low power SAR ADC, an 12-bit 10MS/s single-channel SAR and 7-bit 2GS/s calibration-free time-interleaved ADC are presented. This thesis first proposes an energy-efficient high resolution SAR ADC with small unit capacitance and simple controller logic. In order to save digital power, it combined with arbitrary capacitor array, which tolerates errors of dynamic offset and capacitor settling in MSBs during conversion and a differential control logic circuit are proposed to decrease the circuit complexity. The technique are verified by TSMC 1P6M3X1Z1U 40nm Low Power CMOS process. This work operates at 10MS/s in 0.9V supply voltage. Its power dissipation is only 36.9μW and gets 10.05 bit ENOB performance after off-chip calibration with low-frequency input. As the result, the peak FoM performance is 3.48fJ/conversion-step.
In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it. In addition, a front-end track-and-hold circuit is implemented in order to eliminate time skew mismatch. This time-interleaved ADC in 55nm CMOS technology post-simulation achieves an ENOB of 6.8 and consumes 24.8mW. It results in a FoM of 117fJ/conversion-step.
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Ting-ZiChen and 陳亭諮. "A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12587977983657161660.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>100<br>This thesis presents a 10-bit 50MS/S successive approximation ADC with low input capacitance that uses an on-chip resistive ladder and capacitor array to arrange a new switching scheme. This analog to digital converter possesses a predictive circuit in order to avoid unnecessary switching in DAC network. In addition, the proposed SAR ADC manipulates the concept of 1.5-bit/stage, which is usually employed in pipelined ADC to ease the design of coarse ADC. Besides, the ADC adopts hybrid capacitive and resistance DAC rather than a pure capacitive one. With this hybrid DAC, the total capacitance of the DAC can be largely reduced. For the sake of enhancing sampling frequency, the ADC uses asynchronous timing control technique to remove the high frequency clock generator. Moreover, the splitting monotonic switching procedure is adopted to reduce the signal-dependent dynamic offset of comparator for maintaining good ADC linearity.
This work is fabricated in TSMC 90-nm 1P9M CMOS process, and occupies 220μm × 190μm active area. This prototype chip consumes 0.703 mW from a 1.2-V supply and the effective number of bits (ENOB) is 9.3 bits. The resultant FOM is 28 fJ/conversion-step. The peak DNL and INL are -0.49/0.58 LSB and -0.95/1.1 LSB, respectively.
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Yeh, Kun-Ming, and 葉昆明. "Low Power Successive Approximation Register Analog to Digital Converter Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/52219798851756448222.
Full textAbstract:
碩士<br>國立中興大學<br>電機工程學系所<br>102<br>This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch are used.
The SAR ADC is designed and simulated by HSPICE with TSMC 0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS technology. The supply voltage of the 8-bit SAR ADC is 1.8V and the sampling rate is 5KHz. Its power consumption is 1100μW.
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Huang, Guan-Ying, and 黃冠穎. "Design of Energy Efficient Successive-Approximation Analog-to-Digital Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/6cut26.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>In this thesis, two successive-approximation (SAR) analog-to-digital converters (ADCs) are proposed. In the first ADC, a novel RC time constant capacitor array, which adjusts the numbers of switch, is used to speed up the conversion rate. And a self timing controller is used to control the comparator, which can save half of the power consumption of the comparator. Simulation results of the first ADC, an 8-bit 27 MS/s SAR ADC, show that the total power consumption is 385 μW and the average energy consumption per conversion step is 105 fJ in the TSMC 0.13 μm process.
In order to further increase the conversion rate, a novel capacitor array with passive charge-sharing (PCS) technique, which can effectively reduce the total power consumption and the input capacitance, is used in the second ADC. Simulation results of the second ADC, an 8-bit 50 MS/s PCS SAR ADC, show that the total power consumption is 294 μW and the average energy consumption per conversion step is 41 fJ in the TSMC 0.13 μm process.
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Kao, Ching-Ya, and 高靖亞. "Low Dropout Regulator with Successive Approximation Analog to Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/77112625875388205251.
Full textAbstract:
碩士<br>淡江大學<br>電機工程學系碩士班<br>101<br>Abstract:
Soc circuit will produce a non-ideal effect with process, supply voltage, and temperature, which cause the chip does not work or lead to damage to the chip in serious. And how to design a low power consumption of the circuit is an important issue.
We will design a circuit which use of the successive approximation analog to digital converter to replace error amplifier. Therefore, this paper the target for the design of a low dropout linear regulator with successive approximation analog to digital converter architecture.
There are several key considerations of low dropout linear regulator characteristic parameters: (1) The output voltage difference (△ V) (2) linear regulator with quiescent current (The Quiescent Current, Iq) rate (Line Regulation, LNR) (3 ) load Regulation (Load Regulation, LDR); these parameters has a close relationship with the load current, precision, settling time. The circuit can be divided into three parts, the first part of the 8-bit successive approximation analog-to-digital converter architecture, the second part is the switching of the power transistor, the last part is the comparator.
Using the signal from SAR ADC to control the power transistor to achieve the output voltage, and reduce the quiescent current in the steady state. First, compare the input voltage and the original supply voltage to control the feedback resistor switching. Second, current changes will control turn on the power transistor or turn off the power transistor.
The simulation results are based on 0.18μm CMOS process. The current efficiency is 99.94%. Moreover, the quiescent current of the circuit is 15.8μA in a heavy load condition.
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Yeh, Chen-Kuang, and 葉晨光. "A successive approximation ADC based on a new segmented DAC." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/66685377242348443138.
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碩士<br>南台科技大學<br>電子工程系<br>90<br>A successive approximation analog-to-digital converter (ADC) based on a new segmented digital-to-analog converter (DAC) architecture is presented. A more efficient method which is the bi-direction segmented current-mode approach is proposed to implement the high-resolution and high speed DAC. This DAC has the maximum integral nonlinearity (INL) error of 0.47 LSB, and the maximum differential nonlinearity (DNL) error of 0.154 LSB. Based on this new DAC, a 3-V, 8-bit, 2-MS/s ADC is realized. The whole circuit is implemented by the TSMC 1P4M 0.35μm CMOS process. The experimental results show that the INL of ADC is less than 0.82 LSB. Meanwhile, the DNL is less than 0.31 LSB. The power consumption is only 2.6mW with the effective number of bits of 7.
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Hu, Ting-Wei, and 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.
Full textAbstract:
碩士<br>國立中興大學<br>電機工程學系所<br>104<br>This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added.
The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue.
With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement results of Sarf2_35 chip is obtained. When input frequency is 10MHZ ,the effective number of bits is 6.09bit.When input frequency is 1GHZ, the effective number of bits is 3.48bit.
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Jiang, Ru Hui, and 江茹慧. "Low Dropout Regulator for Successive Approximation Analog to Digital Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/11364419615243477868.
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碩士<br>國立清華大學<br>電機工程學系<br>104<br>Low Dropout Linear Regulator has been widely used in a variety of 3C products, especially the popular portable electronic products in recent years, where extending battery life is the most important thing.Since there are many different modules on electronic circuit, so they need a variety of voltage levels of the DC supply voltage. Thus, the circuit of a system required use multiple voltage regulator circuit, voltage regulator IC plays a very important roles in the performance and stability characteristics of electronic products.
In the field of analog IC design can be divided into several parts: A / D, D / A ,voltage source, current source, amplifier, and a voltage source which is the very important, because a stable voltage or current source is the basis of analog circuits. Electronic components diodes, resistors, capacitors and transistors, etc. are affected by changes of temperature. Analog design for only a few degrees Celsius temperature difference can cause a tremendous impact.
In this paper, the research focus on the design of a low-dropout linear regulator with a stable voltage, the former includes voltage reference generator, error amplifier, feedback network, and Power MOS and is implemented with TSMC 65nm process, operating voltage at 2.5 volt. Due to the linear regulator circuit having a simple structure, low output ripple, less external components, low power consumption and other characteristics. So it is suitable for using in portable electronic products.
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Wu, Po Chun, and 吳伯濬. "Time-interleaved Successive-Approximation Analog-to-Digital Converter with Redundancy." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/93721176098078768105.
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碩士<br>國立清華大學<br>電機工程學系<br>104<br>In recent years, the portable electronic device industry has been highly prosperous. The advance in wireless communication technology has dramatically improved people's lives. As the technologies progress constantly, analog-to-digital converter starts to play an important role in the era of digital. Analog-to-digital converter can convert nature signals into digital signals, then send the digital data to post-stage circuit. Thanks to the invention of the converts, technologies progress rapidly in these years. With the increase of the amount of data transmission and the growing demand of high-speed transmission, how to achieve high resolution and high sample rate analog-to-digital converter becomes one of the main issues.
This thesis introduces algorithms with Redundancy, multi-channel time-interleaved and successive-approximation analog-to-digital converter. Eventually, we have completed a multi-channel time-interleaved successive-approximation analog-to-digital converter with redundancy. Its specifications is 10bits and sampling rate is 400MS/s. We used TSMC 65 nm CMOS process to do the simulation design. This design achieves signal to noise and distortion ratio of 62.46dB, equivalent to the effective number of bits 10.08. The average power consumption is 9.38mW.
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Zeng, Jyun-Syuan, and 曾焌鉉. "A Successive-Approximation Analog-to-Digital Converter with half capacitance." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/18923140951377702775.
Full textAbstract:
碩士<br>國立清華大學<br>電機工程學系<br>101<br>Analog to digital converter are the essential bridge between nature world and digital world, and this thesis introduces a successive approximation analog to digital converter mainly used in the radar receiver, where the received RF signals are frequency-reduced after high-speed sampling, and then amplified by the baseband amplifier. The signals are then processed by the analog to digital converter and finally the converted digital signal to the computer for data analysis.
In the thesis, we have proposed a successive approximation analog to digital converter, which has been greatly improved the capacitance matrix, making the size 50% less than traditional ones. The ADCs with monotonic structure capacitance matrix of different places are able to maintain the common-mode voltage, which is a huge benefit to avoid comparator from generating random offset voltages. The 10 bits in 20 million samples per second successive approximation analog to digital converter is implemented in a TSMC 65 nm CMOS process. The design is operated in 1V with ENOB 9.97 and perfect DNL, INL. The average power consumption is 620μW, and the average energy consumption is 30fJ each conversion.
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Su, Shiou-Wei, and 蘇修緯. "A 10-bit Successive Approximation Register ADCWith Monotonic Capacitor Switching Procedure." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/95871280610812041429.
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Liang, Shing-Yan, and 梁興彥. "A Self-calibrating 10-bit Single End Successive Approximation Register ADC." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/rszv6d.
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Hung-Wei, Kevin Chen. "A New Calibration Method for Successive Approximation Register A/D Converter." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200617114500.
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Chen, Hsin-cheng, and 陳信成. "Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/xar24k.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>103<br>A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. The pipelined stage replace the Flash ADC by SAR ADC. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier.
Using dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications. An additional comparator for MSB is designed for the ADC using in sample phase. The error correction Logic is employed for higher resolution.
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Wang, Po-Tsang, and 王柏蒼. "A Metal Density Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77v7sk.
Full textAbstract:
碩士<br>國立中興大學<br>電機工程學系所<br>105<br>This thesis presents a high speed successive approximation register (SAR) analog to digital converter (ADC) with input buffer and the study of non-ideal situation. The design purpose of this SAR ADC is to use it as one of sub ADCs for a Time-Interleaved ADC. The sample rate of this SAR ADC is 166MS/s, and the highest input frequency is
1.2GHz. In order to strengthen the driving power, we add a buffer to the front end. Last, but not least, considering the characteristic impedance in the high frequency will affect the input signal, we improved the PCB layout design.
On the other hand, for minimizing the delay time after the signal triggered, the ADC’s control logic path is designed as parallel, which can improve the performance.
Fabricated under TSMC 90nm GUTM process, sarf_35 has the ENOB of 6.09 bit when the input frequency is 10MHz and 3.48 bit when input frequency is 1.2GHz. After the improvement, sarf_36 has a higher ENOB at 10MHz, which is 7.028bit, and 5.25bit at 1.2GHz.
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Chen, Hung-Wei Kevin, and 陳宏維. "A New Calibration Method for Successive Approximation Register A/D Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/49368774485171069345.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>94<br>The demand of low power electronic device is become strongly these years, especially in wireless and sensor network devices. Analog to digital converter (ADC) is the key building block of these devices. Therefore, a hot research topic is to reduce ADC power consumption. For some sensor application, the highly accuracy ADC is required. A main ADC architecture for sensor application is success approximation register (SAR). It’s accuracy is usually limited by the mismatch of capacitor array which is about 10 bit. A calibration circuit can be added to enhance the accuracy; however, it usually dissipates a lot power. This work presents a switch capacitor calibration technique to enhance the performance without consume a lot of power. The charge redistribution SAR ADC operation theory is base on charge conservation law. The mismatch of capacitor would cause the voltage shift during the comparison phase. The fundamental of this calibration idea is to store the positive and negative charge in the calibration capacitors during the sample phase. Then, during the comparison phase, these pre-stored charge injects into the main capacitor array to correct the voltage shift. This work is fabricated by TSMC 0.35um CMOS technology. The chip area is 1.88x1.88mm2, and the core area is 0.83 x 0.74mm2. The conversion rate is 200KS/s, and the measured analog power is 1.35mW at 5V and digital power is 3.3mW at 3.3V. The SNDR and SFDR before self-calibration are 63.9 and 74.7dB. After self-calibration process the SNDR and SFDR are 47.9 and 50.6dB. The performance after self calibration is degraded, and it is not expected. The cause of degrading may be noisily environment of testing board. However, the effect of this calibration circuit is only in odd harmonic, and it is the same as the prediction.
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Huang, Chia-Hsuan, and 黃嘉玄. "Low Power 12-bit Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82543200626928576057.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>Generally, the signal bandwidth of biomedical signals ( EEG, ECG, Oxygen Saturation, Heart Rate, Temperature ) is under 10 kHz [29]. For portable biomedical acquisition system, lower power A/D converter is an important component that can determine the performance of whole system.
In this paper, a 1.8V 12-bit 200-kS/s successive approximation analog-to-digital converter (SAR ADC) is presented in this work. In order to overcome the biomedical signal’s dc shift and acquire accurately, the proposed ADC receives rail-to-rail input and performs 12-bit resolution (10-bit is the basic requirement for normal biomedical signal). Moreover, the digital-to-analog converter without reference voltage (WRV) and binary capacitor array is also adopted to reduce the total chip area. With these properties, the proposed ADC can be easily integrated with other components in biomedical acquisition system at low cost. The proposed converter is designed in a 0.18-μm CMOS process for biomedical application. Simulation results show that both INL and DNL errors are well controlled in 0.34LSB. The measurement results show SNDR is 49.7 dB and the total power consumption is 76.32-μW at 1.8V supply voltage. The core area of the test chip is 0.082 mm2.
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Lee, Mao-Cheng, and 李茂誠. "Design of Low Power Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/91556839843235408859.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>To date ADCs play essential roles in the communication fields and in the bio-sensor applications. High-speed and low-power Analog-to-Digital converters (ADCs) are required in these applications. However, with the development of the CMOS technology, the design of high quality analog circuits becomes a challenge. The Successive approximation Register
(SAR) architectures primarily consist of digital circuits. With this property, the SAR ADCs are more suitable fabricated in advanced CMOS technology than other structures.
In this thesis, we present two SAR ADC architectures: a R-2R ladder DAC and a binary capacitive DAC. For the high speed applications, we chose a R-2R resistive DAC in our first work. We design a 10-bit R-2R ladder SAR ADC in TSMC 65nm CMOS technology. In addition, for the high resolution applications, we design a 12-bit capacitive SAR ADC in TSMC 65nm CMOS technology and we introduce two digital calibration technologies in this work.
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Lin, Jing Heng, and 林敬恆. "A 100MS/s Successive-Approximation Analog-to-Digital Converter with Redundancy." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/29066498543349448830.
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碩士<br>國立清華大學<br>電機工程學系<br>103<br>The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC with redundancy algorithm. The algorithm combines the criterion of capacitor mismatch and DAC settling time. The radix of each stage can be calculated precisely under 100 million samples per second. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1V supply voltage. The full rail-to-rail input swing is 1.9V peak to peak. This design achieve signal to noise and distortion ratio of 62.09dB, equivalent to the effective number of bits 10.02.The peak DNL values are -0.4 to +0.6 LSB and the peak INL values are -0.4 to +0.63 LSB. The average power consumption is 2.02mW.
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Su, Hung Tai, and 蘇宏泰. "Design of Fast Frequency-to-Voltage Converter Using Successive-Approximation Technique." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/80794066528236701141.
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碩士<br>南台科技大學<br>電子工程系<br>94<br>In this paper, the current conveyors, up-down counter, and high-speed D/A converter are employed to implement the frequency-to-voltage converter (FVC). Based on the characteristics of successive-approximation technique, the conversion time less than one cycle of input signal can be achieved. Thus, the transient variation on input signal frequency can be detected rapidly. The input signal frequencies ranging from 55 Hz to 2 MHz are tested with the different choices of components and update clock rates. The output ripple voltage is verified so little that no low-pass filter is needed. The experimental and simulation results demonstrate the static characteristics and dynamic responses of proposed FVC.
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Wang, Hongtao. "A Column-Parallel Two-Step Successive Approximation Analog-To-Digital Converter." 2013. https://scholarworks.umass.edu/theses/1091.
Full textAbstract:
The ever-increasing resolution of CMOS imagers has steadily driven the requirements of readout circuitry. As the number of sensors on a chip increases, the bandwidth of the readout circuit must be increased correspondingly to maintain a constant frame rate. Column parallel A/D converters are commonly used to divide the conversions among many converters. However, implementing high-speed, high-resolution A/D converters at the column level is challenging because the entire circuit needs to be as narrow as the sensor.
This thesis presents the design of a 10-bit, one million conversions per second column-parallel A/D converter. A factor of four increase in speed over conventional converters was achieved by combining techniques of successive approximation and two-step subranging in a distributed column-parallel architecture. The speed of the converter makes it suitable to be integrated with a 1-megapixel sensor array providing a frame rate at 1000fps with 11µm pixels in a 0.35µm CMOS technology.
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Lin, Wan-Ting, and 林宛葶. "Low Voltage Successive Approximation ADC with Calibration Technique for Biomedical Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/27223039221762818151.
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碩士<br>長庚大學<br>電子工程研究所<br>95<br>In a biomedical signal detecting system, ADC serves as an important role to translate biomedical signals from analog to digital for the back-end microprocessor to analyze and process. The demand of both resolution and precision of a biomedical signal detecting system is relatively high because the amplitude of biomedical signals is quite small. If the resolution and precision of ADC are too low, we can’t tell the difference of these biomedical signals, which might affect the doctor’s diagnosis.
Based on characteristics of biomedical signals, several methods are used in this thesis to increase the ADC accuracy, which include calibration technique in digital-to-analog converter, the complementary signal generator and the comparator with CDB technique and multi-stage offset cancellation.
In this thesis, a 40KHz 1-volt 50.9uW 12-bit successive approximation ADC has been proposed. The used DAC with calibration technique effectively reduces DNL by simulation results. For biomedical applications, if the ADC input after the instrumentation amplifier is limited to 0.5 volt, DNL and INL are within 1LSB and 8.31LSB, respectively. The signal to noise ratio is 59.82dB and the effective bit resolution is 9.7 bit.
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Ming-LunFan and 范銘倫. "Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/24078815364182330693.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>100<br>This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm.
The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step.
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Lin, Pin-Hong, and 林品宏. "A 160MS/s 10-bit Successive-Approximation Analog-to-Digital Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ng3ba5.
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碩士<br>國立清華大學<br>電機工程學系所<br>106<br>The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC. It combined the redundancy algorithm and the optimization of digital circuit to speed up the conversion. Metal-finger capacitors has smaller capacitance. Then, the area of DAC array can be scaled down and the power consumption can be improved. Application of dynamic logic make ADC become faster. It also make the area smaller then static logic because of less transistors. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhance by channel shunting.
The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1.2V supply voltage. The full rail-to-rail input swing is 1.8V peak to peak. This design achieve signal to noise and distortion ratio of 62.15dB, equivalent to the effective number of bits 10.029.The peak DNL values are -0.01 to +0.01 LSB and the peak INL values are -0.04to +0.04 LSB. The average power consumption is 3.28mW. The area is 90μm×189μm = 0.01701mm2. After digital circuit simplification, the average power consumption becomes 1.851mW and the area becomes 74μm×178μm = 0.01317mm2.
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Liao, I.-Hsuan, and 廖乙璇. "Successive Gaussian Approximation based BP Detection for New Radio Multiple Access." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/pzh74c.
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碩士<br>國立清華大學<br>通訊工程研究所<br>107<br>In this thesis, we propose a multi-user detection (MUD) technique called “Successive Gaussian Approximation based Belief Propagation (SGA-BP) detection with linear pre-filtering”, which can be applied to the new radio multiple access (NR-MA) schemes. With the use of non-orthogonal technique and overloaded transmission, NR-MA schemes have capability to support the requirements of the 5G wireless systems. The concept of SGA-BP detection is to approximate the interference-plus-noise term as a Gaussian random variable and perform iterative SGA-BP, where messages are updated successively during each iteration. By doing so, messages can be delivered efficiently and accurately with low computational complexity. In this thesis, we discuss two candidate schemes of NR-MA to evaluate the performance and potential of SGA-BP detection. We also compare the SGA-BP detection with the GA-BP detection and the minimum mean square error (MMSE) successive interference cancellation (SIC) detection. Simulation results show that SGA-BP detection achieves better performance than the GA-BP detection, and outperforms the MMSE-SIC detection when applied to the MUSA system. For the requirements of massive connections, we also discuss the cases of high overload conditions and a BS with multiple antennas, and again verify the potential of SGA-BP detection with linear pre-filtering.
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LIN, YOU-REN, and 林祐任. "A 12bit Successive Approximation Analog-to-Digital Converter for Electrochemical Analysis." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/p8x27j.
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碩士<br>南臺科技大學<br>電子工程系<br>107<br>As the era progresses towards a smart life, many products are also advancing to include more science and technology, such as in daily necessities, wearable devices, medical supplies and others. However, most of these products require an analog-to-digital converter to change discrete signals into digital forms for analysis.
An electrochemical measuring device is an important bridge of data transmission; thus, it is possible to reduce the device into smaller and portable form, while the medium used in contact should be more affordable, as well as disposable. Cyclic voltammetry of electrochemistry in this study was one of the most commonly used methods. Primarily, a potential function was first applied to generate a current for analysis. The potential scan would start with a positive potential or potential and returned in a cycle after reaching the terminal potential, in which such cycle could allow the plotting of CV for the oxidation reaction. A tri-electrode system was used, where screen printing used three electrodes, which were respectively the working electrode, the reference electrode and the auxiliary electrode.
The 12-bit successive-approximation analog-to-digital converter was used in this study, with the algorithm based on binary search, where the intermediate value was used for comparison and the comparative result was temporarily registered each time, until successively approximated to the exact value of the input voltage drop. The architecture of the analog-to-digital converter included a sample-and-hold circuit, a comparator circuit and a successive-approximation logic control circuit, a control switch circuit and a capacitor array circuit. By double-ended differential input, the system could be effectively shielded from noises and it would be quite helpful for signal accuracy. The capacitor array was consisted of MOM capacitors (Metal-oxide-metal) and used five layers of metal in form of Pillar structure, in order to constitute a small unit capacitance value.
When the sampling frequency is 8.928571429 MHz and clock of 125MHz. The signal-to-noise ratio during pre-simulation was 72.704 dB and the effective bit was 12.3694 bits. SNDR of post-simulation was 47.2578 dB and the effective bit was 8.1425 bits. The circuit layout used a TSMC 0.18μm CMOS process, with a size of 1.2mm x 1.2mm.
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Chien, Chih-Chang, and 簡志昌. "VLSI Design and Research on 10 Bits Successive-Approximation A/D Converter." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/43561598871980445091.
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碩士<br>中原大學<br>電子工程學系<br>88<br>This thesis presents the design and implementation of a 10 bits successive approximation A/D converter. The core circuit blocks of the converter consist of a comparator, charge scaling D/A converter and digital control circuit.
In order to achieve the research goal of low power consumption and competitive chip layout area, three-stage single CMOS inverter amplifier has been used to construct the comparator with techniques of reference voltage memorization and charge injection cancellation. Further, the architecture of two-stage capacitor array with acceptable layout area has been adopted to realize the charge scaling D/A converter. A 13-bits shift register has been designed to provide the control signals for D/A converter, comparator and output stage.
The chip has been implemented in an UMC 0.5mm 2P2M CMOS technology and the core layout area is 430.5mm×805mm. The proposed SAR A/D converter operates at power supply voltage between 3 to 5V and needs 13 clock cycles for each analog data conversion. The measurement result shows that the conversion time is 13ms, DNL is -0.8033 ~ +1.7667 LSB, INL is -0.54~ +8.6667 LSB, and the maximum power consumption is 25mW from a single 5V supply.
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Huang, Yu-Wei, and 黃郁偉. "An 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04137775731994071769.
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碩士<br>國立中興大學<br>電機工程學系所<br>98<br>This thesis designs an analog-to-digital converter (ADC). The architecture is an 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique , and the sample rate of the circuit achieves 1MSample/s based on a TSMC 0.35μm Mixed-Signal 2P4M Polycide 3.3V manufacturing process.
The Chip area of the first SAR-ADC is 1925μm×1579μm , and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz , sample rate is 100KHz , and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V):
Its Differential Non-Linearity error (DNL) is -1LSB~72.986LSB, Integral Non-Linearity error (INL) is -86.961LSB ~ 25.296LSB , SNDR=14.05dB , ENOB=2.04bits , and the whole power consumption is approximately 3.287mW.
The chip area of the second SAR-ADC is 1295μm×1120μm , and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz , sample rate is 100KHz , and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V):
Its Differential Non-Linearity error (DNL) is -1LSB ~ 9.132LSB, Integral Non-Linearity error (INL) is -7.364LSB ~ 20.255LSB , SNDR=27.5dB , ENOB=4.28bits , and the whole power consumption is approximately 2.566mW.