Dissertations / Theses on the topic 'Switched capacitor circuits – Research'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'Switched capacitor circuits – Research.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
Hua, Guichao. "Novel zero-voltage switching techniques for pulse-width-modulated converters." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03242009-040340/.
Full textDarwish, M. K. E.-S. "Switched-capacitor filters for power applications." Thesis, Brunel University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375203.
Full textPeter, Kenneth W. "Integrated interface circuits for switched capacitor sensors." Thesis, University of Edinburgh, 1991. http://hdl.handle.net/1842/15637.
Full textBereza, Bill Carleton University Dissertation Engineering Electrical. "A switched-capacitor circuit technique used to measure capacitor mismatch and explore capacitor and opamp nonlinearity." Ottawa, 1988.
Find full textYassine, Hatem Mahmoud. "Design and realization of switched capacitor filters." Thesis, London South Bank University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.480856.
Full textWong, Kim Fai. "Speed enhancement techniques for comparator-based switched-capacitor circuits." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2493500.
Full textGoette, Josef. "Contributions to the noise-analysis of switched-capacitor circuits /." Konstanz : Hartung-Gorre, 1994. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=389191802X.
Full textGoette, Josef. "Contributions to the noise-analysis of switched-capacitor circuits /." Zürich, 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10214.
Full textGustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.
Full textBoo, Hyun Ho. "Virtual ground reference buffer technique in switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99812.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (pages 121-125).
The performance of switched-capacitor circuits depends highly on the op-amp specifications. In conventional designs, trade-offs in speed, noise, and settling accuracy make it difficult to implement power-efficient switched-capacitor circuits. The problem originates from the inverse relationship between the feedback factor and the signal gain. This thesis proposes the virtual ground reference buffer technique that enhances performance by improving the feedback factor of the op-amp without affecting signal gain. A key concept in the technique is the bootstrapping action of level-shifting buffers. It exploits op-amp-based circuits whose principles are very well understood and the design techniques are mature. The solution ultimately relaxes the required op-amp requirements including unity-gain bandwidth, noise, offset voltage and open-loop gain that would otherwise result in complex design and high power consumption. The concept is demonstrated in a 12-b 250MS/s pipelined ADC.
by Hyun Ho Boo.
Ph. D.
Leonardi, Suryanto Felix 1958, and Suryanto Felix 1958 Leonardi. "Switched-capacitor network synthesis using leapfrog method." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/558107.
Full textSepke, Todd C. (Todd Christopher) 1975. "Comparator design and analysis for comparator-based switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38925.
Full textIncludes bibliographical references (p. 177-182).
The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that eliminates the need for high gain op-amps in the signal path is proposed. The CBSC technique applies to switched-capacitor circuits in general and is compatible with most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 [mu]m CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. Non-stationary noise analysis techniques are applied to circuit analysis problems for white noise sources in a framework consistent with the more familiar wide-sense-stationary techniques. The design of a low-noise threshold detection comparator using a preamplifier is discussed.
(cont.) Assuming the preamplifier output is reset between decisions, it is shown that. for a given noise and speed requirement, a band-limiting preamplifier is the lowest power implementation. Noise analysis techniques are applied to the prototype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD) estimate for the prototype pipeline ADC. Theoretical predictions and measured results of the input referred noise PSD for the prototype are compared showing that the noise contribution of the preamplifier dominates the overall noise performance.
by Todd C. Sepke.
Ph.D.
Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
Full textJan, Ying-Wei. "A switched-capacitor analysis metal-oxide-silicon circuit simulator." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181163717.
Full textNg, Wai Hon. "Design of CMOS wide-band switched-capacitor bandpass filters /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20NG.
Full textEichenberger, Christoph. "Charge injection in MOS-integrated sample-and-hold and switched-capacitor circuits /." Zürich, 1989. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=8969.
Full textNaik, Priti M. (Priti Manher) 1973. "Low voltage, low power CMOS operational amplifier design for switched capacitor circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9948.
Full textUzun, Orhun Aras. "Speed, Power Efficiency, and Noise Improvements for Switched Capacitor Voltage Converters." Scholar Commons, 2017. http://scholarcommons.usf.edu/etd/6970.
Full textWang, Peng Chong. "Design of wideband switched-capacitor delta-sigma analog-to-digital converters /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20WANG.
Full textHarbour, Kenton Dean. "A data acquisition system with switched capacitor sample-and-hold." Thesis, Kansas State University, 1986. http://hdl.handle.net/2097/15269.
Full textSerra, Hugo Alexandre de Andrade. "Design of switched-capacitor filters using low gain amplifiers." Master's thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8214.
Full textAnalog filters are extremely important blocks in several electronic systems such as RF transceivers or sigma delta modulators. They allow selecting between signals with different frequency and eliminating unwanted signals. In modern deep-submicron CMOS technologies the intrinsic gain of the transistors is low and has a large variability, making the design of moderate and high gain amplifiers extremely difficult. The objective of this thesis is to study switched-capacitor (SC) circuits based on the low-pass and band-pass Sallen-Key topologies, since they do not require high gain amplifiers. The strategy used to achieve this objective is to replace the operational amplifier (opamp) with a voltage buffer. Doing this simplifies the design of the amplifier although it also eliminates the virtual ground node from the circuit. Without this node parasitic insensitive SC networks cannot be used. Due to modern parasitic extraction software that can reliably predict the values of parasitic capacitances, the historical disadvantage of parasitic sensitive SC networks (parallel SC) is no longer critical, allowing its influence to be compensated during the design process. Different types of switches were simulated to determine the one with the least nonlinear effects. Two techniques (common mode voltage adjustment and source degeneration) were used to reduce the distortion introduced by the buffers. Low-pass (second and sixth order) and band-pass (second and fourth order) SC filters were simulated in differential configuration in standard 130 nm CMOS technology, having obtained for the low-pass filter a distortion of -62 dB for the biquad section and -54 dB for the sixth-order filter, for a cutoff frequency of 1MHz and when operating at 100 MHz of clock frequency. The total power consumption was 986 W and 5.838 mW, respectively.
Kwan, Jonathan Carleton University Dissertation Engineering Electrical. "Noise analysis and simulation of switched-capacitor circuits using a continuous time circuit simulator." Ottawa, 1988.
Find full textRidley, Raymond Bryan. "A new small-signal model for current-mode control." access full-text online access from Digital dissertation consortium, 1990. http://libweb.cityu.edu.hk/cgi-bin/er/db/ddcdiss.pl?9116643.
Full textChan, Chit Sang. "Bi-directional integrated charge pump with switching low dropout regulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20CHANC.
Full textIncludes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.
Yadhati, Vennela. "A comparative study of capacitor voltage balancing techniques for flying capacitor multi-level power electronic converters." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2010. http://scholarsmine.mst.edu/thesis/pdf/Yadhati_09007dcc807d2cc9.pdf.
Full textVita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed July 26, 2010) Includes bibliographical references (p. 96-102).
Baptista, Acácio João Galhardo. "Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies." Doctoral thesis, FCT - UNL, 2009. http://hdl.handle.net/10362/2619.
Full textSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals.
Hansmann, Chirstine Henriette. "Active capacitor voltage stabilisation in a medium-voltage flying-capacitor multilevel active filter." Thesis, Stellenbosch : University of Stellenbosch, 2005. http://hdl.handle.net/10019.1/1762.
Full textA switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.
U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.
Full textBalasubramaniam, Harish [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Roland [Akademischer Betreuer] Thewes. "Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators / Harish Balasubramaniam. Betreuer: Klaus Hofmann ; Roland Thewes." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2014. http://d-nb.info/1111112207/34.
Full textYing, Tianrui. "Area efficient charge pumps and post low dropout regulators /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20YING.
Full textU, Seng-Pan. "多率開關電容內插技術及其在超高頻模擬前端濾波的應用." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1637078.
Full textVakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
Full textBezerra, Thiago Brito. "DESENVOLVIMENTO DE UM CONVERSOR A/D INTEGRADOR COM FAIXA DE ENTRADA E RESOLUÇÃO PROGRAMÁVEL A CAPACITOR CHAVEADO." Universidade Federal do Maranhão, 2012. http://tedebc.ufma.br:8080/jspui/handle/tede/486.
Full textCoordenação de Aperfeiçoamento de Pessoal de Nível Superior
Programmable integrated circuits enable its adjustment after fabrication to fit more than one application within a certain set of applications. A programmable measurement system can be applied to the measurement of different quantities involving a set of sensors with different signal characteristics and employing a single analog-to-digital converter (ADC). The output signal range for each sensor should be adjusted to be as close to the input range of the ADC as possible, to ensure maximum measurement quality. One solution to implement the adjustment on the signal range is the use of a measurement system with programmable conditioning circuit. In this work, it is proposed to design an ADC integrated circuit whose input range is adjusted to the signal level at the output of the sensor in order to avoid amplification stages in a signal conditioning circuit. For this adjustment, the input of the converter should be programmable, making it more compatible with various sensors with different characteristics. The developed ADC also allows the configuration of the converter resolution, enabling the designer to exploit trade-offs between resolution and conversion speed for a given application. The ADC is a switched capacitor integrating converter and it was designed for the AMS 0.35 μm CMOS process.
Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequarem a mais de uma aplicação dentro de um conjunto determinado de aplicações. Um sistema de medição programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para realizar o ajuste da faixa do sinal é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho de dissertação, propõe-se o projeto de um conversor analógico-digital em circuito integrado em que a faixa de entrada pode ser ajustada ao nível de sinal na saída do sensor, com a finalidade de evitar estágios de amplificação do sinal em um circuito de condicionamento. Para tal ajuste, a entrada do conversor deverá ser programável, o que o torna mais compatível com diversos sensores com características diferentes. O circuito proposto também possibilita a definição da resolução do conversor o que permite a escolha de compromisso entre resolução e velocidade de conversão, dependendo da aplicação. O conversor A/D é do tipo integrador a capacitores chaveados e foi projetado, em nível de transistor e leiaute, para o processo AMS 0,35 m CMOS.
Nunes, Rafael Oliveira. "CONVERSOR ANALÓGICO-DIGITAL INTEGRADOR A CAPACITOR CHAVEADO COM FAIXA DE ENTRADA PROGRAMÁVEL." Universidade Federal do Maranhão, 2010. http://tedebc.ufma.br:8080/jspui/handle/tede/456.
Full textCoordenação de Aperfeiçoamento de Pessoal de Nível Superior
Programmable integrated circuits for specified applications enable its adjustment after fabrication, to fit more than one application within a certain set of applications. These circuits are flexible, but could lose in performance when compared to other circuit constructed to serve only a specific application. A programmable system can be applied to measurements involving a set of sensors with different characteristics of signals and an analog-to-digital converter. The signal range for each sensor should be adjusted as close to the input range of analog-digital converter as possible, to ensure the measurement with the full range of the signal. A solution for ensure the adjustable ranges is the employ a measurement system with programmable conditioning circuit. In this work, an analog-to-digital converter with adjustable input range is proposed, providing, equivalently, an adjustable gain value to the analog input signal. The gain values compose a minimum set to ensure no loss of measurement range of the signal, with loss of resolution within an acceptable limit. The proposed converter is a discrete integrator type with switched capacitor circuits. Behavioral and SPICE simulations were performed to validate the proposed converter.
Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequar a mais de uma aplicação dentro de um conjunto determinado de aplicações. Esses circuitos são flexíveis, mas podem perder em desempenho quando comparado a outro circuito fabricado para servir a apenas uma aplicação específica. Um sistema programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para garantir o ajuste das faixas é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho, um conversor analógico-digital com faixa de entrada ajustável é proposto, proporcionando, de forma equivalente, um valor de ganho ajustável ao sinal analógico de entrada. Os valores de ajuste pertencem a um conjunto mínimo de ganhos definidos para garantir que não haja perda da faixa de medição do sinal, com perda de resolução dentro de um limite aceitável. O conversor proposto é do tipo integrador discreto com circuitos a capacitor chaveado. Simulações comportamentais e em SPICE foram realizadas de forma a validar o conversor proposto.
Shah, Umer. "Novel RF MEMS Devices Enabled by Three-Dimensional Micromachining." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-143757.
Full textQC 20140328
Gulpinar, Feyzullah. "A non-conventional multilevel flying-capacitor converter topology." Thesis, 2014. http://hdl.handle.net/1805/6299.
Full textThis research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.
Bidari, Emad. "Low-voltage switched-capacitor circuits." Thesis, 1998. http://hdl.handle.net/1957/33450.
Full textGraduation date: 1999
Hershberg, Benjamin Poris. "Ring amplification for switched capacitor circuits." Thesis, 2012. http://hdl.handle.net/1957/31112.
Full textGraduation date: 2012
Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013
Liu, Jie-Cheng, and 劉皆成. "Design of nonlinear analog switched capacitor circuits." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/12972696032705049122.
Full textHUANG, XIU-TING, and 黃秀廷. "Design techniques for nonlinear switched-capacitor circuits." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/32708403679923495990.
Full textYesilyurt, Ayse Gul. "Novel switched-capacitor circuits for delta-sigma modulators." Thesis, 1997. http://hdl.handle.net/1957/34330.
Full textGraduation date: 1997
Nilchi, Alireza. "Low-power Charge-pump Based Switched-capacitor Circuits." Thesis, 2013. http://hdl.handle.net/1807/35917.
Full textYoshizawa, Hirokazu. "High-linearity switched-capacitor circuits in digital CMOS technologies." Thesis, 1997. http://hdl.handle.net/1957/33627.
Full textGraduation date: 1998
Chen, Po-Fung, and 陳柏逢. "Switched-capacitor Circuits in 65nm Power Management Integrated Chip." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/82341384554733332284.
Full text國立交通大學
電機學院IC設計產業專班
96
In recent years, the advanced technology continues to decrease the input supply voltage for effectively reducing the power consumption of the chip. Especially, the concept of system-on-chip (Soc) includes multiple digital and analog blocks under low input supplying voltage. However, the low input supplying voltage is converted from a high supplying voltage by the buck DC-DC converter. Thus, the conversion efficiency may be deteriorated due to the large leakage of conversion. That is the buck DC-DC converter consumes much energy in the conversion process. The major reason is that the inefficient design of power conversion between different voltages. In this thesis, switched-capacitor circuits are utilized to convert the high supplying voltage to a regulated output voltage for controlling the controller of the buck DC-DC converter. Owing to the efficient conversion, the power dissipation in the controller can be effectively reduced. After the efficient conversion, the controller is supplied by a low supplying voltage, which is 1.2V. The power consumption of the controller is minimized and the quiescent current of the controller is smaller than that of the conventional designs. Furthermore, the performance of the buck DC-DC converter with low-supplying controller is deteriorated by the low closed-loop gain. A new error amplifier is proposed to increase the low-frequency gain to about 80dB under the supplying voltage 1.2V. In other words, the performance of line and load regulations can be raised to meet to the specifications of the wireless applications. Simulation results demonstrate the correctness and performance of the designs. In the thesis, the DC-DC converter provides two regulated voltages 1.8V and 1.2V without the demand of high input supplying voltage in the controller.
Shen, Min. "Analysis and measurement of charge injection in switched-capacitor circuits." Thesis, 1998. http://hdl.handle.net/1957/33942.
Full textGraduation date: 1998
Huang, Chien-Chih, and 黃健智. "Variation-Aware Placement of Common-Centroid Unit Capacitor Array for Switched-Capacitor Analog Circuits." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/92649422728173215665.
Full text國立中央大學
電機工程學系
104
The key performance of many analog integrated circuits, such as switched-capacitor integrator and analog-to-digital converter, are directly related to their accurate capacitance ratios. The accuracy of capacitance ratio is affected by the systematic and random variations of manufacturing processes more significantly when the manufacturing processes continue to shrink. The variation of capacitance ratio, which can be alleviated by paralleling unit capacitors, is then extended to the capacitor array placement problem. This dissertation is devoted to establish the relationship between the capacitor array placement and the capacitance ratio variation, and to propose the partition-based algorithm to form the capacitor array placement. Placing a unit capacitor at the center of a partitioned sub-array can achieve the lowest variations both systematic and random will be proved. Based on the approach to placing unit capacitor at the center of partitioned sub-array, the capacitor array placement is effectively generated and satisfied the coincidence, symmetry, and dispersion rules. Finally, the proposed algorithm is further applied to the placement of a binary-weighted capacitor array, which is used in successive-approximation register (SAR) analog-to-digital converters (ADCs). Experimental results show that the binary-weighted capacitor array placement can achieve less variation on binary-weighted continued ratio, higher linearity performance, and shorter placement generation time than the state-of-the-art.
LIN, XIN-BIN, and 林信斌. "Computer-aided analysis of switched-capacitor circuits via symbolic approach." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/16348893980578788393.
Full textHuang, Yunteng. "Design techniques of high-performance switched capacitor circuits in the presence of component imperfections." Thesis, 1997. http://hdl.handle.net/1957/34477.
Full textGraduation date: 1997
Lao, Paul A. "Current-feedthrough cancellation techniques in switched-current circuits." Thesis, 1990. http://hdl.handle.net/1957/37719.
Full textLuo, Pei-Wen, and 羅珮大. "Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/57014745892941669126.
Full text國立中央大學
電機工程研究所
99
As semiconductor technology continues to shrink, the process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becoming an important design issue. The key performance of many analog circuits is directly related to accurate capacitor ratios. In general, capacitor mismatches caused by process variation can be classified as two types: random mismatch and systematic mismatch. To analyze process variation in early design stages, process variation information must be input to a circuit simulator, where Monte-Carlo analysis is commonly employed to find out process variation information and to eliminate the random mismatch in the early stages of design. On the other hand, systematic mismatch is mainly due to asymmetrical layout and processing gradients. The common centroid approach is commonly employed to reduce device mismatches caused by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process. This study addresses the impact of capacitor correlation on the yield enhancement of switched-capacitor integrated circuits. The relationships between correlation and mismatch and between correlation and variation of capacitor ratio are also presented. Therefore, both mismatch and variation of capacitor ratio can be expressed in term of capacitor correlation. Based on a spatial correlation model, this study proposes a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yieldperformance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common centroid approach. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed-up the time to market.