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1
Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.
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Bereza, Bill Carleton University Dissertation Engineering Electrical. "A switched-capacitor circuit technique used to measure capacitor mismatch and explore capacitor and opamp nonlinearity." Ottawa, 1988.
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Darwish, M. K. E.-S. "Switched-capacitor filters for power applications." Thesis, Brunel University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375203.
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Peter, Kenneth W. "Integrated interface circuits for switched capacitor sensors." Thesis, University of Edinburgh, 1991. http://hdl.handle.net/1842/15637.
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This thesis reports an investigation into integrated interface circuits for switched capacitor sensors for application in industrial process control instrumentation networks. Three circuits are presented: an absolute capacitance to voltage converter; a capacitance ratio to frequency ratio converter; and a capacitance ratio to voltage ratio converter. Of the circuits, the first two are subject to most thorough investigation with the capacitance ratio to frequency ratio converter being of particular interest. This circuit is based upon a switched capacitor, frequency controlled, negative feedback loop which permits implementation with modest quality analogue components, such as are provided with a standardcell ASIC CMOS process. Initial investigations, accomplished with discrete component implementations of the interface circuits, reveal a significant departure in behaviour from that predicted by firstorder analysis. Switch induced chargefeedthrough is shown to be responsible for the deviation. In addition, parasitic induced jitter and frequency locking are identified as a second source of error. The three interface circuits are implemented as an integrated circuit using the European Silicon Structures (ES2) ASIC CMOS process, with a modification to permit the inclusion of fullcustom designed, chargefeedthrough compensated switches. This implementation exhibits greatly reduced chargefeedthrough, and circuit behaviour is in accordance with a modification to the firstorder analysis that includes the effects of chargefeedthrough. Importantly, no frequency locking and much reduced jitter is observed. Significantly, linear performance is obtained for the capacitance ratio to frequency ratio converter over a 20 to 1 capacitance range, with operation demonstrable down to 5pF sensor capacitance.
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Yassine, Hatem Mahmoud. "Design and realization of switched capacitor filters." Thesis, London South Bank University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.480856.
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Goette, Josef. "Contributions to the noise-analysis of switched-capacitor circuits /." Konstanz : Hartung-Gorre, 1994. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=389191802X.
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Goette, Josef. "Contributions to the noise-analysis of switched-capacitor circuits /." Zürich, 1993. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=10214.
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Wong, Kim Fai. "Speed enhancement techniques for comparator-based switched-capacitor circuits." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2493500.
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Boo, Hyun Ho. "Virtual ground reference buffer technique in switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99812.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 121-125).
The performance of switched-capacitor circuits depends highly on the op-amp specifications. In conventional designs, trade-offs in speed, noise, and settling accuracy make it difficult to implement power-efficient switched-capacitor circuits. The problem originates from the inverse relationship between the feedback factor and the signal gain. This thesis proposes the virtual ground reference buffer technique that enhances performance by improving the feedback factor of the op-amp without affecting signal gain. A key concept in the technique is the bootstrapping action of level-shifting buffers. It exploits op-amp-based circuits whose principles are very well understood and the design techniques are mature. The solution ultimately relaxes the required op-amp requirements including unity-gain bandwidth, noise, offset voltage and open-loop gain that would otherwise result in complex design and high power consumption. The concept is demonstrated in a 12-b 250MS/s pipelined ADC.
by Hyun Ho Boo.
Ph. D.
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Leonardi, Suryanto Felix 1958, and Suryanto Felix 1958 Leonardi. "Switched-capacitor network synthesis using leapfrog method." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/558107.
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Kwan, Jonathan Carleton University Dissertation Engineering Electrical. "Noise analysis and simulation of switched-capacitor circuits using a continuous time circuit simulator." Ottawa, 1988.
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Sepke, Todd C. (Todd Christopher) 1975. "Comparator design and analysis for comparator-based switched-capacitor circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38925.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 177-182).
The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that eliminates the need for high gain op-amps in the signal path is proposed. The CBSC technique applies to switched-capacitor circuits in general and is compatible with most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 [mu]m CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. Non-stationary noise analysis techniques are applied to circuit analysis problems for white noise sources in a framework consistent with the more familiar wide-sense-stationary techniques. The design of a low-noise threshold detection comparator using a preamplifier is discussed.
(cont.) Assuming the preamplifier output is reset between decisions, it is shown that. for a given noise and speed requirement, a band-limiting preamplifier is the lowest power implementation. Noise analysis techniques are applied to the prototype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD) estimate for the prototype pipeline ADC. Theoretical predictions and measured results of the input referred noise PSD for the prototype are compared showing that the noise contribution of the preamplifier dominates the overall noise performance.
by Todd C. Sepke.
Ph.D.
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Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
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Jan, Ying-Wei. "A switched-capacitor analysis metal-oxide-silicon circuit simulator." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181163717.
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Ng, Wai Hon. "Design of CMOS wide-band switched-capacitor bandpass filters /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20NG.
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Eichenberger, Christoph. "Charge injection in MOS-integrated sample-and-hold and switched-capacitor circuits /." Zürich, 1989. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=8969.
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Naik, Priti M. (Priti Manher) 1973. "Low voltage, low power CMOS operational amplifier design for switched capacitor circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9948.
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Uzun, Orhun Aras. "Speed, Power Efficiency, and Noise Improvements for Switched Capacitor Voltage Converters." Scholar Commons, 2017. http://scholarcommons.usf.edu/etd/6970.
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Switched-capacitor (SC) DC-DC converters provide a viable solution for on-chip DC-DC conversion as all the components required are available in most processes. However, power efficiency, power density characteristics of SC converters are adversely affected by the integration, and characteristics such as response time and noise can be further improved with an on-chip converter. An analysis on speed, power efficiency, and noise performance of SC converters is presented and verified using simulations. Based on the analysis two techniques, converter-gating and adaptive gain control, are developed. Converter-gating uses a combination of smaller stages and reconfiguration during transient load steps to improve the power efficiency and transient response speed. The stages of the converter are also distributed across the die to reduce the voltage drop and noise on power supply. Adaptive gain control improves transient response through manipulation of the gain of the integrator in the control loop. This technique focuses on improving the response time during converter reconfiguration and offers a general solution to transient response improvement instead of focusing on the worst case scenario which is usually the largest transient load step. The techniques developed are then implemented in ST 28nm FDSOI process and test methodologies are discussed.
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Wang, Peng Chong. "Design of wideband switched-capacitor delta-sigma analog-to-digital converters /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20WANG.
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Harbour, Kenton Dean. "A data acquisition system with switched capacitor sample-and-hold." Thesis, Kansas State University, 1986. http://hdl.handle.net/2097/15269.
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Ridley, Raymond Bryan. "A new small-signal model for current-mode control." access full-text online access from Digital dissertation consortium, 1990. http://libweb.cityu.edu.hk/cgi-bin/er/db/ddcdiss.pl?9116643.
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Chan, Chit Sang. "Bi-directional integrated charge pump with switching low dropout regulator /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20CHANC.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.
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Serra, Hugo Alexandre de Andrade. "Design of switched-capacitor filters using low gain amplifiers." Master's thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8214.
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Dissertação para obtenção do Grau de Mestre em
Engenharia Electrotécnica e de ComputadoresAnalog filters are extremely important blocks in several electronic systems such as RF transceivers or sigma delta modulators. They allow selecting between signals with different frequency and eliminating unwanted signals. In modern deep-submicron CMOS technologies the intrinsic gain of the transistors is low and has a large variability, making the design of moderate and high gain amplifiers extremely difficult. The objective of this thesis is to study switched-capacitor (SC) circuits based on the low-pass and band-pass Sallen-Key topologies, since they do not require high gain amplifiers. The strategy used to achieve this objective is to replace the operational amplifier (opamp) with a voltage buffer. Doing this simplifies the design of the amplifier although it also eliminates the virtual ground node from the circuit. Without this node parasitic insensitive SC networks cannot be used. Due to modern parasitic extraction software that can reliably predict the values of parasitic capacitances, the historical disadvantage of parasitic sensitive SC networks (parallel SC) is no longer critical, allowing its influence to be compensated during the design process. Different types of switches were simulated to determine the one with the least nonlinear effects. Two techniques (common mode voltage adjustment and source degeneration) were used to reduce the distortion introduced by the buffers. Low-pass (second and sixth order) and band-pass (second and fourth order) SC filters were simulated in differential configuration in standard 130 nm CMOS technology, having obtained for the low-pass filter a distortion of -62 dB for the biquad section and -54 dB for the sixth-order filter, for a cutoff frequency of 1MHz and when operating at 100 MHz of clock frequency. The total power consumption was 986 W and 5.838 mW, respectively.
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Hua, Guichao. "Novel zero-voltage switching techniques for pulse-width-modulated converters." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03242009-040340/.
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Yadhati, Vennela. "A comparative study of capacitor voltage balancing techniques for flying capacitor multi-level power electronic converters." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2010. http://scholarsmine.mst.edu/thesis/pdf/Yadhati_09007dcc807d2cc9.pdf.
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Thesis (M.S.)--Missouri University of Science and Technology, 2010.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed July 26, 2010) Includes bibliographical references (p. 96-102).
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U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.
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Hansmann, Chirstine Henriette. "Active capacitor voltage stabilisation in a medium-voltage flying-capacitor multilevel active filter." Thesis, Stellenbosch : University of Stellenbosch, 2005. http://hdl.handle.net/10019.1/1762.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.
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Baptista, Acácio João Galhardo. "Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies." Doctoral thesis, FCT - UNL, 2009. http://hdl.handle.net/10362/2619.
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Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de
Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals.
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Ying, Tianrui. "Area efficient charge pumps and post low dropout regulators /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20YING.
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Balasubramaniam, Harish [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Roland [Akademischer Betreuer] Thewes. "Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators / Harish Balasubramaniam. Betreuer: Klaus Hofmann ; Roland Thewes." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2014. http://d-nb.info/1111112207/34.
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Bezerra, Thiago Brito. "DESENVOLVIMENTO DE UM CONVERSOR A/D INTEGRADOR COM FAIXA DE ENTRADA E RESOLUÇÃO PROGRAMÁVEL A CAPACITOR CHAVEADO." Universidade Federal do Maranhão, 2012. http://tedebc.ufma.br:8080/jspui/handle/tede/486.
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Programmable integrated circuits enable its adjustment after fabrication to fit more than one application within a certain set of applications. A programmable measurement system can be applied to the measurement of different quantities involving a set of sensors with different signal characteristics and employing a single analog-to-digital converter (ADC). The output signal range for each sensor should be adjusted to be as close to the input range of the ADC as possible, to ensure maximum measurement quality. One solution to implement the adjustment on the signal range is the use of a measurement system with programmable conditioning circuit. In this work, it is proposed to design an ADC integrated circuit whose input range is adjusted to the signal level at the output of the sensor in order to avoid amplification stages in a signal conditioning circuit. For this adjustment, the input of the converter should be programmable, making it more compatible with various sensors with different characteristics. The developed ADC also allows the configuration of the converter resolution, enabling the designer to exploit trade-offs between resolution and conversion speed for a given application. The ADC is a switched capacitor integrating converter and it was designed for the AMS 0.35 μm CMOS process.
Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequarem a mais de uma aplicação dentro de um conjunto determinado de aplicações. Um sistema de medição programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para realizar o ajuste da faixa do sinal é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho de dissertação, propõe-se o projeto de um conversor analógico-digital em circuito integrado em que a faixa de entrada pode ser ajustada ao nível de sinal na saída do sensor, com a finalidade de evitar estágios de amplificação do sinal em um circuito de condicionamento. Para tal ajuste, a entrada do conversor deverá ser programável, o que o torna mais compatível com diversos sensores com características diferentes. O circuito proposto também possibilita a definição da resolução do conversor o que permite a escolha de compromisso entre resolução e velocidade de conversão, dependendo da aplicação. O conversor A/D é do tipo integrador a capacitores chaveados e foi projetado, em nível de transistor e leiaute, para o processo AMS 0,35 m CMOS.
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Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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U, Seng-Pan. "多率開關電容內插技術及其在超高頻模擬前端濾波的應用." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1637078.
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Nunes, Rafael Oliveira. "CONVERSOR ANALÓGICO-DIGITAL INTEGRADOR A CAPACITOR CHAVEADO COM FAIXA DE ENTRADA PROGRAMÁVEL." Universidade Federal do Maranhão, 2010. http://tedebc.ufma.br:8080/jspui/handle/tede/456.
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Programmable integrated circuits for specified applications enable its adjustment after fabrication, to fit more than one application within a certain set of applications. These circuits are flexible, but could lose in performance when compared to other circuit constructed to serve only a specific application. A programmable system can be applied to measurements involving a set of sensors with different characteristics of signals and an analog-to-digital converter. The signal range for each sensor should be adjusted as close to the input range of analog-digital converter as possible, to ensure the measurement with the full range of the signal. A solution for ensure the adjustable ranges is the employ a measurement system with programmable conditioning circuit. In this work, an analog-to-digital converter with adjustable input range is proposed, providing, equivalently, an adjustable gain value to the analog input signal. The gain values compose a minimum set to ensure no loss of measurement range of the signal, with loss of resolution within an acceptable limit. The proposed converter is a discrete integrator type with switched capacitor circuits. Behavioral and SPICE simulations were performed to validate the proposed converter.
Circuitos integrados programáveis possibilitam o seu ajuste após a fabricação, para se adequar a mais de uma aplicação dentro de um conjunto determinado de aplicações. Esses circuitos são flexíveis, mas podem perder em desempenho quando comparado a outro circuito fabricado para servir a apenas uma aplicação específica. Um sistema programável pode ser aplicado em medições que envolvam um conjunto de sensores com características diferentes de sinais e um conversor analógico-digital. A faixa de sinal em cada sensor deve ser ajustada o mais próximo da faixa de entrada do conversor analógico-digital, para garantir a medição com a faixa completa do sinal. Uma solução para garantir o ajuste das faixas é o uso de um sistema de medição com circuito de condicionamento programável. Neste trabalho, um conversor analógico-digital com faixa de entrada ajustável é proposto, proporcionando, de forma equivalente, um valor de ganho ajustável ao sinal analógico de entrada. Os valores de ajuste pertencem a um conjunto mínimo de ganhos definidos para garantir que não haja perda da faixa de medição do sinal, com perda de resolução dentro de um limite aceitável. O conversor proposto é do tipo integrador discreto com circuitos a capacitor chaveado. Simulações comportamentais e em SPICE foram realizadas de forma a validar o conversor proposto.
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Gai, Yingkun. "Noise analysis for switched-capacitor circuitry." [Ames, Iowa : Iowa State University], 2008.
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Zhang, Xuan. "Switched Capacitor Circuit Based Isolated Power Converters." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461327493.
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Pun, C. K. "Frequency analysis of switched capacitor networks." Thesis, University of Hull, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383753.
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Shah, Umer. "Novel RF MEMS Devices Enabled by Three-Dimensional Micromachining." Doctoral thesis, KTH, Mikro- och nanosystemteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-143757.
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This thesis presents novel radio frequency microelectromechanical (RF MEMS) circuits based on the three-dimensional (3-D) micromachined coplanar transmission lines whose geometry is re-configured by integrated microelectromechanical actuators. Two types of novel RF MEMS devices are proposed. The first is a concept of MEMS capacitors tuneable in multiple discrete and well-defined steps, implemented by in-plane moving of the ground side-walls of a 3-D micromachined coplanar waveguide transmission line. The MEMS actuators are completely embedded in the ground layer of the transmission line, and fabricated using a single-mask silicon-on-insulator (SOI) RF MEMS fabrication process. The resulting device achieves low insertion loss, a very high quality factor, high reliability, high linearity and high self actuation robustness. The second type introduces two novel concepts of area efficient, ultra-wideband, MEMS-reconfigurable coupled line directional couplers, whose coupling is tuned by mechanically changing the geometry of 3-D micromachined coupled transmission lines, utilizing integrated MEMS electrostatic actuators. The coupling is achieved by tuning both the ground and the signal line coupling, obtaining a large tuneable coupling ratio while maintaining an excellent impedance match, along with high isolation and a very high directivity over a very large bandwidth. This thesis also presents for the first time on RF nonlinearity analysis of complex multi-device RF MEMS circuits. Closed-form analytical formulas for the IIP3 of MEMS multi-device circuit concepts are derived. A nonlinearity analysis, based on these formulas and on measured device parameters, is performed for different circuit concepts and compared to the simulation results of multi-device conlinear electromechanical circuit models. The degradation of the overall circuit nonlinearity with increasing number of device stages is investigated. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a highest overall IIP3 for the whole circuit.The thesis further investigates un-patterned ferromagnetic NiFe/AlN multilayer composites used as advanced magnetic core materials for on-chip inductances. The approach used is to increase the thickness of the ferromagnetic material without increasing its conductivity, by using multilayer NiFe and AlN sandwich structure. This suppresses the induced currents very effectively and at the same time increases the ferromagnetic resonance, which is by a factor of 7.1 higher than for homogeneous NiFe layers of same thickness. The so far highest permeability values above 1 GHz for on-chip integrated un-patterned NiFe layers were achieved.QC 20140328
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Lim, Seungbum. "A Merged two-stage power conversion architecture with switched capacitor circuit for an LED driver module." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75662.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 71).
In a power converter specified to convert from wide-range and high-level DC voltage or AC line voltage to low-level DC voltage, satisfying high efficiency, high power density, and high power factor is challenging because of the higher device stress and difficulty of maintaining ZVS/ZCS conditions. Our purpose of the proposed two-stage power conversion architecture is to manage this high peak voltage stress and widely-varying operating conditions and to reduce dissipation by placing a switched capacitor pre-regulator stage in front of a very high frequency DC-DC converter stage. Our proposed two-stage architecture has been designed, built, and tested.
by Seungbum Lim.
S.M.
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Bin, Mohd Rozlan Mohd Helmy Hakimie. "DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications." Thesis, Brunel University, 2017. http://bura.brunel.ac.uk/handle/2438/16009.
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This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for low power applications. The proposed circuit has distinct features of both voltage boost-up and near sinusoidal (multi-level/staircase) AC output voltage. The main idea is to utilise a simple circuit technique called resonant-based Double Switch Single Capacitor Switched-Capacitor (DSSC SCC) with variable duty cycle Pulse Width Modulation (PWM) control technique in such a way that multi-level voltage can be realised across a capacitor. In order to show the superiority of the applied technique, comparisons with other techniques/circuits configurations are presented. The circuit technique can significantly reduce the number of multiple stages of switched-capacitor circuit cells of the recent switched-capacitor multi-level inverter topology. The proposed inverter (with integrated DSSC SCC technique) can generate a line-frequency with 13-levels near sinusoidal AC output voltage with low total harmonics distortion. The output voltage can be achieved with the least number of components use and only a single DC source is used as an input. The proposed inverter topology is also reviewed against other inverter-based switched-capacitor circuit topology and the well-known multi-level inverter topology. The proposed inverter has shown a tremendous reduction in the total harmonics distortion and circuit component count in comparison with the recent Switched-Capacitor Boost multi-level inverter and the classical Cascaded H-Bridge multi-level inverter. Mathematical analysis shows the design of the proposed inverter and PSPICE simulation result to verify the design is also presented. The practical experiment implementation of the proposed system is presented and proves the correct operation of the proposed inverter topology by showing consistency between simulation results and practical results.
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Hernandez, Garduno David. "Analog integrated circuit design techniques for high-speed signal processing in communications systems." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1104.
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Sun, J. (Jia). "Speeding up the settling of switched-capacitor amplifier blocks in analog-to-digital converters." Doctoral thesis, Oulun yliopisto, 2019. http://urn.fi/urn:isbn:9789526223902.
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Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active componentsTiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja
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Yao, Chengcheng Yao. "Semiconductor Galvanic Isolation Based Onboard Vehicle Battery Chargers." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1513586255613963.
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Suciu, Constantin. "Switch mode emulation of large value capacitors in the rotor circuit to improve the induction motor performance." Thesis, Nottingham Trent University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314331.
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Hutsel, Brian T. Kovaleski Scott D. "Runtime and jitter of a laser triggered gas switch." Diss., Columbia, Mo. : University of Missouri--Columbia, 2008. http://hdl.handle.net/10355/5783.
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The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Title from PDF of title page (University of Missouri--Columbia, viewed on September 24, 2009). Thesis advisor: Dr. Scott Kovaleski. Includes bibliographical references.
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Khan, Shehryar, and Muhammad Asfandyar Awan. "Study on Zero-Crossing-Based ADCs for Smart Dust Applications." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065.
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The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.
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Hodzic, Naida. "Study of triboelectric kinetic energy harvester with an asymmetric double variable capacitor implemented in a bennet doubler." Electronic Thesis or Diss., Université Gustave Eiffel, 2022. https://these.univ-paris-est.fr/intranet/2022/UEFL-2022/TH2022UEFL2072.pdf.
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La récupération de l'énergie est le processus qui consiste à convertir l'énergie inutilisée présente dans notre environnement en énergie électrique utilisable pour alimenter un système électronique. Les récupérateurs d'énergie cinétique à transduction électrostatique (eKEH) utilisent l'énergie cinétique présente dans l’environnement, qui provient d'un objet en mouvement ou de vibrations, afin de la convertir en énergie électrique. Le principe employé est basé sur un condensateur variable polarisé. En ajoutant une couche triboélectrique entre ses armatures et en créant un contact entre elles, un eKEH devient ce qui l’on appelle communément un nanogénérateur triboélectrique (TENG). Ce type de transducteur accumule des charges par contact dans la couche triboélectrique qui devient ainsi un électret dont le champs électrique semi-permanent généré permet une variation de la distribution des charges électriques dans les électrodes par induction électrostatique.La modification de l'architecture d'un TENG par l'ajout d'une troisième électrode permet de transformer un transducteur à capacité simple en un TENG à capacité double. Le fait de doubler l'élément de conversion dans un transducteur doit permettre d’augmenter la quantité d'énergie convertie. Le circuit électronique choisi pour redresser le signal obtenu en sortie du générateur est le doubleur de Bennet. L’absence de tension de saturation en sortie de ce circuit est une caractéristique particulière de cette pompe de charge dite instable. Elle se traduit par une augmentation exponentielle de la tension de sortie et des charges accumulées dans le condensateur de stockage qui augmentent (en théorie) de manière infinie. Cela signifie que la surface du cycle charge-tension aux bornes du TENG, et donc l’énergie convertie du domaine mécanique, augmente à chaque itération du cycle mécanique du transducteur.Cette thèse comprend l'analyse, la simulation et la démonstration expérimentale d’un doubleur de Bennet comportant deux capacités variables asymétriques incluant chacune une couche triboélectrique. Il est montré que les performances du système « double TENG » - « double Bennet » sont supérieures au doubleur de Bennet classique. L'étude analytique s'aligne sur les simulations. Le système a été testé expérimentalement. Il en est conclu que les résultats expérimentaux sont pertinents lorsqu'ils sont comparés aux performances du système classique d’un « TENG mono-capacitif » - « Bennet simple». Par rapport au doubleur de Bennet classique, le double Bennet atteint les mêmes niveaux de tension en moins de temps. Cela est dû à l'avantage du double condensateur TENG qui augmente le nombre de charges accumulées par cycle mécanique. L'analyse a montré que les deux condensateurs TENG sont co-dépendants et qu’ils s’influencent mutuellement lorsqu’ils sont mis en fonction.Le signal de sortie du double Bennet est caractérisé par des tensions élevées allant de plusieurs centaines à plusieurs milliers de volts. Pour abaisser la tension redressée en sortie à un niveau compatible avec une application commerciale, un convertisseur DC-DC de type Buck est implémenté. Celui-ci nécessite un interrupteur. Cette thèse propose et étudie l'utilisation d'un interrupteur haute-tension MEMS dit à micro-plasma dont la tension d’actionnement est définie par la loi de Paschen. Cette thèse se conclue par une étude théorique et expérimentale de cette loi à l'échelle micrométrique dans le but de proposer des tensions d’actionnement optimales pour une meilleure gestion de l'énergie captéeEnergy harvesting is the process that involves converting otherwise unused energy present in our environment into usable electrical energy that can be used to power an electronic system. Electrostatic kinetic energy harvesters (eKEHs) utilize vastly present kinetic energy that originates either from an object in motion or vibrations and converts it into electrical energy. The employed principle is based on a polarized variable electrostatic capacitor. With an addition of a triboelectric layer between its plates and utilizing the triboelectrification effect, an eKEH is transformed into a triboelectric nanogenerator (TENG). This type of transducer accumulates charges by contact in the triboelectric layer which thus becomes an electret whose generated semi-permanent electric field allows a variation of the distribution of the electric charges in the electrodes by electrostatic induction.Altering the architecture of a TENG by adding the third electrode, a single-capacitive transducer is converted into a double-capacitive TENG. Doubling the conversion element in a transducer is expected to increase the amount of converted energy. Chosen electronics circuit to condition obtained signal from the generator is Bennet’s charge doubler. An increase without saturation point at the output of this circuit is the unique characteristic of this unstable charge pump. It reflects through an exponential increase of output voltage and a number of charges accumulated in the storage capacitor which increase (in theory) in an infinite way. This means that the surface of the charge-voltage cycle at the terminals of the TENG, and thus the converted energy of the mechanical domain, increases at each iteration of the mechanical cycle of the transducer.The scope of this thesis encompasses the simulation, analytical and experimental research of Bennet’s charge doubler with two asymmetric variable capacitors each containing a triboelectric layer. It is postulated that the performance of the "double TENG" - "double Bennet" system is superior to the classic Bennet’s double. The results of analytical and simulation analysis have shown that the expected behavior of this circuit aligns with hypothesized performance results. The system has been tested experimentally. It is concluded that the results of the constructed system are relevant when compared with the reported performance of the classic "single-capacitive TENG" - "Bennet’s doubler" system.When compared with classic Bennet’s doubler, double Bennet reaches the same voltage levels in less time. That is due to the advantage of double capacitive TENG which increases the number of accumulated charges per mechanical cycle. In analytical analysis, it was found that the two TENG capacitors are codependent and that in operation they affect one another.The output signal of double Bennet is characterized by high voltages ranging from a few hundreds of volts to a few kilovolts (kV). To reduce the rectified output voltage to a level compatible with a commercial application, a Buck DC-DC converter is implemented. This requires a switch. This thesis proposes and studies the use of a high-voltage MEMS micro-plasma switch whose actuation voltages is defined by Paschen’s law. Within the scope of this thesis, the theoretical and experimental studies of this law at the micrometer scale propose optimal actuation voltages for better management of the converted energy
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Belfort, Diomadson Rodrigues. "Circuito de Condicionamento de Sinais Analógicos Programável para Sistemas Integrados." Universidade Federal do Maranhão, 2007. http://tedebc.ufma.br:8080/jspui/handle/tede/429.
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Previous issue date: 2007-09-05In digital measurement systems, signal conditioning circuits have the main functionality of adjusting analog signals for digital conversion. For maximizing the application of a measurement circuit or system, yet considering its integration in a single chip, these circuits must be programmable, in order to serve to different kinds of sensors with diverse output signal characteristics. The main functions of the signal conditioning circuit, in this case, are the amplification and dc level shift of the analog signal. In this master s thesis, an architecture of a signal conditioning integrated circuit with programmable gain and dc level shift, optimized in number of discrete components, using the switched capacitor technique is proposed. The proposed architecture allows the circuit use in differential and single-ended modes, with unipolar and bipolar signals. The design of an integrated circuit is carried out for implementing the proposed architecture using 0.35 mm TSMC CMOS technology, available in the ASIC design kit (ADK) of the Mentor Graphics, IC Nanometer software package.
Em sistemas digitais de medição, circuitos de condicionamento de sinais têm como principal finalidade o ajuste dos sinais analógicos para realização da conversão digital. Para maximização da aplicação de um circuito ou sistema de medição, considerando ainda sua integração em uma única pastilha, esses circuitos têm que ser programáveis, de forma a atender a diversos tipos de sensores com características de sinais de saída diversas. As principais funções do circuito de condicionamento, neste caso, são a amplificação e o ajuste de nível cc do sinal analógico. Nesta dissertação, propõe-se uma arquitetura de um circuito de condicionamento integrado com ajuste de nível cc e ganho programáveis, otimizada em número de componentes discretos, usando a técnica de capacitores chaveados. A arquitetura proposta permite a utilização do circuito nos modos diferencial e de terminação única, unipolar ou bipolar. Um projeto de um circuito integrado é realizado implementando a arquitetura proposta em tecnologia CMOS 0,35 mm TSMC, disponível no ASIC design kit (ADK) do pacote de programas da Mentor Graphics, IC Nanometer.
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Bidari, Emad. "Low-voltage switched-capacitor circuits." Thesis, 1998. http://hdl.handle.net/1957/33450.
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In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters.
Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown.Graduation date: 1999
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Hershberg, Benjamin Poris. "Ring amplification for switched capacitor circuits." Thesis, 2012. http://hdl.handle.net/1957/31112.
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A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification.Graduation date: 2012
Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013