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Relevant bibliographies by topics / Switched Capacitor Filter

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Dissertations / Theses

Academic literature on the topic 'Switched Capacitor Filter'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 June 2025

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Dissertations / Theses on the topic "Switched Capacitor Filter"

1

Lee, Sungah. "A zero-crossing switched-capacitor filter design." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44452.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Includes bibliographical references (p. 62).<br>Design of switched capacitor circuits in scaled CMOS technologies is becoming difficult because of low device intrinsic gain and reduced power supply voltage. To solve these problems, comparator-based switched-capacitor (CBSC) circuits and zero-crossing based circuits (ZCBC) were suggested as a possible solution to the op-amp based circuits. In this thesis, we explore zero-crossing based circuits (ZCBC) in high-order differential switched-capacitor filters to replace area inefficient op-amps-based continuous-time baseband filters. For the prototype for the zero-crossing based high-order switched capacitor filter, a low-pass ladder filter network will be used which is less sensitive to component variations. Several transformation steps from this low-pass passive ladder filter network to a differential high-order switched capacitor filter will be explored. To verify this architecture, SWITCAP will be used. And then ZCBC circuit implementation in Cadence will be explored.<br>by Sungah Lee.<br>S.M.

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2

Younis, A. T. "Design techniques for MOS switched capacitor ladder filters." Thesis, University of Essex, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234195.

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3

Wilbur, Mickey Joe D. "The VLSI implementation of a GIC switched capacitor filter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA346083.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1998.<br>Thesis advisor(s): Sherif N. Michael. "March 1998."--Cover. Includes bibliographical references (p. 141-142). Also available online.

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4

Lacy, Cameron. "Design of a programmable switched-capacitor analog FIR filter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ46200.pdf.

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5

Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.

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6

Oldland, Harry G. "The VLSI implementatoin of a GaAs GIC switched capacitor filter." Monterey, California. Naval Postgraduate School, 1997. http://hdl.handle.net/10945/9152.

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Approved for public release; distribution is unlimited<br>Presented is the initial step for the eventual implementation of a programmable GIC switched capacitor filter in a GaAs process. This thesis is the initial engineering effort in the accomplishment of this goal. The focus of this thesis is to design, fabricate, and test all necessary components for the construction of a GIC switched capacitor filter. All components will be stand alone so that future testing of each component may be accomplished. VLSI implementation will be accomplished using the Magic Cad package and the Vitesse HGaAs3 fabrication process. The simulation of the components will be accomplished using HSpice

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7

Nejadmalayeri, Amir Hossein. "CDMA Channel Selection Using Switched Capacitor Technique." Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/782.

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CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

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8

Hansmann, Chirstine Henriette. "Active capacitor voltage stabilisation in a medium-voltage flying-capacitor multilevel active filter." Thesis, Stellenbosch : University of Stellenbosch, 2005. http://hdl.handle.net/10019.1/1762.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.<br>A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

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9

Park, Joohwan. "Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter." Diss., Texas A&M University, 2005. http://hdl.handle.net/1969.1/4194.

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Phase locked loops (PLL) are used in a variety of RF integrated applications because of their ability to generate precise clock signals. These applications include clock recovery systems, frequency synthesizers and frequency multipliers. In order to achieve small size and low cost targets, the PLLs must be fully integrated on-chip with all the necessary components. Unfortunately, the filtering requirement for the low pass filter (LPF) demands a large silicon area, or the use of external capacitors. Moreover, high-density recording and high data rates for image transfer systems in wireless communication require more fully integrated LSI. The main goal of this study is to find area efficiency with fully on-chip design, and to provide a solution to improve the phase noise level without occupying a large area or using off-chip components. Moreover, to reduce the phase noise level, it is necessary to desensitize the VCO control when the loop is in the "lock zone". The introduced phase noise enhancement (PNE) will smartly reduce the phase noise without degrading the settling time by reducing the loop gain in the lock conditions.

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10

Hernandez, Garduno David. "Analog integrated circuit design techniques for high-speed signal processing in communications systems." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1104.

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