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Dissertations / Theses on the topic 'Switched Capacitor Filter'

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Published: 4 June 2021

Last updated: 6 September 2023

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1

Lee, Sungah. "A zero-crossing switched-capacitor filter design." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44452.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 62).
Design of switched capacitor circuits in scaled CMOS technologies is becoming difficult because of low device intrinsic gain and reduced power supply voltage. To solve these problems, comparator-based switched-capacitor (CBSC) circuits and zero-crossing based circuits (ZCBC) were suggested as a possible solution to the op-amp based circuits. In this thesis, we explore zero-crossing based circuits (ZCBC) in high-order differential switched-capacitor filters to replace area inefficient op-amps-based continuous-time baseband filters. For the prototype for the zero-crossing based high-order switched capacitor filter, a low-pass ladder filter network will be used which is less sensitive to component variations. Several transformation steps from this low-pass passive ladder filter network to a differential high-order switched capacitor filter will be explored. To verify this architecture, SWITCAP will be used. And then ZCBC circuit implementation in Cadence will be explored.
by Sungah Lee.
S.M.

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2

Younis, A. T. "Design techniques for MOS switched capacitor ladder filters." Thesis, University of Essex, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234195.

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3

Wilbur, Mickey Joe D. "The VLSI implementation of a GIC switched capacitor filter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA346083.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1998.
Thesis advisor(s): Sherif N. Michael. "March 1998."--Cover. Includes bibliographical references (p. 141-142). Also available online.

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4

Lacy, Cameron. "Design of a programmable switched-capacitor analog FIR filter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ46200.pdf.

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5

Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.

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6

Oldland, Harry G. "The VLSI implementatoin of a GaAs GIC switched capacitor filter." Monterey, California. Naval Postgraduate School, 1997. http://hdl.handle.net/10945/9152.

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Approved for public release; distribution is unlimited
Presented is the initial step for the eventual implementation of a programmable GIC switched capacitor filter in a GaAs process. This thesis is the initial engineering effort in the accomplishment of this goal. The focus of this thesis is to design, fabricate, and test all necessary components for the construction of a GIC switched capacitor filter. All components will be stand alone so that future testing of each component may be accomplished. VLSI implementation will be accomplished using the Magic Cad package and the Vitesse HGaAs3 fabrication process. The simulation of the components will be accomplished using HSpice

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7

Nejadmalayeri, Amir Hossein. "CDMA Channel Selection Using Switched Capacitor Technique." Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/782.

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CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

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8

Hansmann, Chirstine Henriette. "Active capacitor voltage stabilisation in a medium-voltage flying-capacitor multilevel active filter." Thesis, Stellenbosch : University of Stellenbosch, 2005. http://hdl.handle.net/10019.1/1762.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.
A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

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9

Park, Joohwan. "Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter." Diss., Texas A&M University, 2005. http://hdl.handle.net/1969.1/4194.

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Phase locked loops (PLL) are used in a variety of RF integrated applications because of their ability to generate precise clock signals. These applications include clock recovery systems, frequency synthesizers and frequency multipliers. In order to achieve small size and low cost targets, the PLLs must be fully integrated on-chip with all the necessary components. Unfortunately, the filtering requirement for the low pass filter (LPF) demands a large silicon area, or the use of external capacitors. Moreover, high-density recording and high data rates for image transfer systems in wireless communication require more fully integrated LSI. The main goal of this study is to find area efficiency with fully on-chip design, and to provide a solution to improve the phase noise level without occupying a large area or using off-chip components. Moreover, to reduce the phase noise level, it is necessary to desensitize the VCO control when the loop is in the "lock zone". The introduced phase noise enhancement (PNE) will smartly reduce the phase noise without degrading the settling time by reducing the loop gain in the lock conditions.

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10

Hernandez, Garduno David. "Analog integrated circuit design techniques for high-speed signal processing in communications systems." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1104.

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11

Bragina, Tatiana. "Návrh laditelného kmitočtového filtru 2. řádu se spínanými kapacitory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221041.

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Thesis describes analog filters topologies with capability of tuning of the main parameters and the MOSFET-C and switched-capacitor filters are described. With focus to linearity and maximal tuning range optimal topology have been chosen. In work the issue of analog switch design is described and is solved. Design of switched-capacitor low-pass Sallen-key filter in Cadence software was made and simulation results are presented.

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12

Třeček, Stanislav. "Aktivní elektrické filtry na bázi obvodů se spínanými kapacitory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217796.

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This thesis deals with concept of universal frequency filter by application of a switched-capacitor functional block. The concept is based on the theory of switched-capacitor circuits and the theory of a design of classical frequency filters. The printed circuit board was designed based on the filter connection developed by using a software Eagle. The filter was implemented as a laboratory product. This product has been revitalized and the frequency response of all types of filters has been measured. The measured parameters were compared with the parameters set out in the technical documentation of functional block.

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13

Harikumar, Prakash, and Pillai Anu Kalidas Muralidharan. "A Study on the Design of Reconfigurable ADCs." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867.

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Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

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14

Darwish, M. K. E.-S. "Switched-capacitor filters for power applications." Thesis, Brunel University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375203.

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15

Yassine, H. M. "Design and realization of switched capacitor filters." Thesis, London South Bank University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.618624.

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16

Yalkin, Cengiz. "Digitally controlled programmable active switched capacitor filters." Thesis, Monterey, California. Naval Postgraduate School, 1987. http://hdl.handle.net/10945/22244.

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17

Yassine, Hatem Mahmoud. "Design and realization of switched capacitor filters." Thesis, London South Bank University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.480856.

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18

Ribner, David B. (David Byrd) Carleton University Dissertation Engineering Electrical. "Design considerations for high-frequency switched-capacitor filters." Ottawa, 1985.

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19

Leonardi, Suryanto Felix 1958, and Suryanto Felix 1958 Leonardi. "Switched-capacitor network synthesis using leapfrog method." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/558107.

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20

Lindholm, John Erik. "A layout generator for stray insensitive switched capacitor filters." Thesis, University of British Columbia, 1986. http://hdl.handle.net/2429/26309.

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Two software programs have been developed to automatically generate the layout of stray insensitive switched capacitor filters. The first program, CIRCE, uses a SWITCAP filter description to generate an intermediate format filter description that is suitable for direct layout. It groups the filter elements into integrators and then sorts these integrators and their elements. The SWITCAP description can be with or without switch-sharing. The second program, SISCL, lays out the filter in CIF format using a double-polysilicon ISOCMOS process. The layout is done with a capacitor array placed over the switches and the standard-cell operational amplifiers placed beneath the switches. The layout is done with full switch-sharing. Capacitors may be rearranged in the intermediate file to produce better layouts. The software' is written in the C language.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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21

Serra, Hugo Alexandre de Andrade. "Design of switched-capacitor filters using low gain amplifiers." Master's thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8214.

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Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores
Analog filters are extremely important blocks in several electronic systems such as RF transceivers or sigma delta modulators. They allow selecting between signals with different frequency and eliminating unwanted signals. In modern deep-submicron CMOS technologies the intrinsic gain of the transistors is low and has a large variability, making the design of moderate and high gain amplifiers extremely difficult. The objective of this thesis is to study switched-capacitor (SC) circuits based on the low-pass and band-pass Sallen-Key topologies, since they do not require high gain amplifiers. The strategy used to achieve this objective is to replace the operational amplifier (opamp) with a voltage buffer. Doing this simplifies the design of the amplifier although it also eliminates the virtual ground node from the circuit. Without this node parasitic insensitive SC networks cannot be used. Due to modern parasitic extraction software that can reliably predict the values of parasitic capacitances, the historical disadvantage of parasitic sensitive SC networks (parallel SC) is no longer critical, allowing its influence to be compensated during the design process. Different types of switches were simulated to determine the one with the least nonlinear effects. Two techniques (common mode voltage adjustment and source degeneration) were used to reduce the distortion introduced by the buffers. Low-pass (second and sixth order) and band-pass (second and fourth order) SC filters were simulated in differential configuration in standard 130 nm CMOS technology, having obtained for the low-pass filter a distortion of -62 dB for the biquad section and -54 dB for the sixth-order filter, for a cutoff frequency of 1MHz and when operating at 100 MHz of clock frequency. The total power consumption was 986 W and 5.838 mW, respectively.

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22

Ng, Wai Hon. "Design of CMOS wide-band switched-capacitor bandpass filters /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20NG.

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23

Tumati, Sanjay. "Design of large time constant switched-capacitor filters for biomedical applications." Thesis, Texas A&M University, 2004. http://hdl.handle.net/1969.1/1479.

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This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

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24

Sun, Yi-Ran. "Generalized Bandpass Sampling Receivers for Software Defined Radio." Doctoral thesis, Stockholm, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4009.

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25

Uz, Eda. "Design And Implementation Of Thyristor Switched Shunt Capacitors." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12611616/index.pdf.

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This research work deals with the analysis, design and implementation of thyristor switched plain capacitor banks and thyristor switched shunt filter banks. Performances of various thyristor switched capacitor (TSC) topologies are also investigated by simulations. The theoretical findings have been verified by carrying out experimental work on two prototypes implemented within the scope of this research work, one is a wye-connected laboratory prototype and the other is a delta-connected application prototype integrated to some of the SVCs existing in Turkish Coal Enterprise s Plants. The advantages of back-to-back connected thyristor switches over conventional electromechanical contactors are also made clear by conducting an intensive experimental work in the laboratory. A good correlation have been obtained between theoretical and experimental results.

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26

Taylor, J. T. "Stability analysis and exact design of switched capacitor filters of the lossless discrete integrator type." Thesis, Imperial College London, 1985. http://hdl.handle.net/10044/1/37876.

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27

Zhao, Yao Hua. "Low-power high-linearity and area-efficient switched capacitor filters design techniques in nanoscale CMOS." Thesis, University of Macau, 2015. http://umaclib3.umac.mo/record=b3335858.

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28

Chunkag, Viboon. "Three-phase power-factor correction using single-switch and parallel connected switching converters." Thesis, University of Bath, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336239.

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29

Kaelin, August Kälin August N. Kälin August N. Kälin August N. "Contributions to the exact design of switched-capacitor filters with emphasis on modular structures and dynamic range /." [S.l.] : [s.n.], 1990. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9299.

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U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.

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Gercek, Cem Ozgur. "Optimizing Transient And Filtering Performance Of A C-type 2nd Harmonic Power Filter By The Use Of Solid-state Switches." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608836/index.pdf.

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In this research work, the performance of a C-type, 2nd harmonic power filter is optimized by the use of a thyristor switched damping resistor. In the design of conventional C-type, 2nd harmonic filters
the resistance of permanently connected damping resistor is to be optimized for minimization of voltage stresses on filter elements arising from switchings in transient state and for maximization of filtering effectiveness in the steady-state. Transformer inrush current during energization of power transformers and connection of filter bank to the supply are the major causes of voltage stresses arising on filter elements in transient state. These can be minimized by designing a highly damped C-type filter (low damping resistor) at the expense of inadequate filtering performance and high losses in the steady-state. On the other hand, higher damping resistance (high quality factor) is to be chosen in the design of C-type filter for satisfactory filtering of 2nd harmonic current component at the expense of higher voltage rating for capacitor bank and hence a more costly filter bank design. This drawback of conventional C-type 2nd harmonic filter circuit can be eliminated by subdividing damping resistor into two parallel parts
one is permanently connected while the other is connected to and disconnected from the circuit by back-to-back connected thyristor assemblies. The use of light triggered thyristors provides isolation between power stage and control circuit, and hence allows outdoor installation.

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U, Seng-Pan. "多率開關電容內插技術及其在超高頻模擬前端濾波的應用." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1637078.

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Chan, Yan Fong Joseph Yves. "Etude et réalisation de structures CMOS analogiques pour application haute fréquence." Grenoble INPG, 1989. http://www.theses.fr/1989INPG0056.

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Ce travail a pour but d'etudier les problemes associes a la realisation de circuits cmos analogiques destines a des applications haute frequence (freq. Echant. Sup. Un mhz). La premiere partie traite de la modelisation dynamique du transistor mos. La caracterisation du tmos en hf a l'aide des parametres s a permis de valider un modele petit signal valable pour des frequences atteignant les quelques ghz. La deuxieme partie examine les principaux problemes associes aux structures echantillonnees, telles les capacites commutees (cc). Le probleme de l'injection de charges a pu etre quantifie pour differents interrupteurs par des mesures experimentales. La derniere partie traite de l'amplification et du filtrage a cc a haute frequence. Un filtre elliptique d'ordre cinq a cc, utilisant le principe du double echantillonnage et des nouvelles structures d'interface a ete concu dans une technologie cmos 2

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34

Urban, Lukáš. "Laboratorní úloha zaměřená na obvody se spínanými kapacitory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217788.

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This Master`s thesis is focused on through acquaintance of principles of the function circuits with switched capaticors and posibility of their application mainly in frequency filters or signal generators. The origin of the switched capacitor circuits is mentioned at the beginning of the work. There are references to the first scientific work and scientists who have dealt with this issue. Maxwell`s idea: lossy element (resistor) replace with lossless element (switched capacitor) in electric circuit, is further described. In the next chapter of this work are listed types of switching capacitors and their use in simple RC filters and in structures of inverted or noninverted integrators and their application in more complex higher order filters. The advantages and disadvantages of SC circuits versus circuit composed of discrete components are shown. It is also listed a simple low-pass switched RC filter implemented with analogue multiplexer 4053. Using the LTC1043 integrated circuit, which structure and properties are described and analyzed in detail in the work, the 1st order aktive or pasive low and high pass filters were designed and subsequently simulated in the computer simulator OrCAD PSpice v.10. Another chapter deals with the integrated circuits higher order filters, structure and properties of the integrated filter LTC1060 are further analyzed here. Except this IC there are mentioned integrated filters commercially less available from the corporations Linear Technology and Maxim. The main objective of thesis was to propose and establish laboratory device and laboratory measurment focused on the switched capacitor circuits. The laboratory device has been designed with integrated circuits LTC1043 and LTC1060, which is demonstrated by using passive and active integrator, 2nd order band-pass and 4th order band-pass with Chebyshevovou approximation.

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35

陳學平. "= Design of low power switched opamp for switched capacitor filter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/51394520851577343763.

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Huang, Ren-Bin, and 黃任彬. "Switched-Capacitor Bandpass Filter for ECG Application." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/06285315357583840803.

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碩士
龍華科技大學
電機工程系碩士班
101
Large resistors is achieved in the integrated circuits is difficult, because the area of integrated circuits will be occupied by the large resistors. Switched capacitor is used to achieve the a much reduced area and using the tools of MOS technology, one can discover that switches, small-value capacitors, and decent op-amps are easy enough to realize in MOS technology. A fully integrated switched-capacitor bandpass filter is presented in this paper. The band-pass filter is composed by a high-pass and low pass filter. The passband of the filter is 0.05Hz-150Hz which is suited for ECG signal application. The notch filter is designed in order to suppress the 60Hz induced noise. This circuit is design with TSMC 0.35μm process

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WANG, QI-CHUAN, and 王啟川. "The automation of switched capacitor filter design." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/69276652876465299030.

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Tsai, Yung Ming, and 蔡泳銘. "1-V Switched-Capacitor Bandpass Filter for Wireless Bidirectional Microstimulator." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/97675824059938673389.

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碩士
南台科技大學
電子工程系
91
This thesis proposed a 1-V switched-capacitor bandpass filter for wireless bidirectional microstimulator. The operation amplifier used in the filter is the switched- opamp. The advantage of the switched-opamp is that it can turn off its power during un-working cycle. The most concern of the microstimulator is the power problem. The proposed filter we proposed can solve power problems due to its 1-V operation，and using switched-OPAMP technique. The frequency region of nerve signal is 250Hz to 5KHz, therefore the frequency rang has been adopted to accomplish the design of 6th order Bessel filter. The conventional architecture of 1-V switched-opamp has been discussed in this thesis. We found that the level-shifter is sensitive to the bias point. Furthermore, We proposed a new technology to overcome this problem. The proposed 1-V switched-opamp has the advantages of higher DC stability and AC gain as compared with conventional architecture. The proposed switched-opamp is also employed in bandpass filter. The bandpass filter adopts the low-Q SC biquad filter architecture. By way of proper modified phase, the number of operation amplifier operating at the same time can be reduced from 6 to 3,and saving a large amount of power. The bandpass filter has been implemented by using TSMC 0.25μm 1P5M Mix-signal process. It has sampling frequency of 125KHz, passband region from 250Hz to 5KHz, supply voltage of 1V, power consumption of 402uW, peak signal to noise ratio of 39dB and dynamic more then 100dB.

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HUANG, SHOU-YUAN, and 黃守源. "A single-path frequency-translated switched-capacitor bandpass filter system." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/14393146842032014858.

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40

SUN, LI-XING, and 孫利興. "A Mandarin four-tone recognition system using a switched-capacitor filter." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/75949368850263020354.

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41

Chiu, Chuang-Yu, and 邱創郁. "Design of Automatic-Frequency-Tuning Filter Based on Switched-Capacitor Techniques." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/a46hgm.

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碩士
國立臺北科技大學
電腦與通訊研究所
98
The major research of this thesis can be divided into two sections. The proposed tunable Butterworth filter utilizes the switched-capacitor techniques in first section. This thesis utilizes operational transconductance amplifier as the voltage-mode active elements. Therefore, according to the linear transformation, high-order active low pass filter is achieved. Therefore, the bandwidth is tuned by the duty cycle of control switches. The proposed circuit is fabricated by TSMC 0.18μm 1P6M CMOS process. The tunable bandwidth of filter is from 5MHz to 20MHz. The power consumption is 12.3mW, and the chip area without I/O PADs is 0.45mm×0.4mm. This thesis designs an automatic-frequency-tuning system in second section. A fourth-order tunable Butterworth filter is designed by the switched-capacitor techniques. The filter bandwidth is tuned by the duty cycle of control switches. In order to avoid process variation, the on-chip automatic-frequency-tuning system is also designed to compensate the bandwidth variation. The conventional automatic-frequency-tuning system employs the master-slave scheme to control the filter frequency; however the proposed system uses a single switched-capacitor filter to tune the bandwidth. The proposed circuit is fabricated by TSMC 0.18μm 1P6M CMOS process. The tunable bandwidth of filter is from 1MHz to 4MHz. The power supply and power consumption are 1.8V and 15.2mW, respectively. The chip area without I/O PADs is 0.57mm×0.5mm.

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Hsieh, Cheng-Hsun, and 謝政勳. "SWITCHED-CAPACITOR FILTER DESIGN THROUGH BILINEAR TRANSFORM BY USING MULTIPLEXING TECHNIQUE." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/20205266580303779297.

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碩士
大同工學院
電機工程學系
84
In the thesis, a new Switched-Capacitor (SC) filter design methodologyuseing multiplexing technique is proposed to realize arbitrary high-order filter.Using the bilinear transformation, filters including lowpass,bandpass, highpass can implemented by various combination of four basic function SC circuits. Because of the efficient use of multiplexing techniques, the realized high-order filters have less op-amps, switches,capacitors, and smaller chip area, but at the cost of increasing clockphases. Eighth-order Butterworth lowpass, bandpass, and highpass filter design examples are presented to demonstrate how to apply the proposed method to design the high-order filters. The proposed circuits are simulated with SWITCAP. Computer simulation result verified the functioncorrectness and the performance of the proposed design method.

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Lin, Chie-Pon, and 林頎鵬. "Design of Switched-Capacitor Tunable Filter with New Automatic Tuning Method." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/3a48c2.

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碩士
國立臺北科技大學
電腦與通訊研究所
97
In this thesis, we design a switched-capacitor tunable filter for biomedical systems. The low transconductance OTAs implement a fourth-order Butterworth filter. The bandwidth is achieved through the use of duty cycle controlled tuning. In order to reduce the non-ideal effect of switch, therefore the filter uses fully differential architectures. Moreover, the Gm-C filter with on-chip automatic tuning is without master-slave scheme. The scheme of automatic tuning is direct tuning the Gm-C filter and employs a phase-locked loop (PLL). Physical chip was fabricated by using TSMC 0.18 um 1P6M CMOS process. The tunable bandwidth of filter is about 150 Hz to 250 Hz. The power supply and the power consumption are 1 V and 16.7 uW, and the chip area without I/O PAD is 1.1174 mm2.

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44

Chiang, Chih-He, and 江志和. "1-V Low-Power Switched-Capacitor Bandpass Filter For Micro-Stimulator System." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/59101184540768856307.

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碩士
國立中正大學
電機工程所
93
This thesis proposed a 1-V switched-capacitor bandpass filter for nerve micro-stimulator. The operational amplifier used in the filter is the switched opamp. The advantage of the switched opamp is that it can turn off its output stage power during off-state cycle. This is helpful to the low-power design of micro-stimulator. Because the most concern of the micro-stimulator is power dissipation. The proposed filter can save more power due to adopting switched opamp technique in 1-V operation. The frequency region of nerve signal is from 250Hz to 5kHz, therefore the frequency rang has been adopted to accomplish the design of 6th order Bessel filter. The bandpass filter with the low-Q SC biquad filter architecture is presented in this thesis. By way of proper modified phase, the number of operation amplifier operating at the same time can be reduced from 6 to 3, and saving a large of power. The bandpass filter chip has been implemented by using TSMC 0.18μm 1P6M Mixed Signal process. In the sampling frequency of 125kHz, and passband region from 250Hz to 5kHz, the total power consumption is 315μW under a single 1-V supply voltage, the measured peak signal to noise ratio is 57dB, and dynamic range is about 60dB.

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LI, KAI-HUI, and 李開懷. "Analysis and recognition of Mandarin word speech using single switched-capacitor filter." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/00654724182631831602.

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Wu, Zhih-Zhong, and 吳志中. "Automatic Synthesis Flow For Noise Level Of Switched-Capacitor Low-Pass Filter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/74042396559401100540.

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碩士
國立雲林科技大學
電子工程系
104
Due to the technological markets are prosperous development in recent years. Technology companies hope to release new products at short time. Therefore, in order to rapidly satisfy this goal. It compress the time that the engineers design circuits. This thesis proposed an automatic synthesis flow tool to aim at the noise of switched-capacitor low pass filter. First, to analyze the input’s sepcifications based on the noise model. If the specifications are not reasonable, the tool will go back to the user interface and imply user to input specifications again. If the specifications is reasonable, the tool starts analysis, if the simulation results reached the required specifications, the whole design procedures would be done; if it didn’t reach the specification requisitions, applies the Genetic Algorithms(GA) proposed by this thesis, and automatic adjusts the value of circuit parameters of noise model, until the specification are reached. The automatic synthesis tool are operated on Linux operating system. Then collect the noise specifications of users and transmit to noise model by C language, and compute corresponding circuit parameters. Finally, tool analyzes circuit performances by circuit simulation tool Hspice. If the simulation results does not meet specifications, it will repeatedly execute loop to simulation results qualifications. This automatic synthesis tool of this thesis, using Tool Command Language (Tcl) to call the C language and Hspice to execute analysis work, and cascade with Tcl to adjust parameters to realize circuit synthesis between each of the procedures. Keyword ： Switched-capacitor low pass filter, Noise model, Automatic synthesis flow, Tool command language (Tcl), Noise specifications, Circuit parameters

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Chen, Jyun-Yu, and 陳俊宇. "Design of Switched-Capacitor Filter With Automatic Tuning Using Delay-Locked-Loop Techniques." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/98gkct.

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碩士
國立臺北科技大學
電腦與通訊研究所
98
The major research of this thesis can be divided into two parts. The first part, a high-order active mixed-mode low pass filter is based on CCCDTA (Current Controlled Current Differencing Transconductance Amplifier ; CCCDTA). It is synthesized by linear transformation. The mixed-mode filter consists of the voltage-mode, transresistance-mode, current-mode, and transconductance-mode, respectively. By using this technique, it has advantages which include systematic design procedures, simple design equations, minimum active elements, without any resistors and using grounded capacitors. If the filter is design by nth-order, it only need n active elements and n capacitors to achieve mixed-mode filter. The high-order active mixed-mode low pass filter is implemented in a TSMC 0.18μm 1P6M CMOS process, the bandwidth of filter is 5MHz and the power consumption is 2.094mW with ±0.9V power supply. The chip area is 0.12mm × 0.23mm without I/O PADs. The second part designs an automatic tuning system using switched-capacitor tunable filter. The cut-off frequency of filter can be tuned by the varied duty cycle. According to process and temperature variation, the cut-off frequency of filter will be influenced. Therefore, the proposed automatic tuning system can improve these problems. By this technique, it can calibrate the cut-off frequency to achieve higher accuracy of filter. The proposed automatic tuning system is suitable to control the bandwidth of switched-capacitor filter, and the process variation and accuracy of filter can be improved by this system. To compare this automatic tuning method with conventional counter or other digital circuits, this method has the advantage of higher resolution. The automatic tuning system is implemented in a TSMC 0.18μm 1P6M CMOS process. The bandwidth of tunable filter is from 1.5MHz to 5MHz. The power consumption is 6.65mW with ±0.9V power supply, and the chip area is 0.58mm × 0.43mm without I/O PADs.

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Tsai, Ming-Shiung, and 蔡明訓. "A High Order Switched Capacitor A/D Converter Based on Butterworth Filter Implementation." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/09411637481218690233.

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碩士
國立高雄大學
電機工程學系碩士班
95
In this thesis, we present a fourth-order cascade-of-integrators feedback Sigma-Delta A/D converter. We use Oversampling and Noise-Shaping techniques to earn a higher resolution than that in the Nyquist-Rate A/D converters. A generic method is presented to make the system stabilized. In order to fix the zeros and poles in the unit circle, we use MATLAB to design the Butterworth high pass filter, and then the coefficients could be obtained. We present a complete design flow to decrease the time of the design. By applying this method, a fourth-order Sigma-Delta A/D converter is implemented by TSMC 0.35 μm 2P4M Mixed-Signal Polycide process provided by National Chip Implementation Center. The circuit specification is as follows: the supply voltage is 3.3 V, the sampling rate is 256, the signal bandwidth is 20k Hz, the working frequency is 10.24Meg Hz, an SNR, 75.7dB is attained, and the total power consumption is 20.3 mW.

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49

Serra, Hugo Alexandre de Andrade. "Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies." Doctoral thesis, 2017. http://hdl.handle.net/10362/30792.

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Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB.

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50

袁成宇. "A High Bandwidth Switched-capacitor Low-pass Filter and Built-in-self-test Circuit." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/skzp4w.

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碩士
國立交通大學
電機與控制工程系所
92
As IC fabrication technology advances in recent years, faster and more complex test equipments are required to achieve test specifications and test functions. An innovative method to simplify the test equipment is to move test functions onto the chip itself, which is called Built-In-Self-Test (BIST). How to achieve on-chip test function with limited area and power overhead is the main issue for mixed-signal testing designers. In this thesis, we accomplish a fully-differential, 140 MHz sampling frequency, 10 MHz corner frequency, switched-capacitor 4th-order low-pass filter to be the core circuit, which consists of two cascading biquad filters. Besides, we use the concept about probabilities of a triangular-wave to implement BIST circuits for the SC filter. In our BIST circuit, it consists of a 29.2 KHz triangular oscillator taken as test-waveform-generator, a differential-to-single-ended circuit and a dual-comparator taken as output-response-analyzer. According to this approach, we can obtain the information on gain error and offset error of each biquad filters from test results.

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