Dissertations / Theses on the topic 'Switching circuits. Pulsed power systems'

Thesis (M.S.) University of Missouri-Columbia, 2005.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (July 10, 2006) Includes bibliographical references.

This thesis illustrates a typical situation in which theoretical considerations and predictions are used to enhance the value of an experimental investigation. The body of the thesis is in two main parts, the first of which considers the two-dimensional modelling of representative pulsed-power systems while the second describes a number of valuable experimental tools that were developed for use in investigating the experimental behaviour of such systems.

Near-field wireless power transfer (WPT) technology facilitates the energy autonomy of heterogeneous systems, significantly augmenting complementary metal-oxide-semiconductor field-effect-transistor (CMOS) technology. In low-power wearable devices, existing power conditioning integrated circuits do not maximize the power factor (PF) for rectification and power conversion efficiency (PCE) due to multiple conversion. Additionally, there is no core power management for the entire power flow. The majority of the research focuses on active rectifiers, which reduce the turn-on voltage for rectification. Certain studies target the output voltage regulation via feedback to the transmitter or direct battery charging without power maximization. Firstly, this study investigates a high-power factor WPT front-end circuit that is namely the mono-periodic switching rectifier (MPSR) and implemented in a 0.18µm 1.8V/5V CMOS process. Integrated phase synchronizers are used to align the waveshape of a wirelessly-coupled sinusoidal voltage source in a receiving coil to the corresponding conducting current. Using this approach, the PF can be increased from roughly 0.6 to unity without requiring any wireless or wired feedback to the transmitter. The proposed MPSR can also provide AC-DC rectification, and step up and down the sinusoidal voltage source's peak amplitude using a pulse-width modulator. Measured voltage conversion ratios range between 0.73X and 2X, and the PF can be boosted up to unity. Secondly, the wireless power system-on-chip (WPower-SoC) is proposed and implemented in a 0.18µm 1.8V/3.3V CMOS process. The WPower-SoC integrating power management can provide rectification, output voltage regulation, and battery charging. Additionally, the implementation of feedforward envelope detection (FED) can reduce the variation in a wireless power link and improve load transient responses. Simulated results demonstrate that 5% of the output voltage regulation is improved when an output load changes. Moreover, the FED reduces approximately 40% of the transient response time. Overshoot and undershoot voltages are decreased by 23% and 26.5%, respectively. The measured output voltage regulates at 3.42V and can supply output power up to 342mW. A temperature sensor as part of the power management core remains active when the WPT receivers enter sleep mode to prolong the battery usage time. In the final part of this study, a nano-watt high-accuracy temperature sensing core is implemented in a 0.18µm 1.8V/3.3V CMOS process that can self-compensate the temperature shift without the need for additional compensating techniques that consume extra power.

The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Title from PDF of title page (University of Missouri--Columbia, viewed on October 5, 2009). Thesis advisor: Dr. Scott Kovaleski. Includes bibliographical references.

Thesis (M.S.)--University of Missouri-Columbia, 2007.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on March 18, 2008) Includes bibliographical references.

In low power, battery-operated, portable applications, like cell phones, PDAs, digital cameras, etc., miniaturization at a low cost is a prominent driving factor behind product development and marketing efforts. As such, power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because, in catering to all combinations of the output capacitor, its equivalent series resistance Resr, and the power inductor resulting from tolerance and modal design targets, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios. Sigma-delta control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide LC-Resr compliance in boost (step-up) converters. This thesis investigates and presents techniques to achieve sigma-delta control in boost converters by essentially using explicit current and voltage control loops. The proposed techniques are developed conceptually and analytical expressions for stability range and transient response are derived. The proposed concepts are validated and quantified through PCB and IC prototypes to yield 1.41 to 6 times faster transient response than the state of the art in current-mode boost supplies, and this without any compromise in LC-Resr compliance range.

The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Title from PDF of title page (University of Missouri--Columbia, viewed on September 24, 2009). Thesis advisor: Dr. Scott Kovaleski. Includes bibliographical references.

PV Inverters have the task of tracking the maximum power point (MPP), and regulating the solar energy generation to this optimal operation point. The second task is the conversion of direct current produced by the solar modules into alternating current compatible with the grid. A new inverter approach such as a single phase micro inverter is emerging aimed to overcome some of the challenges of centralized inverters. As a counterpart to the central inverter, a micro inverter is a small compact module attached directly to each solar panel. To provide for the constantly increasing demand for a small size, light weight and high efficiency micro inverter, soft switching power conversion technologies have been employed. The switching stress can be minimized by turning on/off each switch when the voltage across it or the current through it is zero at the switching transition. With the addition of auxiliary circuits such as auxiliary switches and LC resonant components the so called soft switching condition can be achieved for semiconductor devices. Four main purposes to investigate the soft switching technologies for single-phase micro-inverter are: (1) to improve overall efficiency by creating the favorable operating conditions for power devices using soft-switching techniques; (2) to shrink the reactive components by pushing the switching frequency to a higher range with decent efficiency. (3) to ensure soft switching does not exacerbate inverter performance, meaning all conventional PWM algorithms can be applied in order to meet IEEE standards. (4) to investigate which soft switching techniques offer the cheapest topology and control strategy as cost and simple control are crucial for low power inverter applications. An overview on the existing soft-switching inverter topologies for single phase inverter technology is summarized. A new quasi resonant DC link that allows for pulse- width- modulation (PWM) is presented in this thesis. The proposed quasi resonant DC link provides zero-voltage switching (ZVS) condition for the main devices by resonating the DC-link voltage to zero via three auxiliary switches and LC components. The operating principle and mode analysis are given. The simulation was carried out to verify the proposed soft switching technique. A 150W 120VAC single-phase prototype was built. The experimental results show that the soft switching for four main switches can be realized under different load conditions and the peak efficiency can reach 95.6%. The proposed quasi DC link can be applied to both single-phase and three-phase DC/AC micro inverter. In order to boost efficiency and increase power density it is important to evaluate the power loss mechanism in each stage of operation of the micro inverter. Using the datasheet parameters of the commercially available semiconductor switches, conduction and switching losses were estimated. This thesis presents a method to analyze power losses of the new resonant DC link inverter which alleviates topology optimization and MOSFET selection. An analytical, yet simple model for calculating the conduction and switching losses was developed. With this model a rough calculation of efficiency can be done, which helps to speed up the design process and to increase efficiency.
ID: 031001282; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Issa Batarseh.; Co-adviser: John Shen.; Title from PDF title page (viewed February 26, 2013).; Thesis (M.S.E.E.)--University of Central Florida, 2012.; Includes bibliographical references (p. 76-80).
M.S.E.E.
Masters
Electrical Engineering and Computing
Engineering and Computer Science
Electrical Engineering

Les travaux de cette thèse portent sur l’analyse de stabilité et la synthèse de commandes robustes pour les systèmes affines à commutation en temps continu en présence d’incertitudes paramétriques constantes. On propose deux méthodes de commande permettant de garantir la stabilité asymptotique globale des systèmes affines à commutation avec paramètres inconnus. La première approche est basée sur l’estimation des paramètres inconnus et la reconstruction de l’état d’équilibre associée pour permettre d’appliquer une commande robuste adaptative. La seconde méthode est basée sur une augmentation d’état par l’ajout d’une action intégrale dans la boucle de commande qui garantit une erreur statique nulle. Pour chaque approche, deux lois de commande sont proposées. Une méthode du type « min switching » qui sélectionne la commutation la plus apte à stabiliser le système et une méthode de type « Embedded » permettant de générer une commande polytopique des différents modes possibles. Les résultats sont appliqués aux convertisseurs de puissance de topologie Flyback avec preuve de stabilité dans les deux modes de conduction (continue et discontinue)
This PhD thesis is focused on stability analysis and robust control synthesis for continuous time switching affine systems in presence of constant parametric uncertainties. Two control methods are proposed to guarantee global asymptotic stability of switching affine systems with unknown parameters. The first approach is based on the estimation of the unknown parameters and the reconstruction of the related equilibrium state to allow the application of a robust adaptive control. The second method is based on a state augmentation by adding an integral action in the control loop that guarantees a null steady state error. For each approach, two control laws are proposed. A "min switching" method that selects the most suitable mode to stabilize the system and an "Embedded" method that generates a polytopic control of the different possible modes. The results are applied to Flyback topology power converters with proof of stability in both conduction modes (continuous and discontinuous)

Revue des propriétés des thyristors interrupteurs. Aptitude à l'utilisation en grande traction. Etude du rétablissement de la tension aux bornes. Soufflage et mise en série des thyristors interrupteurs. Caractérisation des GTO de grande puissance.

Power supply noise, which is the variation in the supply voltage across the on-die supply terminals of VLSI circuits, is a serious performance degrader in digital circuits and mixed analog-digital circuits. In digital VLSI systems, power supply noise causes timing errors such as delays, jitter, and false switching. In microprocessors, power supply noise reduces the maximum operating frequency (FMAX) of the CPU. In mixed analog-digital circuits, power supply noise manifests as the substrate noise and impairs the performance of the analog portion. The decrease in the available noise margin with the decrease in the feature size of transistors in CMOS systems makes the power supply noise a very serious issue, and demands new methods to reduce the power supply noise in sub-micron CMOS systems. In this thesis, we develop a new method to determine optimal time-delays between the switching of input/output (I/O) data buffers in digital VLSI systems that realizes maximum reduction of the power supply noise. We first discuss methods to characterize the distributed nature of the Power Delivery Network (PDN) in the frequency-domain. We then develop an analytical method to determine the optimal delays using the frequency-domain response of the PDN and the supply current spectrum of the buffer units. We explain the mechanism behind the cancellation of the power supply noise by the introduction of optimal buffer-to-buffer delays. We also develop a numerical method to determine the optimal delays and compare it with the analytical method. We illustrate the reduction in the power supply noise by applying the optimal time-delays determined using our methods to two examples of PDN. Our method has great potential to realize maximum reduction of power supply noise in digital VLSI circuits and substrate noise in mixed analog-digital VLSI circuits. Lower power supply noise translates into lower cost and improved performance of the circuit.

Indiana University-Purdue University Indianapolis (IUPUI)
The existing topologies of solar micro inverter use a number of stages before the DC input voltage can be converted to AC output voltage. These stages may contain one or more power converters. It may also contain a diode rectifier, transformer and filter. The number of active and passive components is very high. In this thesis, the design of a new solar micro inverter is proposed. This new micro inverter consists of a new single switch inverter which is obtained by modifying the already existing single ended primary inductor (SEPIC) DC-DC converter. This new inverter is capable of generating pure sinusoidal waveform from DC input voltage. The design and operation of the new inverter are studied in detail. This new inverter works with a controller to produce any kind of output waveform. The inverter is found to have four different modes of operation. The new inverter is modeled using state space averaging. The system is a fourth order system which is non-linear due to the inherent switching involved in the circuit. The system is linearized around an operating point to study the system as a linear system. The control to output transfer function of the inverter is found to be non-minimum phase. The transfer functions are studied using root locus. From the control perspective, the presence of right half zero makes the design of the controller structure complicated. The PV cell is modeled using the cell equations in MATLAB. A maximum power point tracking (MPPT) technique is implemented to make sure the output power of the PV cell is always maximum which allows full utilization of the power from the PV cell. The perturb and observe (P&O) algorithm is the simplest and is used here. The use of this new inverter eliminates the various stages involved in the conventional solar micro inverter. Simulation and experimental results carried out on the setup validate the proposed structure of inverter.

Indiana University-Purdue University Indianapolis (IUPUI)
This thesis presents a converter topology for photovoltaic panels. This topology minimizes the number of switching devices used, thereby reducing power losses that arise from high frequency switching operations. The control strategy is implemented using a simple micro-controller that implements the proportional plus integral control. All the control loops are closed feedback loops hence minimizing error instantaneously and adjusting efficiently to system variations. The energy management between three components, namely, the photovoltaic panel, a battery and a DC link for a microgrid, is shown distributed over three modes. These modes are dependent on the irradiance from the sunlight. All three modes are simulated. The maximum power point tracking of the system plays a crucial role in this configuration, as it is one of the main challenges tackled by the control system. Various methods of MPPT are discussed, and the Perturb and Observe method is employed and is described in detail. Experimental results are shown for the maximum power point tracking of this system with a scaled down version of the panel's actual capability.

Indiana University-Purdue University Indianapolis (IUPUI)
This research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.